JPH02172228A - Method of forming multilayer wiring - Google Patents

Abstract

PURPOSE:To avoid flaws in a lower layer aluminum system wiring caused by stress migration by a method wherein, after a stress relief film and a silicon nitride film are successively formed on the lower layer aluminum system wiring, a levelling film is formed and then the surface is levelled by etching back. CONSTITUTION:A plasma silicon nitride film 5 formed directly on an aluminum wiring film 4 is a thin film with a thickness about 1000Angstrom . A thick silicon nitride film 7 is formed on a PSG film 6, which is a stress relief film. The stress between the aluminum wiring film 4 and the plasma silicon nitride film 7, therefore, is absorbed by the PSG film 6. With this constitution, stress migration and flaws in the aluminum wiring caused by the stress migration can be avoided.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B0 Overview of the invention C0 Prior art [Fig. 4 D1 Problem to be solved by the invention [Fig. 5] E3 Means for solving the problem F9 Effect G. Examples [Fig. 1 to 3] H0 Effects of the Invention (A, Industrial Field of Application) The present invention relates to a method for forming a multilayer interconnection, and particularly to a method for forming a multilayer interconnection including a step of planarizing an interlayer insulating film.

(B. Summary of the Invention) The present invention, in a method for forming multilayer wiring, is designed to prevent chipping of the lower layer aluminum-based wiring due to stress migration margins, which occurs during planarization of the interlayer insulating film. After sequentially forming a stress relaxation film and a silicon nitride film on the aluminum-based wiring, a planarization film is formed, and the planarization is then performed by filling planarization 1 and etching back the silicon nitride film.

(C, Prior Art) [Figure 4] As ICs, LSIs, and VSLIs become more highly integrated, aluminum-based interconnects such as aluminum or silicon-containing aluminum alloys become multilayered, and the importance of multilayer interconnection formation technology increases. It is better to increase. By the way, when increasing the number of layers of aluminum-based wiring, it is necessary to prevent disconnection of the L-layer wiring. This is because the surface of the interlayer M film of multilayer wiring is uneven due to the lower layer wiring, and the upper layer aluminum wiring film is formed on the uneven surface. This is because it becomes easy to cause breakage. Therefore, a planarization technique has been developed in which the surface of the interlayer insulating film is planarized and an upper layer of aluminum interconnection 15AI'E1 is formed on the planarized surface. Various technical proposals have been made regarding this.

FIGS. 4A to 4F are cross-sectional views showing one of the conventional planarization methods in the order of steps.

(A) An aluminum wiring film C containing 1% silicon is formed on the base a with a barrier layer interposed therebetween. FIG. 4<A) shows the state after the aluminum wiring ■qC is formed.

Note that the barrier layer has a two-layer structure of a titanium film and a titanium nitride film or a titanium oxynitride film.

(B) Next, as shown in the same figure (B), a plasma silicon nitride film (thickness: 7500 mm) d is formed.

(C) Next, a resist film e is formed as shown in (C) of the same figure. The resist J12e can be formed to have a flat surface and has an etching rate approximately equal to that of the plasma silicon nitride film d, so it is formed for flattening by etchback.

CD3 Next, the resist 1 and the plasma silicon nitride film d are etched back until the surface of the aluminum wiring film C is exposed or almost exposed, as shown in FIG. 3(D).

(E) Next, as shown in the same figure (E), for example, 1000
~2000 thin plasma silicon nitride IIQ f is formed. This silicon nitride film f
is formed because it has the effect of preventing the formation of hillocks.

(F) Next, as shown in the same figure (F) km, psa+p;
form ig. As a result, interlayer insulating films d, f, and g are formed, and an upper aluminum wiring film is formed on the PSGllQg. Such planarization technology was originally applied to multilayer wiring technology that does not provide a barrier layer, but in recent multilayer wiring technology, it has become common to provide a barrier layer under an aluminum-based wiring film. Therefore, if planarization technology is applied to the method of forming multilayer wiring with a barrier layer, the method shown in FIG. 4 will be obtained.

(D. Problem to be solved by the invention) [Fig. 5] By the way, according to the method shown in Fig. 4, the surface of the interlayer insulating film can certainly be flattened, but As shown in the figure, there was a problem in that a wedge-shaped chip h occurred. Such a problem occurred particularly when the barrier layer was formed as a base for the aluminum wiring film C1C.

The occurrence of such chipping h in the aluminum wiring &*MC causes wire breakage, etc., resulting in a decrease in reliability. When we investigated the cause of this problem, we found that about 70,000, for example, 70,000
It has been found that stress migration occurs when a relatively thick plasma silicon nitride film is formed.

The present invention has been made to solve these problems, and its object is to prevent chipping due to stress migration of the aluminum wiring in the lower layer, which occurs during planarization of an interlayer insulating film.

(E. Means for Solving the Problems) In order to solve the above-mentioned problems, the method for forming a multilayer wiring of the present invention sequentially forms a stress relief film and a silicon nitride film on the lower layer aluminum-based wiring, and then flattens the wiring. 119 and then flattened by ivy.

(F. Effect) According to the method for forming a multilayer wiring of the present invention, since a stress relaxation film is formed on the aluminum-based wiring, stress can be absorbed by the stress relaxation film. Therefore, stress migration can be prevented, and furthermore, chipping of the aluminum-based wiring due to stress migration can be prevented.

(G, Embodiment) [FIGS. 1 to 3] Hereinafter, a method for forming a multilayer wiring according to the present invention will be explained in detail according to the illustrated embodiment.

FIGS. 1(A) to 1(G) are cross-sectional views showing one embodiment of the method for forming a multilayer wiring according to the present invention in the order of steps.

(A) Silicon S is formed on the upper substrate (such as an insulating film such as Sin, a silicon semiconductor substrate, or a polycrystalline silicon layer) 1 through a barrier layer 2.3.
Aluminum wiring I15 containing, for example, 1% t! (Film thickness, for example, 4000 people) 4 is formed. In addition, 2 is a titanium layer (thickness: 300, for example) constituting a barrier layer. 3 is a titanium nitride layer or a titanium oxynitride layer (
The thickness is, for example, 700 people). FIG. 1(A) shows the state after the aluminum wiring film 4 is formed.

(B) Next, as shown in the same figure (B), a plasma silicon nitride film (IIA thickness, for example, 1000 layers) 5 is formed. This silicon nitride film 5 is formed to prevent hillocks and also to prevent peeling of the aluminum wiring film. Furthermore, this silicon nitride f
If i5 is thick, such as 7,500 layers, stress migration may cause chipping of the aluminum wiring film, but if it is thin, such as 1,000 layers, no stress migration will occur.

(C) Next, as shown in the same figure (C), the PSG film (I!!
A film having a thickness of, for example, 6,000 mm) is formed as a stress relaxation film and as an insulating film to ensure withstand voltage. That is, the PSGll
Q6 can absorb the stress generated between the aluminum wiring film 4 and the plasma silicon nitride film to be formed later, so it can prevent stress migration +F.
It has a +f effect, and thus plays a role in preventing chipping of the aluminum wiring film 4 due to stress migration (see h in FIG. 5). Although PSGIQ6 can sufficiently function as a stress relaxation film even with a zero thickness of, for example, 1,000 or 2,000 layers, the reason why it is formed as thick as 6,000 layers is to increase the breakdown voltage. In this way, in this example, p sa 11
G6 plays the role of a stress relaxation film and the role of ensuring voltage resistance.

(D) Next, as shown in FIG. 1(D), a plasma silicon nitride film (film thickness, for example, 7,500 mm) is formed (processing temperature: 300 to 400° C.).

(E) Next, as shown in FIG. 3(E), a resist film 8 is applied to planarize the surface.

(F) Next, the resist film 8 and plasma silicon nitride film 7 are etched, ie, etched back, as shown in FIG. The resist film 8 has a flat surface regardless of the unevenness of the underlying plasma silicon nitride film 7), and its etching rate is almost the same as the etching rate of the plasma silicon nitride IE27. Therefore, the surface of the plasma silicon nitride film 7 is made flat by etching.

CG) Then, as shown in FIG. 1(G), the resist film 8.8 remaining on the surface (1) is removed.

Thereafter, an upper aluminum wiring film is formed on the flattened surface of the plasma silicon nitride film 7.

According to such a method of forming multilayer wiring, the plasma silicon nitride film 5 directly formed on the aluminum wiring film 4 is a thin film of about 1,000 yen, and the thick silicon nitride film 7 is a stress relaxation film. Formed via PSG[6.

Therefore, the stress between the aluminum wiring film 4 and the plasma silicosinonitride film 7 is absorbed by the PSGlli6. Therefore, the aluminum distribution caused by stress migration, moss and fidgeting, I
! i! It is possible to prevent the occurrence of chipping of the film. And p s a II! 26 is as thick as 6,000 people, it is possible to ensure sufficient breakdown voltage between wirings.

In this example, a PSG film is formed as the stress relaxation film, but the stress relaxation film is not necessarily limited to this, and for example, an As5G film, a BPSG film, or a pure S
The iO□ film may be formed as a stress relaxation film.

FIGS. 2A to 2E show a second embodiment of the method for forming a multilayer wiring according to the present invention in order of steps.

(A) In the same process as shown in Fig. 1 (A) and (B), the second
As shown in Figure (A), a plasma silicon nitride film (J151 thickness, e.g. 1,000 layers) 5 for hillock prevention is formed on an aluminum wiring film 4 containing, for example, 1% silicon, and further a PSGI+ film as a stress relaxation film is formed. (Film thickness 2000 layers) 6 is formed.

(B) Next, as shown in FIG. 2(B), a plasma silicon nitride film (thickness: 6,000, for example) 7 and a resist film 8 are sequentially formed.

<C> Next, the resist film 8 and plasma silicon nitride film 7 are etched back as shown in FIG. In this etching, the PSG film 6 does not play the role of a stopper, so unless the etching thickness is strictly controlled, the etching will proceed until the surface of the aluminum wiring film 4 is exposed as shown in the drawing.

(D) Next, as shown in the same figure (D), plasma silicon nitride M9 for preventing peeling is formed.

(E) Then, as shown in the same figure (E), PSGII Mulberry (
A film thickness of, for example, 6,000 layers) is formed. This PSG film 10 is formed to make the withstand voltage sufficiently high. Although the PSG film 6 functions as a stress relaxation film, the role of ensuring breakdown voltage is left to the PSG film 10.

Then, an upper aluminum wiring film is formed on the surface of PSGllQlo.

Also in this example, when etching back, psal
Since lQ6 serves as a stress relaxation film, it is possible to prevent stress migration and the occurrence of chipping of the aluminum wiring film due to stress migration.

FIGS. 3(A) to 3(E) are cross-sectional views showing the third embodiment of the method for forming a multilayer wiring according to the present invention in the order of steps. In this embodiment, the PSCL pattern 6 in the second embodiment shown in FIG. 2 is made to play the role of a stopper during etchback, and the plasma silicon nitride film 5 is preserved even after the etchback. This eliminates the need to form the plasma silicon nitride film 9 for preventing peeling in the embodiments. This will be explained in detail below.

(A) After formation of aluminum arrangement film 4, plasma silicon nitride film (1000A thick) 5 and PSG film (
A film thickness of 2,000 layers) 6 was sequentially formed.

FIG. 3(A) shows the state after the PSG film 6 is formed.

This PSGllQ6 plays a role as a stress relaxation film, and in this example, it also functions as a stopper during etchback, so that silicon nitride I1
It plays the role of protecting and preserving 5!5.

The silicon nitride film 5 functions to prevent the interlayer insulating film from peeling off.

(B) Next, as shown in the same figure (B), plasma silicon nitride rl! A (thickness: 1,000 layers) 7 and resist film 8 are sequentially formed.

(C) Next, the resist film 8 and plasma silicon nitride film 7 are etched back. This etch-back is performed by switching the RIE conditions midway through.

Initially, etching was performed under the following etching conditions: gas 5F6102 = 13/7SCCM, power 275W, and atmospheric pressure 325 mTorr (RIE equipment used, for example, 901
e). Under these etching conditions, the selectivity ratio between the plasma silicon nitride film and the resist film is 1:0.96. However, as for the selection ratio with respect to PSG, the plasma silicon nitride film/PSG is about 2, and as it is, PSG cannot play the role of a stopper. Therefore, under these etching conditions, etching is performed until the resist film 8 is completely removed and the psGIff 16 appears on the surface, specifically, for example, to the stage shown in FIG. 3(C).

(D) Next, the etching conditions are changed to, for example, gas SF at 20SCCM (power 275W, pressure 325mTor).
(r remains unchanged) and continue etching. Under these etching conditions, the etching selectivity ratio of plasma silicon nitride film/resist is approximately 0.2;
Plasma silicon nitride IIQ/PSG is approximately 5. Therefore, PSG[6 can serve as a stopper. Incidentally, in this case, the etching rate of the resist will be lowered, but since etching under these new etching conditions will be performed after the resist is exhausted, there will be no luck.

Etching under these new etching conditions is then continued until P S GIIS & 6 is exposed.

FIG. 3(D) shows the state after etching is completed.

In this example as well, psalH
s is aluminum wiring film 4 and silicon nitride film 7
Since it is interposed between the aluminum wiring film 4 and the aluminum wiring film 4 and plays the role of a stress relaxation film, it is possible to prevent stress migration and the resulting chipping of the aluminum wiring film 4.

(E) Then, as shown in the same figure (E), PSGlilo
form. This PSGliIO is formed to ensure voltage resistance.

In this embodiment, since the psa@s functions as an etching stopper during the etchback, the plasma silicon nitride film 5 for preventing hillocks is preserved after the etchback. Therefore, the silicon nitride film 5 can play the role of preventing peeling of the interlayer insulating film. Therefore, it is no longer necessary to form the silicon nitride film 9 for preventing peeling as in the embodiment shown in FIG. 2, and it is sufficient to form psal15Ho after the etch-back process. Therefore, the number of steps can be reduced.

Further, although it is necessary to carry out etching in two stages by changing etching conditions, this can be carried out simply by changing the gas components, and is hardly accompanied by any trouble or prolongation of the etching time. In addition, as a stress relaxation film, P
The fact that an As5G film, a BPSG film, or a pure Sin film can be used in place of the SG film also applies to the embodiments shown in FIGS. 2 and 3.

As described above, the method for forming a multilayer wiring according to the present invention can be implemented in various ways.

(H. Effect of the invention) As described above, the method for forming a multilayer wiring of the present invention is as follows:
A method characterized by sequentially forming a stress relaxation film and a silicon nitride film on the aluminum-based wiring, then forming a flattening film on the silicon nitride, and flattening the film by etching back. It is.

Therefore, according to the method for forming a multilayer wiring of the present invention, since a stress relaxation film is formed, stress can be absorbed by the stress relaxation film. Therefore, stress migration can be prevented, and furthermore, chipping of the aluminum-based wiring due to stress migration can be prevented.

[Brief explanation of the drawing]

The first ILA (A) to (G) are cross-sectional views showing the first embodiment of the method for forming a multilayer wiring according to the present invention in the order of steps, and FIG. 2 (A)
3(A) to 3(E) are cross-sectional views showing the second embodiment of the method for forming a multilayer interconnection according to the present invention in the order of steps, and FIGS. 4(A) to (F) are sectional views showing the conventional example in the order of steps, and FIG. 5 is a plan view showing the problems to be solved by the invention. Explanation of symbols 4: Aluminum-based wiring, - Stress relaxation film, - Silicon nitride film, - Flattening film. Figure 1 Figure 2

Claims (1)

[Claims] (1) A stress relaxation film and a silicon nitride film are sequentially formed on the aluminum-based wiring, a flattening film is then formed on the silicon nitride film, and then flattening is performed by etching back. How to form multilayer wiring