KR20010011196A - Method of forming vias in semiconductor device - Google Patents

Abstract

PURPOSE: A method of forming a via in a semiconductor device is to form an anchor via at an intermetal dielectric layer comprising an insulating layer of a low dielectric constant, without an overhang being generated. CONSTITUTION: A method of forming a via comprises the steps of: forming a first metal interconnect(100) formed of the first metal on a semiconductor substrate; forming a capping layer(102,104) on the metal interconnect; forming an intermetal insulating layer comprising an insulation layer(106) of a low dielectric constant on the capping layer; dry etching the intermetal insulating layer and the capping layer to form a via hole exposing the metal interconnect; forming a spacer(114) on a sidewall of the via hole; wet etching the metal interconnect exposed by the via hole to form an anchor hole(116) undercutting the capping layer; and burying a second metal into the via hole and the anchor hole to form a via plug(118).

Description

Method of forming vias in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which an anchor via is formed in an intermetal dielectric layer (IMD) including an insulating layer having a low dielectric constant. It is about.

As the size of semiconductor devices becomes smaller and lighter, the design rule decreases, and the RC delay due to wiring has emerged as an important factor for determining the operation speed. Accordingly, a multilayer wiring structure has been put to practical use, and a multilayer wiring structure is essential in a logic device that requires high-speed operation. In the semiconductor device having such a multi-layered wiring structure, the characteristics of the vias connecting the metal wires are more important. In addition, as the minimum line width of the metal wiring is reduced, the size of the via is also reduced. Accordingly, the prevention of defects and the securing of low contact resistance have emerged as important problems. The most common method of forming a multi-layer wiring structure is to form vias of tungsten plug processes in which each metal wiring is formed of aluminum (Al) which is deposited by sputtering, and an electrical passage between the wirings is formed.

On the other hand, during the photolithography process for forming the metal wiring, the reflectivity of the wiring is increased at the stepped portion of the lower substrate. This causes diffuse reflection of light and causes a metal bridge between the metal wirings. Defects can result. Therefore, a method of forming a capping layer in which an ohmic layer made of titanium (Ti) and an anti-reflection layer made of titanium nitride (TiN) is stacked on the metal wiring is mainly used.

Currently used vias are divided into two methods. The first is via etch stop on aluminum (VESA) process to terminate the etching of via hole on aluminum layer, and the second is via etch stop on TiN process to terminate etching of via hole on titanium nitride capping layer.

According to the VESA process, since the aluminum layer used as the lower wiring is directly exposed during the dry etching to form the via hole, the lower aluminum layer may be damaged by the plasma due to the excessive dry etching that may occur in part. In addition, a so-called "black via" phenomenon in which the residual gas of dry etching reacts with oxygen or water (H ₂ O) in the atmosphere during subsequent ashing and organic stripping processes to corrode the underlying aluminum layer. There is a problem that occurs.

According to the VEST process, since the lower aluminum layer is not exposed during the dry etching of the via holes, the black via phenomenon due to the organic stripper is hardly generated compared to the VESA process. However, contact resistance is increased between the lower aluminum layer and the tungsten plug because there is a capping layer of titanium / titanium nitride that is much more resistant than aluminum or tungsten. In particular, as the size of the via hole becomes smaller, the increase of such contact resistance becomes more severe.

In a typical via structure, the via plug and underlying metal wiring are physically separated due to the high stress in the interlayer insulating layer, metal wiring and via plug, and the weak interfaces of the metal wiring / interlayer insulating layer and the metal wiring / via plug. So-called via delamination occurs. During the lifetime of the semiconductor device, the semiconductor device undergoes significant thermal cycling, for example, various temperature conditions are encountered during the manufacturing process and packaging. In addition, a large amount of current flowing through the via plug and the metal wiring in operation causes an increase in temperature in a region of high resistance such as a boundary between the via plug and the lower metal wiring. As a result, the via plug is subjected to a large amount of stress due to the different thermal expansion coefficients of the metal wiring, the via plug and the interlayer insulating layer, resulting in via peeling.

A new via structure that can solve this via peeling problem is disclosed in US Patent No. 5,619,071, which will be described with reference to FIG.

Referring to FIG. 1, a capping layer in which titanium 12 and titanium nitride 14 are stacked is formed on the lower aluminum layer 10. An interlayer insulating layer 15 made of an oxide film is formed on the capping layers 12 and 14. After the interlayer insulating layer 15 and the capping layers 12 and 14 are etched by the photolithography process to form the via holes 16 exposing the lower aluminum layer 10, the lower aluminum layer is subjected to isotropic wet etching using chemicals. Etch (10). As a result, the lower aluminum layer 10 is etched laterally under the capping layers 12 and 14 to form anchor holes 18 for undercutting the capping layers 12 and 14. After the via plug 20 filling the via hole 16 and the anchor hole 18 is formed, the upper aluminum layer 22 is formed on the interlayer insulating layer including the via plug 20.

According to the conventional method having the anchor via described above, via peeling can be prevented by anchoring the via plug in the lower aluminum layer.

On the other hand, in a highly integrated semiconductor device having a transistor design rule of 0.25 μm or less, the RC delay of the wiring is greater than the speed delay caused by the transistor, so that even if the gate length of the transistor is reduced, the speed improvement effect cannot be expected. Accordingly, in order to reduce the parasitic capacitance, a method of applying an insulating film having a low dielectric constant (κ) to the interlayer insulating layer has been developed.

2 is a cross-sectional view of a semiconductor device in which anchor vias are formed in an interlayer insulating layer including a low dielectric constant insulating layer.

Referring to FIG. 2, a capping layer in which titanium 52 and titanium nitride 54 are stacked is formed on the lower aluminum layer 50. An interlayer insulating layer in which the low dielectric constant insulating layer 56 and the oxide film layer 58 are stacked is formed on the capping layer. The upper aluminum layer 66 is formed on the interlayer insulating layers 56 and 58. The via plug 64 electrically connecting the lower aluminum layer 50 and the upper aluminum layer 66 has a narrow via hole 60 extending through the interlayer insulating layers 56 and 58 and the capping layers 52 and 54. ) And the anchor holes 62 formed in the lower aluminum layer 50 by undercutting the capping layers 52 and 54.

According to the conventional method of forming the anchor via in the interlayer insulating layer including the low dielectric constant insulating layer, since the etch rate of the low dielectric constant insulating layer with respect to the chemical is large, the via hole is formed during the wet etching to form the anchor hole. The low-k dielectric layer exposed through is excessively etched laterally, resulting in an overhang such as "A" of FIG. 2.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming anchor vias in an interlayer insulating layer including an insulating layer having a low dielectric constant without forming an overhang.

1 is a cross-sectional view of a semiconductor device having anchor vias by a conventional method.

2 is a cross-sectional view of a semiconductor device in which anchor vias are formed in an interlayer insulating layer including a low dielectric constant insulating layer by another conventional method.

3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device having anchor vias according to the present invention.

<Explanation of symbols for main parts of drawing>

100: lower metal wiring 102, 104: capping layer

106: low dielectric constant insulating layer 108: oxide film layer

110: via hole 112: barrier layer

114: spacer 116: anchor hole

118: via plug 120: upper metal wiring

In order to achieve the above object, the present invention, forming a metal wiring made of a first metal on the semiconductor substrate; Forming a capping layer on the metal wiring; Forming an interlayer insulating layer including a low dielectric constant insulating layer on the capping layer; Dry etching the interlayer insulating layer and the capping layer to form a via hole exposing the metal wire; Forming spacers on sidewalls of the via holes; Wet etching the metal wires exposed by the via holes to form anchor holes for undercutting the capping layer; And embedding a second metal in the via hole and the anchor hole to form a via plug.

Preferably, the dry etching for forming the via holes is performed to be etched to a predetermined depth of the metal wiring.

Preferably, the spacer is formed of a metallic or insulating material.

As described above, according to the present invention, after forming an interlayer insulating layer including an insulating layer having a low dielectric constant and forming a via hole, and forming a spacer made of a metallic material or an insulating material on the sidewall of the via hole, an isotropic wet type using chemical The etched lower metal wires exposed by the via holes are etched to form anchor holes.

Therefore, since the low dielectric constant insulating layer is protected by the spacer during wet etching to form the anchor hole and is not directly exposed to the chemical, side etching of the low dielectric constant insulating layer can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device having anchor vias according to the present invention.

Referring to FIG. 3, after forming a plurality of devices such as transistors, bit lines, or capacitors on a semiconductor substrate (not shown) by a conventional technique, an oxide layer is deposited on the substrate to form an insulating layer (not shown). ).

An aluminum alloy including about 0.5% copper, such as an Al—Cu alloy or an Al—Si—Cu alloy, is deposited on the top of the insulating layer by a sputtering method to form the lower metal wiring 100. In this case, the lower metal wire 100 may be formed of only copper (Cu) instead of an aluminum alloy.

Titanium (Ti) 102 is deposited on the lower metal interconnection 100 to a thickness of about 100 GPa, and titanium nitride (TiN) 104 is deposited on the upper portion of about 400 GPa to form a capping layer. The titanium capping layer 102 forms an ohmic layer for the lower metal wiring 100, and the titanium nitride capping layer 104 serves to prevent diffuse reflection of light in a subsequent photographic process.

After the capping layers 102 and 104 and the lower metal wiring 100 are patterned through a photolithography process, a low layer such as a flowable oxide film, a HOSP film, or a nano-glass film is formed on top of the resultant material. The dielectric insulating layer 106 is spin-coated, for example, to a thickness of about 4000 kPa.

An oxide layer 108 is deposited on the low dielectric constant insulating layer 106 to a thickness of about 10000 kPa by a chemical vapor deposition (CVD) method. As a result, an interlayer insulating layer in which the low dielectric constant insulating layer 106 and the oxide film layer 108 are laminated is formed. The interlayer insulating layers 106 and 108 are preferably planarized to have a flat top surface by chemical mechanical polishing (CMP) or etch back method. The interlayer insulating layers 106 and 108 are preferably formed to a thickness sufficient to provide adequate electrical insulation of the lower metal wiring 100 even after planarization.

After forming a resist pattern (not shown) for defining a via hole region on the oxide layer 108 through a photolithography process, the oxide layer 108 and the low dielectric constant insulating layer are formed using the resist pattern as an etching mask. Dry etching the 106 and the capping layers 102 and 104 to form the via holes 110 exposing the lower metal wiring 100. Preferably, the dry etching for forming the via hole 110 is terminated in the lower metal wiring 100.

Referring to FIG. 4, in order to remove foreign substances such as a resist pattern used for dry etching of the via hole 110 and a polymer existing on the surface of the exposed lower metal wiring 100 and the sidewall of the via hole 110. Nitric acid treatment, ashing and organic stripping processes are carried out continuously. Preferably, the stripping process is performed using a chemical mixture of NH ₄ OH, acetic acid (CH ₃ COOH) and water (H ₂ O). By these processes, foreign substances such as polymers are almost removed, but the surface of the lower metal wiring 100 exposed by the ashing process is oxidized to form an Al ₂ O ₃ layer.

Subsequently, a barrier material 112 is formed by depositing a metallic material, such as refractory metal such as titanium / titanium nitride, on the top of the resultant to a thickness of several hundreds of microseconds. In this case, the barrier layer 112 may be formed of an insulating material deposited by a chemical vapor deposition method, preferably a nitride film deposited by a plasma-enhanced chemical vapor deposition (PE-CVD) method.

Referring to FIG. 5, the barrier layer 112 is dry etched by an etch back method to form a spacer 114 on the sidewall of the via hole 110. In this case, the barrier layer 112 at the bottom of the via hole 110 may be completely removed to expose the lower metal wire 100. If the barrier layer 112 remains at the bottom of the via hole 110, an etching process for removing the barrier layer 112 at the bottom of the via hole 110 is performed after dry etching to form the spacer 114. It should be carried out in addition.

Referring to FIG. 6, the spacer 114 is formed on the sidewall of the via hole 110, and the lower portion exposed by the via hole 110 using an organic stripper such as EKC245 or ACT-CMI, for example. The metal wire 100 is isotropically wet etched to a thickness of about 1000 mm 3. As a result, the lower metal wiring 100 is etched laterally under the capping layers 102 and 104 to form an anchor hole 116 for undercutting the capping layers 102 and 104. This anchor hole 116 provides a strong mechanical bond between the via plug and the lower metal wiring 100 formed in a subsequent process.

Preferably, in addition to the organic stripper such as EKC245 or ACT-CMI described above, the lower metal wiring 100 may be formed using chemicals containing fluorine (F) such as hydrofluoric acid (HF), HBF ₄ , LAL, or buffered oxide etchant (BOE). ) Can be etched.

In addition, preferably, the lower metal interconnection 100 may be etched using a chemical mixture of a first chemical containing fluorine (F) and a second chemical including a carboxyl group (COO-). More preferably, a chemical mixture of hydrofluoric acid (HF) and acetic acid (CH ₃ COOH), a chemical mixture of NH ₄ F and acetic acid (CH ₃ COOH), or NH ₄ F with hydrofluoric acid (HF) and acetic acid (CH ₃ The lower metal interconnection 100 is wet etched using chemicals mixed with COOH). When the wet etching process is performed using the chemicals, the surface layer of the lower metal interconnection 100 damaged during the dry etching process for the formation of the via hole 110 may be removed, and may remain during the ashing and organic strip processes. Since all foreign substances such as polymers are removed, the clean surface of the lower metal wire 100 is exposed.

Referring to FIG. 7, after the anchor hole 116 is formed as described above, the wafer is placed in the reaction chamber of the RF sputtering facility, and the foreign material, such as the lower metal wiring 100, which may remain at the bottom of the anchor hole 116. RF etching is carried out to remove the Al ₂ O ₃ layer present on the surface. Since the RF etching proceeds with straightness, the anchor hole 116 is vertically etched to a predetermined depth, while the sidewall of the via hole 110 is not affected by the RF etching so that the spacer 114 remains intact.

After completing the above-described RF etching, titanium and titanium nitride are sequentially deposited on top of the resultant in-situ to form a barrier metal layer (not shown). In general, when the tungsten is deposited by chemical vapor deposition (CVD) to form a via plug, the reactive gas, WF ₆ , has a very good reactivity, and in some cases, an underlayer material such as aluminum (Al) or silicon (Si) may be used. It can easily react with and form unwanted reaction products, leading to an increase or failure of contact resistance. Therefore, in order to prevent this, a method of forming a barrier metal layer and then depositing tungsten so as not to directly expose the underlying layer to the WF ₆ gas is widely used. In addition, the barrier metal layer serves to promote adhesion between the tungsten plug and the aluminum alloy wiring.

Subsequently, a metal such as tungsten is deposited on top of the barrier metal layer by sputtering or chemical vapor deposition (CVD) to fill the via hole 110 and the anchor hole 114. Preferably, a nucleation layer is formed by chemical vapor deposition using chemicals containing WF ₆ and SiH ₄ , followed by tungsten by chemical vapor deposition using chemicals including WF ₆ and H ₂ . Form a layer. Subsequently, the via plug 118 is formed in the via hole 110 and the anchor hole 114 by etching the tungsten layer until the surface of the oxide layer 108 is exposed by a chemical mechanical polishing (CMP) method. . Therefore, the via plug 118 is formed in a structure fixed to the lower metal wire 100 through the anchor hole 114.

Titanium was sputtered to a thickness of about 150 microns on top of the resultant via plug 118 to form an ohmic layer (not shown), and then about 6000 microseconds of aluminum alloy or copper containing about 0.5% of copper thereon. The upper metal interconnection 120 is formed to be electrically connected to the lower metal interconnection 100 through the via plug 118. Titanium is sputtered to a thickness of about 100 GPa on the upper portion of the upper metal wiring 120 and titanium nitride is sputtered to a thickness of about 400 GPa on the upper portion of the upper metal wiring 120 to form a capping layer (not shown). Subsequently, the capping layer, the upper metal wiring 120, and the ohmic layer are patterned through a photolithography process to complete the multilayer wiring structure of the semiconductor device.

As described above, according to the present invention, a via hole is formed by etching an interlayer insulating layer including an insulating layer having a low dielectric constant, and a spacer made of a metallic material or an insulating material is formed on the sidewall of the via hole, followed by wet etching using chemicals. The anchor metal is formed by wet etching the lower metal wires exposed by the via holes.

Therefore, since the low dielectric constant insulating layer is protected by the spacer during wet etching to form the anchor hole and is not directly exposed to the chemical, side etching of the low dielectric constant insulating layer can be prevented.

In addition, the wet etching process for forming the anchor hole not only removes all foreign substances such as polymers and damaged surface layers of the metal wiring, which were generated during the dry etching process in the previous step, but also the underlying metals produced by the ashing process after dry etching. By removing the oxide film on the wiring surface, a low and stable contact resistance can be ensured.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (3)

Forming a metal wiring made of a first metal on the semiconductor substrate; Forming a capping layer on the metal wiring; Forming an interlayer insulating layer including a low dielectric constant insulating layer on the capping layer; Dry etching the interlayer insulating layer and the capping layer to form a via hole exposing the metal wire; Forming spacers on sidewalls of the via holes; Wet etching the metal wires exposed by the via holes to form anchor holes for undercutting the capping layer; And And embedding a second metal in the via hole and the anchor hole to form a via plug. The method of claim 1, wherein the dry etching for forming the via hole is performed to be etched to a predetermined depth of the metal wiring. The method of claim 1, wherein the spacer is formed of a metallic material or an insulating material.