JPH02172220A - Ion implantation - Google Patents

Abstract

PURPOSE:To facilitate formation of a retrograded impurity introduced layer whose surface impurity concentration is controlled by a method wherein a first mask region composed of a mask material which blocks the implantation is provided on a substrate except the impurity introduced region and a second mask region composed of a patterned mask material is provided on the impurity introduced region. CONSTITUTION:A mask material 3 on the impurity introduced region 2 of a semiconductor substrate 1 is patterned and a mask 6 which blocks implanted ions perfectly is provided on a region 5 into which the impurity is not introduced. The paths of the implanted ions 4 are changed by the patterned mask material 3 on the impurity introduced region 2 and the impurity ions are implanted into the surface of the semiconductor substrate 1 with various angles and energies. In other words, if the implanted ions 4 come close to the mask 3 of the impurity introduced region 2, they are scattered in the mask 3 and the impurity ions 4 coming out of the mask 3 is implanted into the substrate 1 with various angles and energies. With this constitution, a region 17 having uniform impurity concentration can be formed near the surface of the substrate 1.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for forming an impurity-introduced layer, and in particular, to a method for forming an impurity-introduced layer having a uniform concentration distribution from the surface of a semiconductor substrate to a depth of 1 to 2 μm. The present invention relates to an ion implantation method suitable for.

[Conventional technology]

In conventional semiconductor devices, especially in MO5LSI, impurity implantation layers such as wells are formed by implanting impurities into the surface region and then performing impurity diffusion at high temperature for a long time, as described in Japanese Patent Application Laid-Open No. 136661/1983. It was formed by doing. In addition, deep impurity-introduced layers such as wells are described in IE, Transaction on Electron Devices, E.D.-32, 203 (198
5) Pages 203 to 204 (IEEE, Trans
, Electron DevLcess, ED32゜2
03 (1985) pp. 203-204) using high energy ion implantation.

[Problem to be solved by the invention]

In the conventional technology using impurity diffusion described above, in order to control device characteristics, it is necessary to maintain the same concentration from the substrate surface to a depth of about 1 to 2 μm, and the resulting impurity diffusion layer becomes deeper than necessary, resulting in a problem with semiconductor devices. This made miniaturization difficult. In addition, concentration control is difficult due to thermal diffusion;
There was a problem that the diffusion time was long. In addition, with the conventional technology using high-energy ion implantation described above, it is not possible to control the substrate surface concentration that determines the device characteristics, so an impurity introduction process is required to control the substrate surface concentration, and the impurity introduction process is complicated. It was hot.

The present invention aims to solve the above-mentioned problems of the prior art and provide a simple and highly reliable impurity introduction process. The purpose is to provide.

[Means to solve the problem]

The above object is achieved by implanting impurity ions 4 after patterning a mask material 3 in an impurity introduction region 2 of a semiconductor substrate 1, as shown in FIG. Here, the region 5 where no impurity is introduced requires a mask 6 to completely block the implanted ions 4. Thereby, an impurity-introduced layer with a uniform concentration distribution near the surface of the substrate 1 can be easily formed.

Further, in order to control the concentration in the uniform portion, the width and mask interval of the mask 3 in the impurity introduction region 2 are set to 1/4 to 4 times the standard deviation of the range of the implanted ions 4 within the mask 3. The value was set to double the range.

Furthermore, in order to control the concentration in the uniform portion, the implantation angle 7 of the implantation ions 4 is set at 6.0 degrees with respect to the surface of the substrate 1.
It was over 0 degrees.

The materials of the masks 3 and 6 do not necessarily have to be the same, and may be any one of an organic resist, a high melting point metal, a compound of a high melting point metal, silicon and a silicon compound, or a combination thereof. Furthermore, the patterning shape of the mask 3 in the impurity-introduced region 2 was made to match the processed shape of the electrodes, wiring, etc. of the semiconductor element. In order to simplify the process after the main ion implantation process, the structure of the resists 3 and 6 and the processed shape of the resist 3 were made to match.

[Effect]

Patterned mask 3 in the impurity introduced region 2
changes the trajectory of the implanted ions 4 so that impurities are implanted into the surface of the semiconductor substrate 1 at various angles and energies.

In the vicinity of the end of the mask 3, the implanted ions 4 are implanted as shown in FIG.

In other words, impurities are introduced! In a portion 8 sufficiently far away from ej2, the implanted ions 4 remain in a region 9 within the mask 6, and if the distance is 4 to 6 times or more the at standard deviation of the implantation distribution within the mask 6, the implantation is completed. Ion 4 hardly reaches the impurity introduced N2.

Next, in a portion 10 that is away from the impurity introduction region 2 by a distance of about 8 $ deviation, in addition to the impurities that stay in the region 11 within the mask 6, there are impurities that are scattered within the mask 6 and jump out of the mask 6. Therefore, impurities are applied to the impurity introduced region 2 and reach the region 12a of the substrate 1 at various angles and energies.

Further, in the boundary portion 13 of the impurity introduced region 2, impurities scattered within the mask 6 and flying out of the mask 6 and impurities scattered by the side walls of the mask 6 cause the impurity introduced region 2 to
are driven into region 12b at various angles and energies.

Here, in the portion 14 without the mask 6, the light enters the region 15 of the substrate 1 as it is. Therefore, in the vicinity of the end of the mask 6, an impurity distribution 16 of 8 degrees of similarity lines as shown in FIG. 3 is obtained.

Now, as shown in FIG. 4, when the mask 3 of the impurity-introduced region 2 approaches, the ions are transferred to the mask 3 as explained above.
Impurity ions scattered within the mask 3 and ejected to the outside of the mask 3 are implanted into the substrate 1 at various angles and energies, forming a region 17 with a uniform concentration near the surface of the substrate 1. Here, impurities that do not pass through the mask 6 are implanted into the substrate 1 with the initial energy of implantation, and are implanted into the region 17.
As a result, a slightly higher concentration region 18 is formed.

This is achieved when the width of the mask 3 and the spacing between the masks 3 are equal to or less than the value of the standard range of implantation. Note that by selecting the width of the mask 3 and the mask interval, it is possible to control scattering of impurities and control the concentration on the substrate surface.

Furthermore, if the implantation angle 7 is 60 degrees or more, impurities will be scattered on the sidewalls of the mask 3, so that the impurities will be implanted into the substrate 1, but if the angle 7 is less than 60 degrees, there will be areas where the impurities are not implanted. . By selecting this implantation angle, scattering of impurities is controlled to control the concentration on the substrate surface.

By using a high melting point metal or a high melting point metal compound as the material of the mask 3 patterned in the impurity-introduced region, in addition to an organic resist, the blocking ability against the implanted ions 4 can be increased, and the film thickness of the mask 3 can be increased. Can be made smaller. This enables finer patterning. Further, by patterning the mask 3 containing a high melting point metal into the processed shape of the electrodes and wiring, it becomes possible to omit the electrode and wiring process after forming the impurity-introduced layer. Furthermore, here,
By using a silicon film instead of a high melting point metal, the same process as above can be simplified.

Furthermore, if the semiconductor substrate is likely to be contaminated by the mask 3 made of a material containing an organic resist or a high melting point metal, the exposed portion of the mask 3 is covered with silicon or a silicon compound to prevent the contamination. .

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 5 to 10.

[Example 1]--Silicon (
A plan view and a cross-sectional view of an example in which a p-type retrograde well layer 19 is formed on a Si) substrate 18 are shown.

A silicon oxide film (SiOx) 2 with a thickness of 30Ωm is formed on the surface of an n-type Si substrate 18 with a (100) plane orientation of 10Ω.
After depositing a photoresist mask 21 with a film thickness of 4 μm, the mask 21 was processed into a rectangular shape in the well formation region 22 ((a) and (b)). This processing was performed using a normal photoetching method. was used, and the mask width and mask interval were set to 1 μm. Thereafter, boron (B) ions were injected at 0,8 M a V energy, 1
After implanting with an implantation amount of x1018/cd and removing the resist mask 21, it was heated to 100'C in nitrogen (N2).

A heat treatment was performed for 10 minutes to form a p-type retrograde well layer 19 having a concentration distribution as shown in (C) in the figure. In the same figure (C), the actual [23] is the distribution of the part without a mask, and the broken line 24 is the distribution of the part directly under the strip-shaped mask 21. In addition, the concentration near the surface is 2 × 10
It was ``/am'.

According to this embodiment, since a uniform distribution can be formed near the surface of the Si substrate 18, the M
It has become easier to control the characteristics of OS transistors. Furthermore, by obtaining the distribution shown in FIG. 5(C), the well layer 1
The resistance of the CMO8 can be reduced to half that of the conventional well layer, the latch-up resistance of the CMO8 can be improved by about three times, and the resistance of the MOS memory to alpha rays can also be improved. By being able to form a well layer as shallow as 173 mm compared to conventional wells, M
Effects such as facilitating miniaturization of O3LSI can be obtained.

[Example 2] The example in which an n-type shield layer was formed under the P-type retrograde well layer of the above example was changed to the sixth example.
A p-type silicon substrate 25 of 6 CZ, (100), 10 Ω, which will be explained using the cross-sectional view and concentration distribution diagram in the figure.
After forming a Si○2 film 26 with a thickness of 1100 nm on the surface by thermal oxidation, a tungsten silicide film 27 with a thickness of 2 μm (the composition ratio of tungsten and silicon was 1:1) was formed by sputtering. The silicide film 27 was deposited and processed by a normal photoetching method.Next, a resist film 28 with a thickness of 4 μm was deposited and processed by photoetching (Figure (ai), the processed shape is shown in Figure 5). Also, the mask width is set to 0.
8 μm, and the mask interval was 1.2 μm.

After this, ions of B were implanted under the same conditions as in Example 1.
A implanted layer 29 was formed.

Next, the resist film 28 was etched away by 1.5 μm using an isotropic dry etching method. At this time, the strip-shaped mask completely disappeared, leaving a resist 28 of 2.5 μm on the silicide film 27. Then, in this state, phosphorus (P) was ion-implanted at an amount of 5×10”/at at an energy of 4 M a V to form P implantation N30 (FIG. (b)).

Thereafter, after removing the resist film 28 and the silicide film 27, heat treatment is performed at 1000° C. for 10 minutes in an Nx atmosphere to form a p-type well layer 31 and an n-type well layer 31 with an impurity concentration distribution as shown in CC) in the figure. A mold shield layer 32 was formed. The concentration near the surface of the p-type well layer is 3X1016
■It became δ.

According to this example, an n-type shield layer can be easily formed under the p-type well layer having the effect described in Example 1, so that by manufacturing a MOS memory with the above structure, α
Almost complete shielding against line and board noise can now be achieved, significantly improving device reliability.

[Example 3] Immediately after forming the p-type well layer shown in Example 1, an example in which element isolation was formed using a part of the mask material constituting the implantation mask is shown in Fig. 7. This will be explained using a plan view and a sectional view.

As in Example 1, a 5iOz film 2 is formed on the surface of the Si substrate 18.
0, silicon nitride fJ! is further formed using the CVD method. X (S i 5N4) 33 to 120 n
m deposited. After that, a resist mask 3 with a film thickness of 6 μm is applied.
4 was formed (Figure (b)). The processed shape of the mask 34 in the well layer forming region (the part surrounded by the broken line 35 in Figure (a)) is square as shown in Figure (a), and the dimensions of the square mask 36 are 2 μrn square. Furthermore, the 5iaNa film was first etched using a dry etching method with the distance between the masks 34 being 1 μm. In this state, set B to 1
．． A B implanted layer 37 with a maximum depth of about 3 μm was formed by ion implantation at 5 MeV and 2×IO”/cmz (Figure C (b)). After that, the resist film 34 was removed, and then B38 was implanted. 4 x IQ”/a at 90keV
A B implantation layer 39 for a channel stopper was formed by implanting a B implantation layer 39 for a channel stopper (FIG. (C)).

After heat treatment at 1000° C. for 10 minutes in a N2 atmosphere, a field 5iOz film 40 with a film thickness of 500 nm was formed without selective oxidation at 1000° C. for 2 hours in a steam oxygen atmosphere. Channel stopper layer 41 and p
A mold well layer 42 was formed (Figure (d)), after which 5
The iaN4 film 33 was removed and the process proceeded to the MOS transistor manufacturing process.

According to this embodiment, since the p-type well layer having the effect shown in the first embodiment and the element isolation region can be formed at the same time, it is possible to simplify the process and improve the reliability of device characteristics. Further, by using this method in a CMOS process, the n-channel region and the p-channel region can be formed with independent specifications. Also.

In addition to forming element isolation using the selective oxidation described above,
) If grooves are formed in the Si substrate 18 by anisotropic dry etching immediately after the B implantation, groove-type element isolation can also be formed.

[Example 4] An example in which a trench for a trench capacitor of a memory element is formed using an implantation mask immediately after the formation of the p-type well layer shown in Example 1 is shown in the plan view of FIG. This will be explained using figures and cross-sectional views.

As in Example 1, after forming the 5i02 film 20 on the surface of the n-type Si substrate 18, the film thickness was reduced to 200 nm by the CVD method.
A 5iaN film 43 with a thickness of 1 μm and a 5iOz film 44 with a thickness of 1 μm were deposited. Next, the photoresist film 45 having a film thickness of 6 μm was processed into a lattice shape in the well formation region (the area surrounded by the broken line 46) as shown in Figure (a) by a normal photoetching method. At this time, the size of the portion 47 without the resist mask 45 was set to 1 μm square. Further, the width of the resist mask 45 was set to 2 μm.

Next, after processing the Si012 film 44 and the 5iaNa film 43 by dry etching, B is etched with 3M e.
Ion implantation by 3 x 101a/cJ at V
After forming the implantation layer 48 (FIG. (b)) and removing the resist mask 45, 5iOzll! was formed by dry etching. 20 and the Si substrate 18 to form a groove 49 with a depth of 4 μm (Figure (C)
).

According to this embodiment, the formation of the p-type well layer having the effect shown in the first embodiment and the groove processing can be performed in the same photo process.

[Example 5] The plan view and cross-sectional view of FIG. 9 show a part of the patterned mask of the impurity introduction region
An example of use as a gate electrode of an S transistor will be explained.

The processed shape of the mask of the impurity introduction region 50 is 1 μm wide at 1 μm intervals (a). This structure is made of p-type Si
After forming a field oxide film 52 with a thickness of 600 nm and a gate oxide film 53 with a thickness of 10 Ωm on a substrate 51, a phosphorus-doped polycrystalline Si film (thickness = 200 nm) is formed.
54. After depositing a Si○2 film 55 with a film thickness of 200 nm, and further depositing a 2 μm thick tungsten oxide film 56 with a tungsten and oxygen composition ratio of 1:1, 1. Membrane 56, 5i
The Oz film 55 and polycrystalline Si film 54 are processed, and finally,
Silicon nitride film 57 is grown by vapor phase growth using plasma.
This was achieved by depositing 50 Ωm ((b) in the figure).

Next, a B implantation layer 58 was formed by ion implanting B by 3XIO1B/alt using IMAV.
The silicon nitride film 57 and the tungsten oxide film 56
After removal, heat treatment was performed at 900° C. for 10 minutes in N2 to form a p-type retrograde well layer 58. After this, arsenic was implanted at 40 keV by 5XIQIII/aJ, and N2. 900℃ inside.

By performing heat treatment for 10 minutes, the n-medium diffusion layer 59
was formed to produce a MOS transistor ((C
)).

According to this example, the gate electrode of the MOS transistor could be processed at the same time as the retrograde well was formed.
The MO8 element manufacturing process was simplified. Also 1 usually,
Although the tungsten oxide film 56 contains many contaminants, by covering it with the silicon nitride film 57, contaminants can be prevented from entering during implantation. Furthermore, the polycrystalline Si film 5
By replacing 4 with a tungsten film, a tungsten gate MOS transistor could also be realized.

[Example 6] An example of manufacturing a bipolar transistor will be described with reference to the plan view and cross-sectional view of FIG. 10.

P-type, 10Ω・cs, (100) oriented Si substrate 6o
A field oxide film 61 with a film thickness of 600 nm and a 5iOz film 62 with a film thickness of 1100 nm were formed on the substrate.Next, boron difluoride (BFz) ions were irradiated with 3×101 at 15 keV.
Insert number /d, N2. A p-type base 563 was formed by heat treatment at 1000° C. for 30 seconds. After patterning the 5iC)z film 62, As and BF2 were implanted with IX 101IS/cd at 25keV, and heat treatment was performed at 1000°C for 30 seconds in Nz.
An n-middle layer 64 and a p+M layer 65 were formed, respectively. Here, the n-middle layer and p-middle layer formed in the p-type base layer 63 were used as an emitter layer and an external base layer, respectively. Further, the other n-middle layer was used as a collector-drawn n-middle layer.

Next, as shown in FIG.
6, a mask for P implantation was formed. This mask consists of a tungsten film 67 with a thickness of 300 nm and a tungsten film 67 with a thickness of 4 nm.
The photoresist film was 1 μm thick, and the mask width and mask interval were 1 μm. Furthermore, the shape of the mask was the shape of the extraction electrodes of the emitter, base, and collector of a bipolar transistor. Using this mask, P is ion-implanted at 3 M e V by 5 x 1014/d, and after removing the resist film 68, heat treatment is performed in N2 at 1000°C for 10 seconds to form an n-type buried collector layer 69. Formed.

Through the above steps, a bipolar transistor was manufactured.

According to this embodiment, since the buried collector layer 69 can be formed using ion implantation, it is possible to provide a manufacturing process that is not only simpler but also cheaper than manufacturing a transistor using a conventional epitaxial substrate. Furthermore, since bipolar transistors having various collector concentrations can be formed by controlling the processing shape of the mask, the degree of freedom in transistor manufacturing is improved.

〔Effect of the invention〕

According to the present invention, the surface concentration can be controlled and a trograde type impurity introduced layer can be formed with a single ion implantation, so the formation time of the impurity introduced layer can be significantly reduced (from 1/2 to 1/1
In addition to improving the characteristics of the device formed in the impurity-introduced layer, a shallow, low-resistance impurity-introduced layer can be formed, which is effective in miniaturizing semiconductor elements.

In addition, by arbitrarily selecting the processing dimensions of the mask and the ion implantation angle in the impurity introduction region, it is possible to arbitrarily select the concentration in the uniform area near the substrate surface, so various surface concentrations can be obtained on the same substrate. This method is effective in simplifying the process and increasing the degree of freedom in device design.

Moreover, according to the present invention, selecting the material of the implantation mask,
Furthermore, by matching the processed shape of the mask to the processed shape of the electrodes and wiring, it is possible to omit the step of manufacturing the electrodes and wiring after implantation, thereby simplifying the process.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views for explaining the principle of the present invention, Figures 3 and 4 are cross-sectional views showing the impurity concentration distribution obtained by the present invention, and Figure 5 is a p-type retrograde well formation. FIG. 6 is a plan view, a cross-sectional view, and an impurity concentration distribution diagram of the element forming part when the present invention is implemented, and FIG. 6 is a cross-sectional view of the element forming part in an example in which an n-type shield layer is formed around the p-type retrograde well. and impurity concentration distribution diagram, Fig. 7 Plan view and cross-sectional view of the element forming part when the beam trograde well formation mask is used as a selective oxidation mask, Fig. 8 Beam trograde well formation mask is used as a groove processing mask Fig. 9 is a plan view and a sectional view of the element forming part when the trograde well formation mask is used as a gate electrode processing mask, Fig. 10 is a plan view and a sectional view of the element forming part when the trograde well formation mask is used as a gate electrode processing mask, and Fig. 10 is an n-type buried collector. FIG. 7 is a plan view and a cross-sectional view of an element forming portion when a forming mask is used as a processing mask for electrodes and wiring of a bipolar transistor. 1... Semiconductor substrate, 2, 22, 35, 46, 50°6
0... Impurity introduction region, 3.21... Patterned mask, 4, 8, 10, 13.14... Impurity ion, 9, 11, 12, 13, 15, 16° 17.1
8... Impurity introduced layer, 19, 29, 42° 48.58
... p-type impurity introduced layer, 30.69... n-type impurity introduced layer. Tomi 1 drawing 舅 2 drawing Tomizu 1st section 〆fig. Tomizu Diagram

Claims (1)

[Scope of Claims] 1. When forming an impurity-introduced layer in a semiconductor substrate using an ion implantation method, a first mask region is provided in a portion other than the impurity-introduced region using a mask material that blocks the implantation, An ion implantation method characterized in that a second mask region formed by patterning the mask material is provided in the impurity introduction region. 2. In the method according to claim 1, the mask width and mask interval in the second mask area are
An ion implantation method characterized in that the ion implantation range is from 1/4 to 4 times the standard range within the mask in the ion implantation. 3. In the method described in claim 1 above, the implantation angle of the ion implantation is 6° with respect to the surface of the semiconductor substrate.
An ion implantation method characterized by increasing the temperature to 0 degrees or higher. 4. In the method described in claim 1 above, the material of the mask material is any one of an organic resist, a high melting point metal, a compound of a high melting point metal, silicon and a silicon compound, or a combination thereof. An ion implantation method characterized by the following. 5. The ion implantation method according to claim 1, wherein the patterning shape of the second mask region is a processed shape of an electrode or wiring of a semiconductor element.