JPH02171907A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To practically attain the extension of the operation cycles of a synchronizing type master device and an asynchronous type master device by providing the subject circuit with a clock signal output control circuit and optionally controlling the stop of the supply of an operation clock signal to be applied to the master devices. CONSTITUTION:A universal pulse processor 1 incorporates an oscillation circuit 10 for forming a clock signal for regulating the internal synchronizing operation of itself of that of a microprocessor 2 and a clock signal output control circuit 11 controls the stop of operation for outputting a clock signal CLKs synchronizing with the clock signal formed by the oscillation circuit 10 to the external as necessary. The stop controlling operation is executed by a waiting signal WT outputted from a control part 12 and the validity/invalidity of the stop control is determined in accordance with the setting state of a mode flip flop 13 constituting one bit of a control register. Consequently, the operation cycles of both synchronous type and asynchronous type master devices can be practically extended.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a built-in oscillation circuit and supplies that clock signal or a clock signal synchronized therewith to the outside. 1. For example, the present invention relates to a technique that is effective when applied to a data processing device such as a peripheral controller that is to be a slave device to a microprocessor or microcomputer.

[Prior art]

Some master devices, such as microprocessors and microcomputers, have a wait function that prolongs or stops the master device's own operation cycle in order to enable asynchronous access control of peripheral devices with slow operating speeds. . For example, when accessing a relatively slow device such as memory, or when setting data in a register inside one peripheral controller takes time, output from those peripheral devices or wait controllers. When the master device samples the wait signal ?, the mask device prolongs the operating cycle according to the assert period of the wait signal.

Further, some master devices such as microprocessors and microcomputers do not have the above-mentioned wait function and access peripheral devices in complete synchronization. When such a master device is used and the maximum operating speeds of the 5-mask device and the peripheral device are different, the system operating speed is determined in accordance with the slower device.

An example of a document describing microcomputers is "Hitachi Microcomputer Data Book 8-Bit Single Chip Microcomputer" published by Hitachi, Ltd. in 1985.

[Problem to be solved by the invention]

However, mask devices such as processors used to configure a required system do not necessarily have a wait function, depending on the required specifications of the system. Therefore, when a synchronous master device without a wait function is employed, the operating speed of the system is limited to the minimum operating speed of the peripheral devices employed in the system. Regarding this point, for example, if we focus on peripheral controllers that require extra time to set data to internal registers, the operating speed of the entire peripheral controller will be limited to such slow operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit to be used as a peripheral device that can substantially extend the operation cycle of both synchronous and asynchronous mask devices.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, to control the stoppage of the clock signal generated by the built-in oscillation circuit or the output of the clock signal synchronized thereto to the outside based on a signal that requests to stop or postpone the operation of the external circuit during internal operation. clock signal output control circuit and receives control information from the outside,
A semiconductor integrated circuit is constructed by providing storage means for instructing the clock signal output control circuit to enable/disable stop control based on this control information.

In order to effectively utilize the wait function of the master device that performs asynchronous bus control, it is preferable to output a signal to the outside that requests to stop or postpone the operation of the A section circuit during the above-mentioned internal operation.

In order to prevent the waveform of the clock signal to be output to the outside from being undesirably interrupted in the middle of a cycle, a synchronization circuit for synchronizing the output stop timing of the clock signal with the change in the output clock signal of the built-in oscillation circuit is installed on the clock signal. Provided in the signal output control circuit.

Further, it is preferable to provide a synchronization circuit for synchronizing the timing of applying the information set in the storage means to the tarlock signal output control circuit with changes in the output clock signal of the built-in oscillation circuit.

[Function] According to the above means, the clock signal output control circuit:
The supply of the operating clock signal to the master device is controlled to be stopped arbitrarily according to the internal operation, and this makes it possible to substantially extend the operating cycle for both synchronous and asynchronous master devices. It acts on

[Embodiment] FIG. 3 shows a universal pulse processor 1 which is an embodiment of the present invention. The universal pulse processor shown in the figure is formed on a single semiconductor substrate such as a silicon substrate using semiconductor integrated circuit manufacturing technology. This universal pulse processor 1 is 1
The microprocessor 2 is a peripheral device of a microprocessor 2 which is typically shown as a master device, and is coupled to the microprocessor 2 via a system bus 3.

The above universal pulse processor 1 is.

Although not particularly limited, it is generally an LSI in which a timer/counter is structured as a processor. That is.

This universal pulse processor 1 has an execution unit including a register file constituted by a plurality of general-purpose registers, an arithmetic and logic unit that can be shared as an incrementer, a decrementer, and a comparator. The required registers included in the file are registers for counters and capture registers.

Also, by functioning as a conveyor register,
It can be used for general purpose counting, comparison, and transfer operations. In particular, the universal pulse processor 1 is
It has a function table that holds rewritable microprograms for controlling internal operations, increasing the versatility of the pulse input/output control function. The operating mode for the universal pulse processor 1 is given from the microprocessor 2 by a command or the like.

By the way, in such a universal pulse processor 1, due to the necessity of its timer/counter operation,
For registers that function as capture registers,
Alternatively, the external microprocessor 2 must access registers for the counter.

This data to be accessed is exchanged via the system bus 3. The cycle time for such data transfer is longer than the arithmetic operation cycle inside the universal pulse processor 1 or the operation cycle of the processor 2. Therefore, if the operating speed of the system shown in FIG. When performing this, the operating cycle of the microprocessor 2 must be extended or suspended. In this embodiment, the universal pulse processor 1 controls the operation cycle of the microprocessor 2 to be extended or temporarily stopped, and the universal pulse processor 1 provides the operation clock signal CLKs to the microprocessor 2.

Next, a control mechanism for extending or temporarily stopping the operation cycle of the microprocessor 2 will be explained.

The universal pulse processor 1 of this embodiment includes an oscillation circuit 10 that generates a clock signal for defining its own internal synchronous operation and the internal synchronous operation of the microprocessor 2. The clock signal generated by this oscillation circuit 10 is not directly output to the outside, but is provided to the microprocessor 2 via a clock signal output control circuit 11. This clock signal output control circuit 11 controls to stop the operation of outputting the clock signal CLKs to the outside in synchronization with the clock signal generated by the oscillation circuit 10, as necessary. This stop control is performed using a wait signal WT output from the control unit 12 of the entire universal pulse processor 1.
The validity/invalidity of the stop control by the clock signal output control circuit 11 is not particularly limited, but depends on the setting state of the mode flip-flop 13 that constitutes one bit of the control register. The wait signal WT is a signal for requesting the operation of the microprocessor 2 to be temporarily stopped or postponed during the operation of the universal pulse processor 1, for example, during data transfer with the microprocessor 2. Further, the settings for the mode flip-flop 13 are performed under the control of the microprocessor 2.

A detailed example of a control mechanism for prolonging or suspending the operating cycle of microprocessor 2 is shown in FIG.

Although not particularly limited, the oscillation circuit 10 is a fundamental wave crystal oscillator circuit, in which a feedback resistor 15 and a feedback complementary MOS inverter 16 are connected in parallel to an externally attached crystal oscillator 14, forming a π-type network. 180° phase difference between the internal and external feedback MOS inverters 16
It resonates due to the phase difference between the two, and the oscillation is extracted as tarok signals C and LK from the output inverter 17 which functions for waveform shaping or amplification.

The clock signal output control circuit 11 includes two D-type latches 20, 21 . Nant gate 22 and inverter 23
It is made up of. The above-described type latch 20 has the clock signal CLK supplied to the clock input terminal C, and
A wait signal WT is supplied to the data input terminal. The NAND gate 22 is supplied with the tarock signals CI, K and the level of the inverted output terminal Q of the D-type latch 20. In the D-type latch 21, the output signal of the Nandt gate 22 is supplied to the tarlock input terminal C, the inverting output terminal Q is feedback-coupled to the data input terminal, and the non-inverting output terminal Q is connected to the input terminal of the inverter 23. has been done. This inverter 23 functions as a buffer for outputting the operating clock signal CLKs to the outside. When the inverting output terminal Q of the D-type latch 20 is at a high level, the output level of the Nant gate 22 is changed in synchronization with the change in the clock signal CLK and in the opposite phase thereof. On the other hand, when the inverted output terminal Q of the D-type latch 20 is set to low level,
That is, when the wait signal WT is set to high level in synchronization with the rising edge of the clock signal CLK,
The output of the Nant gate 22 is fixed at a high level. When the output of the Nant gate 22 is fixed at a high level, D
The level of the non-inverting output terminal Q of the type latch 21 is fixed,
As a result, the change in the operating clock signal CLKs is stopped. The above type latch 20 uses the clock signal CLK to set the timing for fixing the output of the NAND game 1-22 at a high level.
It functions as a synchronization circuit to synchronize with the rise change of . Therefore, the wait signal WT is the clock signal C
Even if it is changed asynchronously with LK, the operating clock signal CLK
The change in s is interrupted in the middle of the clock cycle and does not stop, but the change is stopped in synchronization with the rising or falling timing.

The instruction to disable the output stop control for the operating clock signal CLKs by the tarlock signal output control circuit 11, in other words, the instruction to maintain the output state of the operating clock signal CLKs even if the wait signal WT is asserted is the first instruction. According to the figure, it is applied to the reset terminal R of the above type latch 20. When a high level is applied to the reset terminal R, the interleaved latch 20 sets the inverted output terminal Q to an initial state of a high level, and allows the output of the operating clock signal CLKS regardless of the level of the wait signal WT.

According to FIG. 1, the mode flip-flop 13 for giving an instruction to enable/disable the output stop control of the operation clock signal CL K s is constituted by a D-type latch. Hereinafter, this mode flip-flop 13 will also be simply referred to as the D-type latch 13. The data input terminal of the D-type latch 13 is supplied with 1-bit control data CDATA from the microprocessor 2. This control data CDATA is the clock signal output control circuit 11.
This is regarded as information that instructs whether the output stop function of the operating clock signal CLKs is enabled or disabled, and its high level indicates ineffectiveness. Writing control data CDATA to the D-type latch 13 is performed by writing the control data CDATA to the D-type latch 13.
The write control signal W supplied to the clock input terminal C of
It is performed in synchronization with the change of CLK and K. This D
Control data CDA written to mold latch 13
TA is not directly supplied to the reset terminal R of the above-mentioned type latch 2o, but is supplied via the D-type latch 25. This D-type latch 25 uses a clock signal CL to control the reset timing and reset release timing for the D-type latch 20.
It functions as a synchronization circuit to synchronize with changes in K. Therefore, the writing timing of the control data CDATA to the D-type latch 13 is determined by the clock signal C.
The reset timing for the D-type latch 20 is synchronized with the clock signal CLK even if it deviates from the change timing of LK.

A reset signal RESET is supplied to the reset terminal R of the above-mentioned type latch 13. This reset signal RESET
is a signal corresponding to a power-on reset, and when this reset signal RESET is set to low level, the D-type latch 13
When the reset terminal R of is set to high level, its non-inverting output terminal Q becomes low level, achieving an initial state in which the function of stopping the output of the operating clock signal CLKs by the clock signal output control circuit 11 is enabled.

Next, the operation of the above embodiment will be explained with reference to the timing chart of FIG.

Once the reset signal RESET is set to low level by power-on reset, the D-type latch 13 is in the same state as if the low-level control data CDATA had been written, in other words, the clock signal output control circuit 11
An instruction state is set to enable the output stop function of the operating clock signal CLKs. In this state, the level of the non-inverting output terminal Q of the D-type latch 25 is set to a low level, which is a non-reset level. Therefore, in a state where the wait signal W'r is negated to a low level as in the state before time 1, the inverting output terminal Q of the D-type latch 20 is set to a high level, so that the output of the Nant gate 22 is changed in level in synchronization with the clock signal CLK, thereby outputting the operating clock signal CLKs.

At time L□, wait signal WT is asserted to high level -1-
Then, at time t2 synchronized with the rise of the clock signal CLK, the inverted output terminal Q of the D-type latch 20 is changed to low level, thereby causing the operating clock signal CLKs to change to low level.
changes are stopped.

This state is maintained until the clock signal CLK rises immediately after the wait signal WT is negated.

Therefore, when the microprocessor 2 does not have a wait function and data is transferred between the microprocessor 2 and the built-in register of the universal pulse processor I, the data transfer cycle is
Even if it is longer than the bus cycle in which the microprocessor 2 starts up, the universal pulse processor 1 asserts the wait signal WT for the necessary time to control the operation cycle of the microprocessor 2, which operates in synchronization with the operation clock signal CLKs. Operation clock signal CLK
It can be extended only during the period in which the change in s is stopped.

On the other hand, when the microprocessor 2 has a wait function, the wait signal WT output from the universal pulse processor 1 is supplied to the wait signal input terminal of the microprocessor 2, as shown by the broken line in FIG. Moreover, high level control data CDATA is written into the D-type latch 13. In this state, the levels of the non-inverting output terminals Q of the D-type latches 13 and 25 are fixed at a high level, and as a result, the D-type latch 20 is always in a reset state. is fixed at a high level, and the stop control of the operating clock signal CLKs by the clock signal output control circuit 11 is disabled. In this stop control invalid state, even if the wait signal WT is asserted (at time t in FIG. 2), D
Priority is given to the reset state of the type latch 20, and the operating clock signal CLKs continues to be supplied to the microprocessor 2. At this time, since the microprocessor 2 has a wait function, it inserts a wait cycle into the operation cycle for a period corresponding to the assertion period of the way signal WT given from the universal pulse processor 1, and controls the extension of the bus cycle etc. by itself. do.

According to the above embodiment, the following effects can be obtained.

(1) When interfacing the universal pulse processor 1 with a microprocessor 2 that does not have a wait function, supply the operating clock signal CLKs for the microprocessor 2 according to the needs of the universal pulse processor. The operation cycle of the microprocessor 2, which stops and operates in synchronization with the operation clock signal CLKs, can be extended by a required period.

In addition, when interfacing the universal pulse processor 1 with a microprocessor 2 having a wait function, the universal pulse processor 1
A wait signal W is sent to the microprocessor 2 as needed.
By supplying T, the microprocessor 2 inserts a wait cycle into the operation cycle for a period corresponding to the assertion period of the wait signal W1', and thereby controls the extension of the bus cycle by itself. In this way, the operating cycles of both synchronous and asynchronous microprocessors 2 can be substantially extended regardless of whether or not they have a wait function.

(2) From the above effects, even if the master device, such as a microprocessor, which should be selected according to the required specifications of the system, does not have a wait function, the operating speed of the system can be improved by the peripherals adopted in the system. It becomes possible to eliminate restrictions such as having to match the minimum operating speed of the device. This further shows that
If we focus on a universal pulse processor 1 that takes extra time to set data to internal registers, it will also eliminate the situation where the overall operating speed of the processor 1 is limited to such slow operation. .

(3) Since a synchronization circuit such as a D-type latch 20.25 is provided, the operating clock signal C to be outputted to the outside
It is possible to prevent the waveform of LKs from being undesirably interrupted during the cycle. In other words, the weight signal W
There is no need to completely synchronize the assertion timing of T and the timing of writing data to the D-type latch 13 with changes in the clock signal CLK.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, when the D-type latch 13 is reset, an initial state is obtained in which the clock signal output stop control function is enabled, but the initial state is a state in which the function is disabled. You may also do so.

Further, the weight signal does not need to be output to the outside. In this case, in order to extend the operation cycle of a mask device having a wait function, it is also possible to temporarily stop the supply of an operation clock in the same way as for a mask device without a wait function.

In the above explanation, the invention made by the present inventor was mainly applied to a universal pulse processor, which is the field of application in which the invention is based, but the present invention is not limited thereto, and can be applied to coprocessors, coprocessors,
Furthermore, it can be applied to various other semiconductor integrated circuits that are considered other peripheral devices. The present invention is widely applicable to semiconductor integrated circuits that operate in synchronization with a clock signal generated by a built-in oscillation circuit based on at least an external instruction, and provide that clock signal or a clock signal synchronized thereto to an external device. can do.

〔Effect of the invention〕

The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, to control the stoppage of the clock signal generated by the built-in oscillation circuit or the output of the clock signal synchronized thereto to the outside based on a signal that requests to stop or postpone the operation of the external circuit during internal operation. Since it has a clock signal output control circuit and a storage means for instructing whether to enable or disable clock signal output stop control, it is possible to substantially lengthen the operation cycle for both synchronous and asynchronous mask devices. The effect is that it can be done. Therefore, even if a mask device such as a microprocessor, which should be selected according to the required specifications of the system, does not have a wait function, the operating speed of the system must match the minimum operating speed of the peripheral devices employed in the system. This makes it possible to eliminate restrictions such as: Furthermore, when focusing on peripheral controllers that take extra time to set data to internal registers, this also helps to eliminate the situation where the overall operating speed of the peripheral controller is limited to such slow operation. Become.

By making it possible to output to the outside a signal requesting to stop or postpone the operation of the external circuit, it is possible to effectively utilize the wait function of the master device that performs asynchronous bus control.

A synchronization circuit for synchronizing the output stop timing of the clock signal with the change in the output clock signal of the built-in oscillation circuit, and a synchronization circuit for synchronizing the output stop timing of the clock signal with the change in the output clock signal of the built-in oscillation circuit and the timing for giving the information set in the storage means to the clock signal output control circuit are output from the built-in oscillation circuit. By providing a synchronization circuit to synchronize to clock signal changes.

It is possible to prevent the waveform of the shift signal to be outputted to the outside from being undesirably interrupted in the middle of the cycle.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a control mechanism that extends or temporarily stops the operation cycle of an external master device, FIG. 2 is a timing chart showing an example of the operation of the control mechanism shown in FIG. 1, and FIG. FIG. 1 is a system configuration diagram including a universal pulse processor that is an embodiment of the present invention. 1... Universal pulse processor, 2...
Microprocessor, 3... System path, 10...
・Oscillation circuit, CLK...clock signal, 11...clock signal output control circuit, CL Ks...operation clock signal, 12...control unit, WT...wait signal, 13...mode Flip-flop, 20, 21.
25...D type latch, CDATA...control data, WCLK...write control signal. Agent: Patent Attorney Katsuo Ogawa N.1
Figure 3 Figure 33 s':yhmuha's

Claims (1)

[Claims] 1. A semiconductor integrated circuit that performs internal operations in synchronization with a clock signal generated by a built-in oscillation circuit based on instructions from the outside, and provides the clock signal or a clock signal synchronized therewith to the outside. In a circuit, control to stop the output of a clock signal generated by the built-in oscillation circuit or a clock signal synchronized thereto to the outside based on a signal requesting to stop or postpone the operation of an external circuit during internal operation. 1. A semiconductor integrated circuit comprising: a clock signal output control circuit for controlling a stop control; and a storage means for receiving control information from the outside and instructing the clock signal output control circuit to enable/disable stop control based on the control information. 2. The data processing device according to claim 1, wherein a signal requesting to stop or postpone the operation of the external circuit during the internal operation can also be outputted to the outside. 3. The data processing device according to claim 2, wherein the clock signal output control circuit includes a synchronization circuit for synchronizing the output stop timing of the clock signal with a change in the output clock signal of the built-in oscillation circuit. 4. The data processing device according to claim 3, further comprising a synchronization circuit for synchronizing the timing at which the information set in the storage means is provided to the clock signal output control circuit with changes in the output clock signal of the built-in oscillation circuit.