JPH02166999A - Time division exchange circuit - Google Patents

Abstract

PURPOSE:To prevent data quantity to be exchanged from being limited by the access time of a speech path memory by inputting data to the plural speech path memories with the parallel data of plural bits and selecting an (n) bit out of the read parallel data. CONSTITUTION:The serial input data are converted to the plural parallel data, which have phase difference in a prescribed bit time mutually, by plural serial/ parallel converters 8-1 and 8-2 and the plural parallel data of the phase difference are separately written to respective speech path memories 3-1 and 3-2 with respectivephases based on the instruction of a writing address output part 2. After that, the memory address, to which the bit data to execute data conversion are written, is outputted from a holding memory 10 and the parallel data are read from the respective addresses. Then, 1-bit data are selected out of the respective parallel data by a selector 9 and inputted to a data output paty 7-3. Then, the respective bit data are synthesized to the serial data and outputted in a selection order. Thus, the exchange ability of the data is not limited by the access time of the respective memories.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time division switching circuit that performs bit switching of data transferred at high speed on a data highway.

[Conventional technology]

FIG. 3 shows a conventional time division switching circuit disclosed in, for example, Japanese Unexamined Patent Publication No. 61-7790. In the figure, (1) is the human data highway, (2) is the sequential write counter,
(3) is the communication path memory, (4) is the holding memory, (5) is the output data highway, (6) is the input data latch, (
7) is an output data latch.

The operation of this circuit is as follows: input data highway (1)
The data that has been serially transmitted on the
), the signals are sequentially written into the communication path memory (3) in the order of the counter indicated by the write counter (2). Next, based on the address specified by the holding memory (4), the data written in the communication path memory (3) is read from an arbitrary address, and the output data latch (7)
After being latched into the output data highway (5), it is sent out on the output data highway (5).

As a result, time-division exchange is performed by rearranging the data on the human-powered data highway and sending it out on the output data highway. Figure 4 shows data A and B on the human data highway (1).

Output C, D, E, F on the data highway (5).
This is a timing chart when rearranging and transmitting in the order of A, C, E, B, and D. Input data highway (1
) above data A, B, C, D.

After E and F(a) are latched by the manual data latch (6), they are sequentially written to the communication path memory (3) by the write counter (2).
) are sequentially written from address 1 to address 6 in the order of the counter indicated by (b). Next, the holding memory (4
), data F written in address 6 is read out first, then data A in address 1 is read out, and then data C, E, B, and D are read out in the same order. (C) (d) After the read data is latched in the output data latch (7), it is sent out on the output data highway (5) in the order of F, A, C, E, B, and D.

(Problem to be solved by the invention) Since the conventional time division exchange is configured as described above,
For example, as the data transfer speed on the data highway becomes faster and the data exchange capacity per hour increases, communication path memory and retention memory with fast access times become necessary.
Furthermore, if the data exchange unit is set to bits, the communication path memory and holding memory must be operated at an operating speed equal to or higher than the data transfer speed on the data highway, so the data exchange ability is limited by the access time of each memory. There were some problems.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a time-division exchange circuit that can time-divisionally exchange high-speed transfer data in a non-block manner in accordance with the operations of each of the above-mentioned memories.

(Means for Solving the Problems) A time division switching circuit according to the present invention converts serial data into N
A plurality of serial-sequence converters that convert bit-configured parallel data with a phase difference of multiple bit times, and a communication path that separately stores the parallel data output from each serial converter. a memory, a write address output unit that generates and outputs a data write address for each call path memory, a read output unit that generates and outputs a different data read address for each call memory, and a read address output unit that generates and outputs a different data read address for each call memory, and It is provided with a selector that selects arbitrary bit data from each parallel data in read address order, and a data output section that serially converts and outputs each bit data in the selection order.

[Effect]

According to this invention, serial human data can be
A column/column converter converts the data into multiple pieces of parallel data with a predetermined bit temporal phase difference, and writes the multiple pieces of parallel data with the phase difference to each communication memory and outputs each one based on the instructions from the address output section. The data is written separately in each phase, and then the memory address where the bit data to be converted is written is read out and outputted from the address output section to the communication memory, and the parallel data is read out from each address.
The serial data is converted into data by selecting one bit of data from each parallel data using a selector, inputting it to the data output section, and combining and outputting each bit of data into serial data in the selected order.

(Embodiment) Figure 1 shows an embodiment of the present invention in the case of converting serial input data into 2-bit parallel data, in which (1) is a human-powered data highway, (8-1) and (8-2) are S /P
Converter, (8-1), (6-2) are manual data latches, (2) is sequential write counter, (3-1), (3-
2) is the communication path memory, (lO) is the communication path memory (3-1
), (3-2) is a holding memory that determines the data exchange order, (9) is a selector, (7-1), (7-2), (7
-3) is an output data latch, and (5) is an output data highway.

In FIG. 1, data on the input data highway (1) is sent to two S/P converters (8 -
1) and (8-2), it is converted into 2-bit data. The two converted 2-bit data are transferred to a manual data latch (6-
1) and (6-2), the communication path memories (3-1) and (3) are sequentially written based on the instructions of the write counter (2).
-2) in each phase.

From the holding memory (10), each communication channel memory (3-1), (
Based on each address sent separately to 3-2),
Data is read out from arbitrary addresses of each channel memory (3-1), (3-2) in each phase, and latched by output data latches (7-1), (7-2). The latched 4-bit data (from 2 x 2 bits, 1 bit corresponding to each address is selected by the selector (9) and the output data is latched (after being latched by 7-31, each bit data is serially configured and output data highway Send to (5).

Figure 2 shows serial input data A, B, C, DE, F.
, A, C, E, B, D. FIG. Human power data A, B, C, D, E,
F(a) is two S/Ps with a phase difference of 1 bit from each other.
It is converted into 2 bits by converters (8-1) and (8-2),
The communication path memory (3-
1) and (3-2) are sequentially written from address 1 at a speed of 172, which is the data transfer speed of the human output data highway (b-1) and (b-2). On the reading side, the holding memory (
Based on the address sent from the communication path memory (ff-1), E and F at address 3 of the communication path memory (ff-1) are input, and then, with a phase difference of 1 bit, A of address 1 of the communication path memory (3-2) is input. (c-1), (c-2) are read at a speed of 172 of the data transfer rate of the output data highway. The read 4-bit data is first selected by the selector (9) which operates at the same speed as the data transfer speed of the 0 person output data highway, and then the second bit F of address 3 is selected, and then the second bit F of address 1 is selected.
The 4th bit A is selected. Similarly, C, E
, B, D are selected in this order, and the output data highway (5)
(d), (e) In this embodiment, 2-bit parallel is explained, but any number of bits may be used in parallel, and as the number of parallel bits increases, the communication path memory,
Retention memory can be slowed down.

〔Effect of the invention〕

As described above, according to the present invention, after manually inputting data into multiple call path memories as multiple bit parallel data,
n from the parallel data read out from each channel memory.
Since a selector is provided to select bits, the amount of data to be exchanged is not limited by the data access time of the channel memory, allowing a large amount of data to be exchanged, and the exchange of bits, which is the smallest unit of exchange, has a low operating speed. This can be achieved using call path memory.

[Brief explanation of the drawing]

FIG. 1 is a time division block diagram according to an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of this embodiment,
FIG. 3 is a block diagram of a conventional time division circuit, and FIG. 4 is a timing chart explaining the operation of the conventional circuit. In the figure, (1) is the human data highway, (2) is the sequential write counter, (3), (3-1), (3-
2) is the communication path memory, (4) (10) is the holding memory, (5) is the output data highway, (6) is the manual data latch, (7) (7-IL(7-2), (7-
31 is an output data latch, (a-t), (8-2) is S
/P converter, (9) is a selector. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Multiple serial-to-serial converters convert serial data into N-bit parallel data, each with a phase difference of multiple bit times, and the parallel data output from each serial converter is stored separately. a write address output section that generates and outputs a data write address for each call path memory; a read output section that generates and outputs a different data read address for each call memory; A time division switching circuit characterized by comprising a selector for reading and selecting arbitrary bit data from each output parallel data in address order, and a data output section for serially converting and outputting each bit data in the selected order. .