JPH02165645A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH02165645A
JPH02165645A JP63321071A JP32107188A JPH02165645A JP H02165645 A JPH02165645 A JP H02165645A JP 63321071 A JP63321071 A JP 63321071A JP 32107188 A JP32107188 A JP 32107188A JP H02165645 A JPH02165645 A JP H02165645A
Authority
JP
Japan
Prior art keywords
wire
lead frame
impurity
diffusion
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63321071A
Other languages
Japanese (ja)
Inventor
Mamoru Ando
守 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63321071A priority Critical patent/JPH02165645A/en
Publication of JPH02165645A publication Critical patent/JPH02165645A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
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    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/15747—Copper [Cu] as principal constituent

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To increase adhesive strength between a lead frame and a wire in low temperature treatment by making the lead frame or the wire contain diffusion impurity. CONSTITUTION:A lead frame 2 can be obtained by punchprocessing a conductive metallic plate which is mainly made of copper like Cr-Zr-Cu alloy, etc., for its main material and contains antimony by 0.05-5wt.% as diffusion impurity 8. A wire 7 is a metallic fine line which consists of gold whose purity is 99.9% or more and contains beryllium by 0.0001-0.01wt.% as diffusion impurity 9. The antimony which is contained in the lead frame 2 as diffusion impurity 8 has a great diffusion coefficient to the gold. On the other hand, the beryllium which is contained in the wire 7 as the diffusion impurity 9 also has a great diffusion coefficient to copper. Accordingly, alloying between the lead frame 2 and the wire 7 is advanced, and the adhesive strength of the second bond increases.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明はワイヤの接着性に優れ、信頼性の高いベアボン
ド型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a bare bond type semiconductor device which has excellent wire adhesion and is highly reliable.

（ロ）従来の技術 半導体装置の組立てには、リードフレームの素子設定部
に半導体素子を取付けるダイボンド工程と、半導体装置
の電極とリードフレームの各リード片とをワイヤで結線
するワイヤボンド工程がある。(b) Conventional technology The assembly of semiconductor devices includes a die bonding process in which the semiconductor element is attached to the element setting part of the lead frame, and a wire bonding process in which the electrodes of the semiconductor device and each lead piece of the lead frame are connected with wires. .

その中で、半導体装置の一層のローコスト化を目的とし
て、金属メツキを省略したリードフレームを利用する、
所謂ベアボンドと称される組立手法が提案キれている。Among these, with the aim of further reducing the cost of semiconductor devices, lead frames that omit metal plating are being used.
An assembly method called so-called bare bonding has been proposed.

ベアボンドは、ｆ：！４（Ｃｕ）を主材料とする平面状
の金属板を打ち抜いて製造したフードフレームを銅素材
が露出した状態で使用し、チップサイズが大きい場合に
は例えばＡｇペースト、半田プリフォーム等のソフトソ
ルダーにより裸のリードフレームのタブ部に半導体チッ
プをダイボンドし、続いて半導体チップの電極とリード
フレームの裸のリードとを金（Ａｕ）線等のワイヤでワ
イヤボンドを行うものである（特開昭６２−２５５９号
、ＨＯＩＬ　２３／４ｇ）。Bare Bond is f:! A hood frame manufactured by punching out a flat metal plate mainly made of 4(Cu) is used with the copper material exposed, and if the chip size is large, soft solder such as Ag paste or solder preform is used. In this method, a semiconductor chip is die-bonded to the tab portion of a bare lead frame, and then the electrodes of the semiconductor chip and the bare leads of the lead frame are wire-bonded using a wire such as a gold (Au) wire. 62-2559, HOIL 23/4g).

（ハ）発明が解決しようとする課題 しかしながら、ダイボンド用接着剤としてエポキシ系Ａ
ｇペーストや半田プリフォーム等を選択した場合、Ａｇ
ペーストの品質保障温度が２５０〜３００℃、半田プリ
フォームの融点が約３１０℃と比較的低く、その為ワイ
ヤボンド工程を高温で処理できない制約がある。一方、
銅（Ｃｕ）に対する金（Ａｕ）の拡散係数はＤ−１，６
９Ｘ１０’″’　”　（Ｔ１１　”　／　’５ｅｃ（Ｔ
−３００℃）と小さく、その為低温下では接着信頼性の
高いワイヤボンドができない欠点があった。(c) Problems to be solved by the invention However, epoxy A is used as a die bonding adhesive.
If you select Ag paste or solder preform, etc.
The quality guarantee temperature of the paste is 250 to 300°C, and the melting point of the solder preform is relatively low, about 310°C, which limits the wire bonding process to high temperatures. on the other hand,
The diffusion coefficient of gold (Au) to copper (Cu) is D-1.6
9X10'''''(T11'' / '5ec(T
-300°C), and therefore had the disadvantage that wire bonding with high adhesion reliability could not be performed at low temperatures.

（ニ）課題を解決するための手段 本発明は上記従来の課題に鑑み成されたもので、（１）
銅系リードフレーム（２）に拡散不純物を含有させるこ
とにより、（２）金ワイヤ（７）に拡散不純物を含有さ
せることにより、低温で且つ接着信頼性に優れたワイヤ
ボンドを実施し得るベアボンド型の半導体装置を提供す
るものである。(d) Means for solving the problems The present invention has been made in view of the above-mentioned conventional problems, and includes (1)
By incorporating a diffusion impurity into the copper lead frame (2), and (2) by incorporating a diffusion impurity into the gold wire (7), a bare bond type that can perform wire bonding at low temperatures and with excellent bonding reliability. The present invention provides a semiconductor device.

（＊）作用 本発明によれば、ワイヤボンド時の熱処理により、（１
）銅系リードフレーム（２）から金線（７）へ拡散不純
物（８）が、（２）金線（７）から銅系リードフレーム
（２）へ拡散不純物（９）が、夫々拡散するので、低温
処理での両者の接着強度を増大できる。(*) Effect According to the present invention, by heat treatment during wire bonding, (1
) The diffusion impurity (8) diffuses from the copper lead frame (2) to the gold wire (7), and (2) the diffusion impurity (9) diffuses from the gold wire (7) to the copper lead frame (2). , the adhesive strength between the two can be increased during low-temperature treatment.

（へ）実施例 以下に本発明の一実施例を図面を参照して詳細に説明す
る。(F) Example An example of the present invention will be described below in detail with reference to the drawings.

第１図は本発明の半導体装置を示す断面図で、（１）は
リードフレーム（２）のタブ、（３）はリードフレーム
（１）の外部接続端子となるリード、（４）は表面に素
子形成とＡ１又はＡｌ−５ｉ電極（５）の形成が終了し
たシリコン半導体チップ、（６）はチップ（４）をフー
ドフレーム（２）のタブ（１）に固着する例えばエポキ
シ系Ａｇペーストや半田プリフォーム等のロウ材、（７
）はチップ（４）表面の電極（５）とリード（３）の表
面とを電気接続する金（Ａｕ）ワイヤである。FIG. 1 is a cross-sectional view showing the semiconductor device of the present invention, in which (1) is a tab of a lead frame (2), (3) is a lead serving as an external connection terminal of the lead frame (1), and (4) is a surface The silicon semiconductor chip (6) is a silicon semiconductor chip on which element formation and A1 or Al-5i electrode (5) have been formed. For example, epoxy-based Ag paste or solder is used to fix the chip (4) to the tab (1) of the hood frame (2). Brazing material for preforms, etc. (7
) is a gold (Au) wire that electrically connects the electrode (5) on the surface of the chip (4) and the surface of the lead (3).

フードフレーム（２）は、例えばＣｒ−Ｚｒ−Ｃｕ合金
等のｇ４（Ｃｕ）を主材料とし、且つ拡散不純物（８）
としてアンチモン（Ｓｂ）を０，０５〜５重量％含む導
電性金属板をパンチング加工することにより得られるも
ので、表面にメツキ被覆層は形成せず裸のままで使用す
る。The hood frame (2) is mainly made of g4 (Cu) such as Cr-Zr-Cu alloy, and contains diffused impurities (8).
It is obtained by punching a conductive metal plate containing 0.05 to 5% by weight of antimony (Sb), and is used as it is without forming a plating layer on the surface.

ワイヤ（７）は、例えば直径５０ａｍ、Ｉｆ！ｉ！の純
度９９．９％以上の金（Ａｕ）から成り、且つ拡散不純
物（９）としてベリリウム（Ｂｅ）を０．０００１〜０
．０１重量％含む金属細線である。The wire (7) has a diameter of, for example, 50 am, If! i! It is made of gold (Au) with a purity of 99.9% or more, and contains beryllium (Be) of 0.0001 to 0 as a diffusion impurity (9).
．． It is a thin metal wire containing 0.01% by weight.

リードフレーム（２）に含有した拡散不純物（８）とし
てのアンチモン（Ｓｂ）は、金（Ａｕ）に対してＤ；２
．０３　Ｘ　１０−”ａｎ”／５ｅｅ（Ｔｍ　３　Ｑ　
０℃）と大きな拡散係数を有する。一方、ワイヤ（７）
に含有した拡散不純物（９）としてのベリリウム（Ｂｅ
）は、銅（Ｃｕ）に対してＤ＝Ｍ４．３８Ｘ　１０−”
ｃｍ”／５ｅｃ（Ｔ−３００℃）とこれも大きな拡散係
数を有する。Antimony (Sb) as a diffusion impurity (8) contained in the lead frame (2) is D; 2 with respect to gold (Au).
．． 03 X 10-”an”/5ee(Tm 3 Q
It has a large diffusion coefficient (0°C). On the other hand, wire (7)
Beryllium (Be) as a diffusion impurity (9) contained in
) is D=M4.38X 10-” for copper (Cu)
cm''/5ec (T-300°C), which also has a large diffusion coefficient.

従って上記本願の構成によれば、ワイヤボンドのセカン
ドボンドにおいて、 （１）　リードフレーム（２）のアンチモン（ｓｂ）が
ワイヤ（７）に拡散する （２）　ワイヤ（７）のベリリウム（Ｂｅ）がリードフ
レーム（２）に拡散する という現象が発生する。従って、上記（１）又は（２）
のどちらか一方若しくは上記（１）（２）の両方を備え
ることにより、セカンドボンド点においてリードフレー
ム（２）とワイヤ（７）との合金化が促されるので、セ
カンドボンドの接着強度が増大する。また、ロウ材（６
）の制約に基いて２５０〜３００℃の低温でのワイヤボ
ンドを実施できる。Therefore, according to the configuration of the present application, in the second bond of the wire bond, (1) antimony (sb) in the lead frame (2) diffuses into the wire (7), and (2) beryllium (Be) in the wire (7) diffuses into the wire (7). A phenomenon of diffusion into the lead frame (2) occurs. Therefore, (1) or (2) above
By providing either one or both of (1) and (2) above, alloying between the lead frame (2) and the wire (7) is promoted at the second bond point, thereby increasing the adhesive strength of the second bond. . In addition, wax material (6
) Wire bonding can be performed at a low temperature of 250 to 300°C.

第２図Ａ乃至第２図りは夫々本発明の製造方法を工程順
に示した断面図である。FIGS. 2A to 2D are cross-sectional views showing the manufacturing method of the present invention in the order of steps.

先ず第２図Ａに示すように、表面にトランジスタ等の素
子形成とボンディング用の電極（５）形成が終了した半
導体チップ（４）と、銅系素材が露出したリードフレー
ム（２）・とを用意し、ロウ材（６）によって２５０〜
３００℃の熱処理を伴うダイボンド工程により半導体チ
ップ（４）をリードフレーム（２）のタブ（１）に固着
する。そのリードフレーム（２）をワイヤボンド装置の
ヒータブロックを内蔵した図示せぬ作業台上に載置して
電極（５）の位置認識を行い、このデータに基いてＸ方
向及びＹ方向に進退自在な取付部材に着脱自在に取り付
けられたキャピラリチップ（１０）を半導体チップ（４
）の電極（５）上空に移動する。キャピラリチップ（１
０）の挿通孔（１１）には金ワイヤ（７）が挿入され、
ワイヤ（７）の先端には図示せぬトーチの炎により、又
は電極との高圧放電により挿通孔（１１）の直径より大
きな球状のボール部（１２）が形成されている。（１３
）はクランパ、（１４）はワイヤスプールである。First, as shown in FIG. 2A, the semiconductor chip (4) on which elements such as transistors and bonding electrodes (5) have been formed, and the lead frame (2) with exposed copper material are separated. 250 ~ depending on the wax material (6)
The semiconductor chip (4) is fixed to the tab (1) of the lead frame (2) by a die bonding process involving heat treatment at 300°C. The lead frame (2) is placed on a workbench (not shown) that has a built-in heater block of the wire bonding machine, and the position of the electrode (5) is recognized, and based on this data, it can move forward and backward in the X and Y directions. A capillary chip (10) removably attached to a mounting member is attached to a semiconductor chip (4).
) move above the electrode (5). Capillary tip (1
A gold wire (7) is inserted into the insertion hole (11) of 0),
A spherical ball portion (12) larger than the diameter of the insertion hole (11) is formed at the tip of the wire (7) by a flame from a torch (not shown) or by high voltage discharge with an electrode. (13
) is a clamper, and (14) is a wire spool.

尚、上記状態において、 （１〉　リードフレーム（２）に拡散不純物（８）が含
まれる （２）ワイヤ（７）に拡散不純物＜９）が含まれる（３
）　リードフレーム（２）とワイヤ（７）の両方に拡散
不純物（８）（９）が含まれる のうちいずれかの状態にあるものとする。In the above state, (1) the lead frame (2) contains the diffused impurity (8), (2) the wire (7) contains the diffused impurity (<9), (3)
) It is assumed that both the lead frame (2) and the wire (7) contain diffusion impurities (8) and (9).

次に第２図Ｂに示すように、キャピラリチップ（１０）
を下降してボール部（１２）の下面を半導体チップ（４
）の電極（５）に所望圧力で圧接し、且つキャピラリチ
ップ（１０）全体に図示せぬ振動装置で超音波振動を与
えることによりワイヤ（７）を超音波併用熱圧着してフ
ァーストボンド（ボールボンド）とする、その後クラン
パ（１３）を開放し、ワイヤ（７）を自由にすると共に
、キャピラリチップ（１０）を垂直に上昇させ、次にキ
ャピラリチップ（１０）を水平方向に移動してセカンド
ボンド点へと向う。Next, as shown in Figure 2B, the capillary tip (10)
lower the ball part (12) and touch the bottom surface of the semiconductor chip (4).
) by applying ultrasonic vibration to the entire capillary chip (10) using a vibrating device (not shown), the wire (7) is bonded with ultrasonic heat and pressure to form a first bond (ball). Then, the clamper (13) is released, the wire (7) is freed, and the capillary tip (10) is raised vertically, and then the capillary tip (10) is moved horizontally to Head to Bond Point.

続いて第２図Ｃに示すように、セカンドボンド点に移動
したキャピラリチップ（１０）を下降させてキャピラリ
チップ（１０）の圧接部によりワイヤ（７）をリード端
子＜３）表面に圧接し、キャピラリチップ（１０）全体
に超音波振動を与えることによりワイヤ（７）を超音波
併用熱圧着してセカンドボンド七する。ワイヤボンディ
ング工程中、リードフレーム（２）は前記ヒータブロッ
クの加熱により２００〜３００℃の温度に保たれ、圧接
点は前記ヒータブロックの加熱と超音波振動により２５
０〜３００℃の温度になる。この温度により、セカンド
ボンド時には上記３つの状態に応じて （１）　リードフレーム（２）に含有した拡散不純物（
８）としてのアンチモン（ｓｂ）がワイヤ（７）に拡散
される （２）ワイヤ（７）に含有した拡散不純物（９）として
のアンチモン（ｓｂ）がリードフレーム（２）に拡散さ
れる （３）　リードフレーム（２）の拡散不純物（８）とワ
イヤ（７）の拡散不純物（９）とが相互に拡散されると
いう現象が発生し、この現象がリードフレーム（２）と
ワイヤ（７）との合金化を促す。Next, as shown in FIG. 2C, the capillary chip (10) moved to the second bond point is lowered and the wire (7) is pressed against the surface of the lead terminal <3 by the pressure contact part of the capillary chip (10). By applying ultrasonic vibration to the entire capillary chip (10), the wire (7) is bonded by thermocompression with ultrasonic waves to form a second bond. During the wire bonding process, the lead frame (2) is kept at a temperature of 200 to 300°C by the heating of the heater block, and the pressure contact point is kept at a temperature of 25°C by the heating of the heater block and ultrasonic vibration.
The temperature will be between 0 and 300°C. Due to this temperature, during the second bonding, the diffusion impurities contained in the lead frame (2) are
(8) Antimony (sb) is diffused into the wire (7) (2) Antimony (sb) as a diffusion impurity (9) contained in the wire (7) is diffused into the lead frame (2) (3 ) A phenomenon occurs in which the diffused impurity (8) of the lead frame (2) and the diffused impurity (9) of the wire (7) are mutually diffused, and this phenomenon occurs between the lead frame (2) and the wire (7). Promotes alloying.

然る後第２図りに示すように、キャピラリチップ（１０
）を圧接した状態でクランパ（１３）がワイヤ＜７〉を
挾持し、クランパ（１３）がワイヤ（７）を引張ること
によりワイヤ（７）をキャピラリチップ（１０）の先端
付近で切断する。After that, as shown in the second diagram, a capillary tip (10
), the clamper (13) clamps the wire <7>, and the clamper (13) pulls the wire (7) to cut the wire (7) near the tip of the capillary tip (10).

以上に説明した本願のワイヤボンド方法によれば、セカ
ンドボンド時において、リードフレーム（２）又はワイ
ヤ（７）に含有させた拡散不純物（８）（９）が相互に
拡散するので、接合点においてリードフレーム（２）と
ワイヤ（７）との合金化が促される。According to the wire bonding method of the present application described above, at the time of second bonding, the diffusion impurities (8) and (9) contained in the lead frame (2) or the wire (7) are mutually diffused, so that at the bonding point Alloying of the lead frame (2) and wire (7) is promoted.

従って、ロウ材（６）の制約に伴う低温下の熱処理でも
強固な接着力が得られる。Therefore, strong adhesive strength can be obtained even during heat treatment at low temperatures due to the limitations of the brazing material (6).

（ト）発明の効果 以上に説明した如く、本発明によればリードフレーム＜
２）又はワイヤ（７）に拡散不純物（８）（９）を含み
、セカンドボンド時において相互に拡散させるので、接
着力強固なワイヤボンド構造が得られる利点を有する。(G) Effects of the Invention As explained above, according to the present invention, the lead frame <
2) Or, since the wire (7) contains the diffusion impurities (8) and (9) and they are mutually diffused during the second bonding, there is an advantage that a wire bond structure with strong adhesive strength can be obtained.

また、低温下での処理が可能なのテ、銅フレームとＡｇ
ペーストヤ半田プリフォーム等の組合わせにより信頼性
の高い半導体装置を安価に製造できる利点を有する。In addition, the copper frame and Ag can be processed at low temperatures.
It has the advantage that highly reliable semiconductor devices can be manufactured at low cost by combining paste, solder preform, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明を説明する為の側面図、第２図Ａ乃至第
２図りは夫々本発明を説明する為の断面図である。FIG. 1 is a side view for explaining the present invention, and FIGS. 2A to 2A are sectional views for explaining the present invention.

Claims (3)

【特許請求の範囲】[Claims] （１）金属素材が露出したリードフレームに半導体チッ
プをダイボンドしワイヤボンドを行う半導体装置におい
て、 前記リードフレームにワイヤボンドのワイヤへの拡散不
純物が含まれるか、又は前記ワイヤにリードフレームへ
の拡散不純物が含まれるか、若しくはそれらの両方を具
備することを特徴とする半導体装置。(1) In a semiconductor device in which a semiconductor chip is die-bonded and wire-bonded to a lead frame with an exposed metal material, the lead frame contains an impurity that diffuses into the wire of the wire bond, or the wire diffuses into the lead frame. A semiconductor device characterized by containing impurities or both. （２）金属素材が露出したリードフレームに半導体チッ
プをダイボンドしワイヤボンドを行う半導体装置におい
て、 前記半導体チップをロウ材により固着すると共に、 前記リードフレームにワイヤボンドのワイヤへの拡散不
純物が含まれるか、又は前記ワイヤにリードフレームへ
の拡散不純物が含まれるか、若しくはそれらの両方を具
備し、 前記ワイヤボンドのセカンドボンド時において、前記拡
散不純物をリードフレームからワイヤへ、又はワイヤか
らリードフレームへ、若しくはそれらの両方へ拡散させ
、 且つ前記ワイヤボンドは前記ロウ材の融点又は補償温度
より低い温度で行うことを特徴とする半導体装置の製造
方法。(2) In a semiconductor device in which a semiconductor chip is die-bonded and wire-bonded to a lead frame with an exposed metal material, the semiconductor chip is fixed with a brazing material, and the lead frame contains an impurity that diffuses into the wire of the wire bond. or the wire contains a diffusion impurity to the lead frame, or both, and at the time of second bonding of the wire bond, the diffusion impurity is transferred from the lead frame to the wire or from the wire to the lead frame. , or both thereof, and the wire bonding is performed at a temperature lower than the melting point or compensation temperature of the brazing material. （３）前記リードフレームが銅（Ｃｕ）を主成分とする
金属材料であり前記ワイヤが金（Ａｕ）を主成分とする
金属材料であり、且つ前記リードフレームの拡散不純物
は０．０５〜５．５重量％のアンチモン（Ｓｂ）であり
拡散不純物は０．０００１〜０．０１重量％のベリリウ
ム（Ｂｅ）であることを特徴とする請求項第１項又は第
２項に記載の半導体装置又は半導体装置の製造方法。(3) The lead frame is made of a metal material mainly composed of copper (Cu), the wire is made of a metal material mainly composed of gold (Au), and the diffusion impurity of the lead frame is 0.05 to 5. 3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is antimony (Sb) in an amount of .5% by weight and the diffusion impurity is beryllium (Be) in an amount of 0.0001 to 0.01% by weight. A method for manufacturing a semiconductor device.
JP63321071A 1988-12-20 1988-12-20 Semiconductor device and its manufacture Pending JPH02165645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63321071A JPH02165645A (en) 1988-12-20 1988-12-20 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63321071A JPH02165645A (en) 1988-12-20 1988-12-20 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH02165645A true JPH02165645A (en) 1990-06-26

Family

ID=18128483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63321071A Pending JPH02165645A (en) 1988-12-20 1988-12-20 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH02165645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026335A1 (en) * 2006-09-01 2008-03-06 Murata Manufacturing Co., Ltd. Electronic part device and method of manufacturing it and electronic part assembly and method of manufacturing it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008026335A1 (en) * 2006-09-01 2008-03-06 Murata Manufacturing Co., Ltd. Electronic part device and method of manufacturing it and electronic part assembly and method of manufacturing it

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