JPH0216463U - - Google Patents
Info
- Publication number
- JPH0216463U JPH0216463U JP9495888U JP9495888U JPH0216463U JP H0216463 U JPH0216463 U JP H0216463U JP 9495888 U JP9495888 U JP 9495888U JP 9495888 U JP9495888 U JP 9495888U JP H0216463 U JPH0216463 U JP H0216463U
- Authority
- JP
- Japan
- Prior art keywords
- data
- latch circuit
- reading
- control device
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の磁気記録装置の制御装置の一
構成例を示す電気的接続図、第２図は第１図の回
路の動作を説明するためのタイムチヤート、第３
図はＮＲＺＩ変調方式を示す図である。
１……ＣＰＵ、２……入力ポート、３……出力
ポート、４……磁気記憶装置、５……波形整形回
路、６……ラツチ回路、７……オア回路。
FIG. 1 is an electrical connection diagram showing an example of the configuration of a control device for a magnetic recording apparatus according to the present invention, FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 1, and FIG.
The figure is a diagram showing the NRZI modulation method. 1...CPU, 2...Input port, 3...Output port, 4...Magnetic storage device, 5...Waveform shaping circuit, 6...Latch circuit, 7...OR circuit.
Claims (1)
書込みと読出しができるようにした磁気記憶装置
の制御装置であつて、 磁気記憶装置から読み出した各チヤンネルのデ
ータおよび奇数パリテイビツトをラツチするラツ
チ回路と、 このラツチ回路が出力する各チヤンネルのデー
タおよび奇数パリテイビツトの論理和をとるオア
回路と、 データを書込むときには多チヤンネルのうちの
任意の１チヤンネルに奇数パリテイビツトを書込
み、データを読出すときには、前記ラツチ出力を
クロツク信号として利用し、そのクロツク信号の
到来を確認した後、すべてのチヤンネルのデータ
がラツチ回路にラツチされたと推定される一定時
間後に前記ラツチ回路に保持されているデータを
読込むようにする機能を有する中央演算処理装置
を具備し、スキユーによる読取りミスを防止する
ようにしたことを特徴とする磁気記録装置の制御
装置。[Claims for Utility Model Registration] A control device for a magnetic storage device that is capable of writing and reading multi-channel data to and from a magnetic storage device, the control device including data of each channel and odd parity bits read from the magnetic storage device. A latch circuit that latches the data, and an OR circuit that takes the logical sum of the data of each channel output by this latch circuit and the odd parity bit. When writing data, the odd parity bit is written to any one of the multiple channels, and the data is When reading the data, the latch output is used as a clock signal, and after confirming the arrival of the clock signal, the data of all channels are held in the latch circuit after a certain period of time when it is estimated that the data is latched in the latch circuit. 1. A control device for a magnetic recording device, comprising a central processing unit having a function of reading data in a magnetic recording device, and preventing reading errors due to skew.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9495888U JPH0216463U (en) | 1988-07-18 | 1988-07-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9495888U JPH0216463U (en) | 1988-07-18 | 1988-07-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216463U true JPH0216463U (en) | 1990-02-01 |
Family
ID=31319555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9495888U Pending JPH0216463U (en) | 1988-07-18 | 1988-07-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216463U (en) |
-
1988
- 1988-07-18 JP JP9495888U patent/JPH0216463U/ja active Pending
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