JPS58133615A - Data reader - Google Patents

Data reader

Info

Publication number
JPS58133615A
JPS58133615A JP1610282A JP1610282A JPS58133615A JP S58133615 A JPS58133615 A JP S58133615A JP 1610282 A JP1610282 A JP 1610282A JP 1610282 A JP1610282 A JP 1610282A JP S58133615 A JPS58133615 A JP S58133615A
Authority
JP
Japan
Prior art keywords
signal
circuit
outputs
instruction
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1610282A
Other languages
Japanese (ja)
Inventor
Takashi Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1610282A priority Critical patent/JPS58133615A/en
Publication of JPS58133615A publication Critical patent/JPS58133615A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals

Abstract

PURPOSE:To recognize the marginal rate of generation of readout errors at an arbitrary recording position, by suitably changing the amount of phase difference to be changed relatively with the instruction of the upper-order device or a maintenance device. CONSTITUTION:A peak point detection circuit 14 inputs a reading signal 101 and outputs a peak sense signal 102. A discriminating signal generation circuit 15 outputs a window signal 103 taking a minimum pulse interval of pulses b1-b5 as a period. A reading data signal 104 is outputted from an AND circuit 16. In the state as indicated above, when an instruction signal 107 or 108 is given from the upper-order device 21 or the maintenance device 22 to a phase difference set circuit 17, the circuit 17 outputs a marginal mode signal 105 to the circuit 15, which changes the phase of the data window of the signal 103 relatively to the pulse of a peak sense signal 102.
JP1610282A 1982-02-03 1982-02-03 Data reader Pending JPS58133615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1610282A JPS58133615A (en) 1982-02-03 1982-02-03 Data reader

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1610282A JPS58133615A (en) 1982-02-03 1982-02-03 Data reader

Publications (1)

Publication Number Publication Date
JPS58133615A true JPS58133615A (en) 1983-08-09

Family

ID=11907149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1610282A Pending JPS58133615A (en) 1982-02-03 1982-02-03 Data reader

Country Status (1)

Country Link
JP (1) JPS58133615A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0244665A2 (en) * 1986-04-30 1987-11-11 International Business Machines Corporation Apparatus for, and a method of, obtaining a measure of data detection error

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0244665A2 (en) * 1986-04-30 1987-11-11 International Business Machines Corporation Apparatus for, and a method of, obtaining a measure of data detection error

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