JPH02164058A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPH02164058A JPH02164058A JP32123188A JP32123188A JPH02164058A JP H02164058 A JPH02164058 A JP H02164058A JP 32123188 A JP32123188 A JP 32123188A JP 32123188 A JP32123188 A JP 32123188A JP H02164058 A JPH02164058 A JP H02164058A
- Authority
- JP
- Japan
- Prior art keywords
- package
- check
- chip
- internal wiring
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 abstract 2
- 238000007789 sealing Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 208000003443 Unconsciousness Diseases 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＩＣ（半導体集積回路）パッケージ、特に外
部リードの数が多い１例えばＦＬＡＴ（フラット）パッ
ケージ、ＰＧＡ （ピングリットアレイ）パッケージ等
に関する。ＦＬＡＴパッケージ、ＰＧＡパッケージ等で
は、チップ自体は小さくても外部へ取出すべきリード数
が多いので、ＩＣパッケージが大きくなる。そのため、
ＩＣチップを搭載する基板全面の太きさのキャップを封
止することが難しいので、キャップはＩＣチップ部分の
みにとどめ、ＩＣチップとボンディングワイヤする配線
がＩＣチップ搭載基板のキャップ封止部分より外側では
内部に配線するようにして、ＩＣチップ搭載基板の各リ
ード端子に接続している。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to IC (semiconductor integrated circuit) packages, particularly those having a large number of external leads, such as FLAT (flat) packages, PGA (pin grid array) packages, etc. . In FLAT packages, PGA packages, etc., even though the chip itself is small, there are many leads that must be taken out to the outside, so the IC package becomes large. Therefore,
Since it is difficult to seal a cap that is as thick as the entire surface of the board on which the IC chip is mounted, the cap should be applied only to the IC chip area, and the wiring that connects the IC chip to the bonding wire should be placed outside the cap-sealed part of the IC chip mounting board. Then, it is wired internally and connected to each lead terminal of the IC chip mounting board.
ところで、この種のＩＣパフケージでは、リード端子と
して、ＩＣ本来の動作に必要な入出力信号、電源、アー
ス用端子が設けられているが、ＩＣチップに設けるチェ
ック素子に接続し測定を行なうためのリード端子はない
、また、パッケージ平面の大きさからこのようなリード
端子を配置する余地は少ない。By the way, in this type of IC puff cage, terminals for input/output signals, power supply, and ground necessary for the original operation of the IC are provided as lead terminals. There are no lead terminals, and there is little room for arranging such lead terminals due to the size of the package plane.
また、チェック素子（トランジスタ・抵抗等）は、ＩＣ
の製造途中または製造後にウェーハの状態でチェックす
ることが主目的であったため、ＩＣパッケージに組立後
のチェック素子用のリードを特別に設けることはなかっ
た。In addition, check elements (transistors, resistors, etc.) are IC
Since the main purpose was to check the wafer state during or after manufacturing, the IC package was not specially provided with leads for check elements after assembly.
しかし、現実問題として、ＩＣパッケージに組立てた後
で、チェック素子を測定したい場合が生ずる０例えば、
ＩＣ製造後、各種テストを実行して、不良の発生が多い
場合に、不良原因をチェックする必要が生ずる。このと
きにはＩＣパッケージのキャップをはがして行なわなけ
ればならなかった。また、放射線照射試験のように、電
源電圧をかけた状態で放射線照射をしなければならない
試験では、従来のチェック素子ではバイアスをかけられ
ないため、半導体装置と等価的な評価が不可能である。However, as a practical matter, there are cases where it is desired to measure the check element after it has been assembled into an IC package.
After IC manufacturing, it becomes necessary to perform various tests and check the cause of the failures if many failures occur. At this time, the cap of the IC package had to be removed. In addition, in tests such as radiation irradiation tests that require radiation to be irradiated with a power supply voltage applied, conventional check elements cannot apply bias, making it impossible to perform evaluations equivalent to those of semiconductor devices. .
したがって、照射後キャップをはずして、チェック素子
によって劣化状況の検δ・１を行なっても意味がないと
いう欠点があった。Therefore, there is a drawback that there is no point in removing the cap after irradiation and checking the deterioration state using the check element δ·1.
本発明の目的は、上記の事情に鑑み、ＩＣパッケージに
チップ對人後においても、チップのチェック素子の測定
を行なうことのできるＩＣパッケージを提供することに
ある。SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide an IC package in which the check elements of a chip can be measured even after the IC package is assembled.
〔課題を解決するための手段〕
本発明のＩＣパッケージは、正規のリード配列位置以外
の部分に、パッケージ表面から接触できる導電部材を設
け、該導電部材がパッケージ内部配線を介して、ＩＣチ
ップのチェック素子と電気接続されるようにしたもので
ある。[Means for Solving the Problems] The IC package of the present invention is provided with a conductive member that can be contacted from the package surface in a portion other than the regular lead arrangement position, and the conductive member connects the IC chip through the internal wiring of the package. It is designed to be electrically connected to the check element.
チェック素子の各端子が、ワイヤボンディングにより内
部配線に結ばれ、この内部配線に導電接続された導電部
材が、ＩＣパッケージの外側から接触できるので、キャ
ップを外さないでもチェック素子の測定が可使である。Each terminal of the check element is connected to the internal wiring by wire bonding, and the conductive member connected to this internal wiring can be contacted from outside the IC package, so the check element can be measured without removing the cap. be.
また、正規のリード配列以外の部分であるから、プリン
ト基板に装着する場合に特に不都合は生じない。In addition, since this is a part other than the regular lead arrangement, there will be no particular inconvenience when mounting it on a printed circuit board.
以下、図面を参照して、本発明の一実施例につき説明す
る。この実施例はＦ Ｌ Ａ Ｔ ／＜ツケージの場合
で、第１図はキャップ封入後のＩＣ／ぐッケージ平面図
である。１がＩＣチップ搭載基板、２がキャップ、３が
リードである。リード３はＦＬＡＴパッケージであるの
で、ＩＣチップ搭ａ基板１の上面から、横方向に突出し
ている。１１，１２．１３はチェック素子に導電接続が
なされた導電部材（以後チェック用導体という）であっ
て、外側から容易にチェック用導体の一端部に接触でき
、そして、他端部は。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. This embodiment is for the case of F L A T /< package, and FIG. 1 is a plan view of the IC/package after being sealed with a cap. 1 is an IC chip mounting board, 2 is a cap, and 3 is a lead. Since the lead 3 is a FLAT package, it protrudes laterally from the upper surface of the IC chip-mounted substrate 1. Reference numerals 11, 12, and 13 are conductive members (hereinafter referred to as check conductors) electrically connected to the check element, and one end of the check conductor can be easily contacted from the outside, and the other end is.
ＩＣチップ搭載基基板の内部配線と接続されている。It is connected to the internal wiring of the IC chip mounting board.
第２図は、ＩＣチップ搭載基基板において、第１図のＡ
Ａ’線断面に相当する図（ただし寸法を拡大）である、
ＩＣチップ４は凹部にグイボンディングされて、さらに
、内部配線の上記凹部近傍の接続部（ステッチ）とワイ
ヤボンディングされる。この図でワイヤ５と接続してい
る内部配線６は、リード３に接続される通常の配線であ
る。ワイヤ７と接続される内部配線８は、本発明の実施
に係るチェック用導体１２と接続される配線である。Figure 2 shows the A of Figure 1 in the IC chip mounting substrate.
This is a diagram corresponding to the A' line cross section (however, the dimensions are enlarged).
The IC chip 4 is wire-bonded to the recess, and further wire-bonded to the connecting portion (stitch) of the internal wiring near the recess. The internal wiring 6 connected to the wire 5 in this figure is a normal wiring connected to the lead 3. The internal wiring 8 connected to the wire 7 is a wiring connected to the check conductor 12 according to the embodiment of the present invention.
さらに、わかり易いように、第３図に、ＩＣチップ搭載
基板１のチェック素子１０の近傍部分を透視図的に示し
た。この図の黒く塗りつぶした部分は基板内にあり、実
際には外から見えない部分である。なお、１１′〜１３
′はチェック用導体１１〜１３の接続する部分を示す。Furthermore, for ease of understanding, FIG. 3 shows a perspective view of a portion of the IC chip mounting board 1 near the check element 10. The blacked-out parts in this figure are inside the board and are not actually visible from the outside. In addition, 11' to 13
' indicates the part to which the check conductors 11 to 13 are connected.
図において、チェック素子ｌＯはトランジスタであって
、その電極とステッチ３１〜Ｓ３とがワイヤボンディン
グされ、ステッチ５ＩＮＳ３はそれぞれ内部配線で、チ
ェック導体１３゜１２．１１と接続される。In the figure, check element IO is a transistor, and its electrodes are wire-bonded to stitches 31 to S3, and each stitch 5INS3 is connected to check conductor 13.degree. 12.11 by internal wiring.
以上説明した例は、ＦＬＡＴパッケージであるが、ＰＧ
Ａパッケージに適用できることはいうまでもない、また
、プラスチックパッケージのＤＩＰ、チップキャリアパ
ッケージにも適用できる。The example explained above is a FLAT package, but the PG
Needless to say, it can be applied to the A package, and also to DIP plastic packages and chip carrier packages.
以上説明したように本発明では、半導体集植回路内のチ
ェック素子とＩＣパッケージ内のステッチとをワイヤボ
ンディングで接続し、ステッチとチェック用導体とを内
部配線で接続することにより、パフケージ封入後のチェ
ック素子の測定を、パッケージの外からチェック用導体
に接触することで可能としている。また。As explained above, in the present invention, the check element in the semiconductor integrated circuit and the stitch in the IC package are connected by wire bonding, and the stitch and the check conductor are connected by internal wiring. The check element can be measured by contacting the check conductor from outside the package. Also.
放射線劣化試験のように、バイアスをかけて試験をする
場合にも、チェック素子にバイアスをかけることができ
るので、半導体果粒回路の内部素子と等価な条件でチェ
ックが可能である。Even when performing a test with a bias applied, such as in a radiation deterioration test, the check element can be biased, so it is possible to check under conditions equivalent to the internal elements of a semiconductor chip circuit.
図面は本発明の実施例に係り、第１図はＦＬＡＴパッケ
ージに適用した実施例の平面図、第２図はキャップをは
ずした第１図のＡＡ’線断面図、第３図は導電部材（チ
ェック用導体）近傍の配線状況を説明するための一部透
視図である。
１・・・ＩＣチップ搭載基板、
２・・・キャップ、 ３・・・リード、４・・・
ＩＣチップ、 ５，７・・・ワイヤ、６．８・・・
内部配線、 １０・・・チェック素子、１１．１２．
１３・・・導電部材
（チェック用導体）。
第３図The drawings relate to embodiments of the present invention; FIG. 1 is a plan view of the embodiment applied to a FLAT package, FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1 with the cap removed, and FIG. 3 is a conductive member ( FIG. 3 is a partially perspective view for explaining the wiring situation near the check conductor. 1...IC chip mounting board, 2...cap, 3...lead, 4...
IC chip, 5,7... wire, 6.8...
Internal wiring, 10... Check element, 11.12.
13... Conductive member (conductor for checking). Figure 3
Claims (1)
部分に、パッケージ表面から接触できる導電部材を設け
、該導電部材がパッケージ内部配線を介して、ＩＣチッ
プのチェック素子と電気接続されることを特徴とするＩ
Ｃパッケージ。The IC package is characterized in that a conductive member that can be contacted from the package surface is provided at a portion other than the regular lead arrangement position, and the conductive member is electrically connected to a check element of the IC chip via the package internal wiring. I
C package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32123188A JPH02164058A (en) | 1988-12-19 | 1988-12-19 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32123188A JPH02164058A (en) | 1988-12-19 | 1988-12-19 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02164058A true JPH02164058A (en) | 1990-06-25 |
Family
ID=18130278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32123188A Pending JPH02164058A (en) | 1988-12-19 | 1988-12-19 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02164058A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
-
1988
- 1988-12-19 JP JP32123188A patent/JPH02164058A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808357A (en) * | 1992-06-02 | 1998-09-15 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
| US6031280A (en) * | 1992-06-02 | 2000-02-29 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
| US6271583B1 (en) | 1992-06-02 | 2001-08-07 | Fujitsu Limited | Semiconductor device having resin encapsulated package structure |
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