JPH02163988A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH02163988A JPH02163988A JP31875388A JP31875388A JPH02163988A JP H02163988 A JPH02163988 A JP H02163988A JP 31875388 A JP31875388 A JP 31875388A JP 31875388 A JP31875388 A JP 31875388A JP H02163988 A JPH02163988 A JP H02163988A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- semiconductor device
- case material
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000010396 two-hybrid screening Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000005476 soldering Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000010397 one-hybrid screening Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Landscapes
- Casings For Electric Apparatus (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は混成集積回路に関し、特に混成集積回路内に書
き込み、消去可能なＲＯＭが内蔵きれた混成集積回路に
関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit in which a ROM that can be written and erased is built-in.
（ロ）従来の技術
通常、混成集積回路は第３図に示す如く、混成集積回路
基板（２１）上に複数の回路素子（２２）が固着され、
回路素子（２２）を密封封止するために樹脂性のケース
材（２３）が混成集積回路基板（２１）に固着され一体
化されている。(B) Conventional technology Usually, as shown in FIG. 3, a hybrid integrated circuit has a plurality of circuit elements (22) fixed on a hybrid integrated circuit board (21).
A resin case material (23) is fixed and integrated with the hybrid integrated circuit board (21) in order to hermetically seal the circuit element (22).
斯る混成集積回路にＥＰＲＯＭあるいはマイフン等の所
定のデータを書き込み、消去することができる半導体素
子を固着実装する場合は第４図に示す如く、半導体チッ
プ（２４）を基板（２１）上にグイボンドしてケース材
（２３）で封止する構造あるいは第５図に示す如く、半
導体チップがｔｓｍ封止された半導体装置（２５）を基
板（２１）上に半田付けしてケース材〈２３）で封止す
る構造が一般的であった。When a semiconductor element such as an EPROM or a memory card capable of writing and erasing predetermined data is fixedly mounted on such a hybrid integrated circuit, the semiconductor chip (24) is mounted on the substrate (21) by bonding, as shown in FIG. Alternatively, as shown in FIG. 5, a semiconductor device (25) in which a semiconductor chip is TSM-sealed is soldered onto a substrate (21) and sealed with a case material (23). A sealed structure was common.
（ハ）発明が解決しようとする課題
斯るＥＰＲＯＭあるいはマイコン等の所定のデータを書
き込み、消去することができる半導体素子が内蔵される
混成集積回路では、ケース材が固着一体止されているた
めに素子のデータの変更があれば混成集積回路自体の交
換を行っていた。(c) Problems to be Solved by the Invention In hybrid integrated circuits such as EPROMs or microcomputers that contain semiconductor elements that can write and erase predetermined data, the case material is fixed and fixed. If there was a change in element data, the hybrid integrated circuit itself had to be replaced.
その理由として半導体素子自体の交換が非常に困難であ
る。また交換中に他の素子が破損する恐れがある。The reason for this is that it is extremely difficult to replace the semiconductor element itself. Furthermore, there is a risk that other elements may be damaged during replacement.
更に従来の混成集積回路構造で多品種少量生産を行う場
合には、ＥＦＲＯＭ等の半導体素子のデータが異なるた
めに異種の製造ライン又は製造装置を必要とすると共に
製造期限が長くなり製造コストが高くなる問題があった
。Furthermore, when performing high-mix, low-volume production using the conventional hybrid integrated circuit structure, different types of manufacturing lines or manufacturing equipment are required because the data of semiconductor elements such as EFROM are different, and the manufacturing deadline is lengthened, resulting in high manufacturing costs. There was a problem.
（ニ）課題を解決するための手段
本発明は上述した課題に鑑みて為されたものであり、複
数の回路素子が固着された二枚の混成集積回路基板と、
前記二枚の混成集積回路基板を離間固着し、前記二枚の
混成集積回路基板と平行に配置される中敷板を有するケ
ース材と、少なくとも一方の前記混成集積回路基板と前
記中敷板との間に弾性力を有する導電性シートを介して
配ａすれた半導体装置とを備えて解決する。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes two hybrid integrated circuit boards to which a plurality of circuit elements are fixed,
A case material having an insole plate that fixes the two hybrid integrated circuit boards apart from each other and is arranged parallel to the two hybrid integrated circuit boards, and between at least one of the hybrid integrated circuit boards and the insole plate. and a semiconductor device disposed through a conductive sheet having elastic force.
（＊）作用
この様に本発明に依れば、二枚の混成集積回路基板の少
なくとも一方の混成集積回路基板とケース材の中敷板と
の間に弾性力を有する導電性シートを介して半導体装置
を配置することにより、半導体装置が混成集積回路基板
と中敷板によって押圧されるために半田付レスの接続が
行える。(*) Function As described above, according to the present invention, semiconductors are transferred between at least one of the two hybrid integrated circuit boards and the insole plate of the case material through a conductive sheet having an elastic force. By arranging the device, the semiconductor device is pressed by the hybrid integrated circuit board and the insole plate, so that connection without soldering can be performed.
（へ）実施例
以下に第１図に示した実施例に基づいて本発明の混成集
積回路を詳細に説明する。(F) Embodiment The hybrid integrated circuit of the present invention will be explained in detail below based on the embodiment shown in FIG.
本発明の混成集積回路は第１図に示す如く、二枚の混成
集積回路基板（１）（２）と、二枚の混成集積回路基板
（１）（２）を離間固着し夫々の基板（１）（２）を仕
切る中敷板（３）を有するケース材（４）と、少なくと
も一方の混成集積回路基板（１）（２）と中敷板（３）
との間に配置された導電性シート（５）及び半導体装置
（６）とから構成される。As shown in FIG. 1, the hybrid integrated circuit of the present invention includes two hybrid integrated circuit boards (1) and (2), and two hybrid integrated circuit boards (1 and 2) that are fixedly spaced apart from each other. 1) A case material (4) having an insole plate (3) that partitions (2), at least one hybrid integrated circuit board (1), (2) and an insole plate (3).
It is composed of a conductive sheet (5) and a semiconductor device (6) arranged between the conductive sheet (5) and the semiconductor device (6).
二枚の混成集積回路基板（１）（２）はセラミックスあ
るいは金属基板を用いることができ、本実施例では金属
基板、特に絶縁処理されたアルミニウム基板を用いるも
のとする。夫々の基板（１）（２）の−主面には絶縁樹
脂層（図示しない）を介して銅箔が貼着され、その銅箔
をエツチングして所望形状の導電路（７）（８）が形成
されている。The two hybrid integrated circuit boards (1) and (2) can be ceramic or metal substrates, and in this embodiment, a metal substrate, particularly an insulated aluminum substrate, is used. Copper foil is adhered to the main surface of each substrate (1) (2) via an insulating resin layer (not shown), and the copper foil is etched to form conductive paths (7) (8) in a desired shape. is formed.
その導電路（７）（８）上にはペアチップ状のＩＣ。On the conductive paths (7) and (8) are paired chip ICs.
ＬＳＩ、 トランジスタ、チップコンデンサー及びチ
ップ抵抗等の複数の回路素子（９）（ｔｏ）が所定の接
着によって固着され、近傍の導電路（７）（８）上にワ
イヤポンディングされている。A plurality of circuit elements (9) (to) such as LSI, transistors, chip capacitors, and chip resistors are fixed by predetermined adhesives and wire bonded onto nearby conductive paths (7) and (8).
夫々の導電路（７バ８）が延在形成される所定位置には
半導体装置（６）を接続するための専用の固着パッド（
７’＞（８’）が形成きれている。半導体装置（６）は
固着バッド（７゛八８″）上に直接実装されるものでは
なく、半導体装置（６）の交換が容易に行える様に導電
性シート（５）を介して接続されるものである。Dedicated fixing pads (for connecting the semiconductor device (6)) are provided at predetermined positions where the respective conductive paths (7 bars 8) are extended.
7'>(8') is completed. The semiconductor device (6) is not directly mounted on the fixing pad (7'88''), but is connected via a conductive sheet (5) so that the semiconductor device (6) can be easily replaced. It is something.
半導体装置（６）はＥＰＲＯＭ、ＥＥＰＲＯＭ、マイコ
ン等の所定データの書き込み、消去可能なチップが樹脂
モールドされた、例えばブリップチップ型のものであり
、その半導体装置（６）の底面には複数の電極（１１）
が設けられており、その電極（１１）は導電性シート（
５）を介して導電路（７’＞（８’）と接続されること
になる。The semiconductor device (6) is, for example, a blip-chip type in which a chip such as an EPROM, EEPROM, or microcomputer in which predetermined data can be written and erased is molded in resin, and a plurality of electrodes are provided on the bottom surface of the semiconductor device (6). (11)
is provided, and its electrode (11) is a conductive sheet (
5), it will be connected to the conductive path (7'>(8')).
一方、導電性シート（５）はある程度弾性力を有するゴ
ム又は合成樹脂から成る絶縁シートで第２図に示す如く
、板状に形成され、その厚さ方向に線状導体（１２）が
複数本埋め込まれており、導電性シート（５）の両面か
らは複数の線状導体（１２）が突出されている。斯る導
電性シート（５）は特開昭６２−２２９７１４号公報、
特開昭５９−５８７０９号公報に記載されている。On the other hand, the conductive sheet (5) is an insulating sheet made of rubber or synthetic resin that has some degree of elasticity, and is formed into a plate shape as shown in Fig. 2, and has a plurality of linear conductors (12) in the thickness direction. A plurality of linear conductors (12) protrude from both sides of the conductive sheet (5). Such a conductive sheet (5) is disclosed in Japanese Patent Application Laid-Open No. 62-229714,
It is described in Japanese Patent Application Laid-Open No. 59-58709.
導電性シート（５）を介して接続される半導体素子（６
）はケース材（４）と夫々の基板（１）（２）とを固着
する際に挾持されることによって接続が行われる。A semiconductor element (6) connected via a conductive sheet (5)
) are clamped when fixing the case material (4) and the respective substrates (1) and (2), thereby making the connection.
二枚の基板（１）（２）を離間固着するケース材（６）
は枠状に形成され、その略中間部分に基板（１）（２）
と平行する様な中敷板（３）が設けられている。即ち、
半導体装置（６）はこの中敷板（３）と基板（１）（２
）とによって導電性シート（５）を介して挾持されるこ
とになる。更にこの中敷板（３）には半導体装置（６）
、あるいは半導体装置（６）及び導電性シート（５）を
位置規制するだめの枠部り１３）が設けられているため
、ケース材（４）と基板（１バ２）とを一体止する場合
でも位置ズレ等を起こすことはない。当然のことながら
、中敷板（３）に設けられた枠部（１３）は導電性シー
ト〈５〉が当接される固着パッド（７゛）（８′〉の略
真上（あるいは下）に位置する様にあらかじめ設定され
ている。Case material (6) that separates and fixes two boards (1) and (2)
is formed into a frame shape, and the substrates (1) and (2) are placed approximately in the middle of the frame.
An insole plate (3) is provided that is parallel to the insole plate (3). That is,
The semiconductor device (6) consists of this insole plate (3) and the substrates (1) and (2).
) are sandwiched between the conductive sheets (5). Furthermore, this insole board (3) is equipped with a semiconductor device (6).
, or when the case material (4) and the substrate (1 bar 2) are integrally fixed because a frame portion 13) is provided to restrict the position of the semiconductor device (6) and the conductive sheet (5). However, it does not cause misalignment. Naturally, the frame (13) provided on the insole board (3) is located almost directly above (or below) the fixing pad (7゛) (8') on which the conductive sheet <5> comes into contact. The location is preset.
二枚の基板（１）（２）とケース材（４）は半導体装置
（６）の交換が容易に行えるために第１図に示す如く、
ビス（１４）によってビス止めされている。このとき、
半導体装置（６）と当接されない導電性シート（５）の
先部はケース材（４）の段差部＜１５）より若干突出さ
れた状態である。この結果、基板＜１）（２）をケース
材（４）にビス止めすると、半導体装置（６）が導電性
シート（５）を介して押圧きれることになり、半導体装
置（６）の接続が行われる。The two substrates (1) and (2) and the case material (4) are used as shown in Fig. 1 in order to facilitate the replacement of the semiconductor device (6).
It is fixed with screws (14). At this time,
The leading end of the conductive sheet (5) that is not in contact with the semiconductor device (6) is in a state of being slightly protruded from the stepped portion <15) of the case member (4). As a result, when the substrate <1) (2) is screwed to the case material (4), the semiconductor device (6) is pushed through the conductive sheet (5), and the connection of the semiconductor device (6) is interrupted. It will be done.
断る本発明に依れば、二枚の基板（１）（２）を固着す
るケース材（４）に中敷板（３）を設け、中敷板（３）
と夫々の基板（１）（２）間に導電性シート（５）を介
して樹脂モールドされた半導体装置（６）を配置するこ
とにより、半田付けを用いることなく、半導体装置（６
）の接続が行え、半導体装置（６）の交換が容易に行え
る。According to the present invention, the insole plate (3) is provided on the case material (4) that fixes the two substrates (1) and (2), and the insole plate (3)
By placing the resin-molded semiconductor device (6) between the substrates (1) and (2) through the conductive sheet (5), the semiconductor device (6) can be assembled without using soldering.
) can be connected, and the semiconductor device (6) can be easily replaced.
（ト）発明の効果
以上に詳述した如く、本発明に依れば、二枚の基板を固
着するケース材に中敷板を設け、中敷板と基板間に導電
性シートを介して半導体装置を配置することにより、半
田付レスで樹脂モールドされた半導体装置の接続が行え
るため、データの書き変えあるいは不良等での半導体装
置の交換が容易に行える。(G) Effects of the Invention As detailed above, according to the present invention, an insole plate is provided in the case material that fixes two substrates, and a semiconductor device is connected between the insole plate and the substrate via a conductive sheet. With this arrangement, resin-molded semiconductor devices can be connected without soldering, making it easy to rewrite data or replace semiconductor devices due to defects.
また、本発明では半導体装置自体の検査工程と、半導体
装置を組込む前の基板との検査工程とが異なるため多品
種少量生産が行える利点を有する。Furthermore, the present invention has the advantage that high-mix, low-volume production can be performed because the inspection process for the semiconductor device itself and the inspection process for the substrate before incorporating the semiconductor device are different.
第１図は本発明の実施例を示す断面図、第２図は本実施
例で用いる導電性シートを示す斜視図、第３図乃至第５
図は従来例を示す断面図である。
（１）（２）・・・混成集積回路基板、 （３）・・・
中敷板、（４）・・・ケース材、 （５）・・・導電性
シート、 （６）・・・半導体装置。Fig. 1 is a sectional view showing an embodiment of the present invention, Fig. 2 is a perspective view showing a conductive sheet used in this embodiment, and Figs.
The figure is a sectional view showing a conventional example. (1)(2)...Hybrid integrated circuit board, (3)...
Insole board, (4)...Case material, (5)...Conductive sheet, (6)...Semiconductor device.
Claims (7)
基板と、 前記二枚の混成集積回路基板を離間固着し、前記二枚の
混成集積回路基板と平行に配置される中敷板を有するケ
ース材と、 少なくとも一方の前記混成集積回路基板と前記中敷板と
の間に弾性力を有する導電性シートを介して配置された
半導体装置とを備えたことを特徴とする混成集積回路。(1) Two hybrid integrated circuit boards to which a plurality of circuit elements are fixed; and an insole plate that is fixedly spaced apart from the two hybrid integrated circuit boards and is arranged parallel to the two hybrid integrated circuit boards. and a semiconductor device disposed between at least one of the hybrid integrated circuit board and the insole plate with an elastic conductive sheet interposed therebetween.
部が設けられ、前記収納部内に前記半導体装置及び前記
導電性シートが収納配置されていることを特徴とする請
求項１記載の混成集積回路。(2) The hybrid integrated circuit according to claim 1, wherein the insole board is provided with a storage section in the direction of the hybrid integrated circuit board, and the semiconductor device and the conductive sheet are stored and arranged in the storage section. integrated circuit.
両面から多数の線状導体が突設されていることを特徴と
する請求項１記載の混成集積回路。(3) The hybrid integrated circuit according to claim 1, wherein the conductive sheet is formed of an insulating sheet and has a large number of linear conductors protruding from both sides thereof.
前記混成集積回路基板と前記ケース材とを固定する際に
前記混成集積回路基板上に押圧接続されていることを特
徴とする請求項１記載の混成集積回路。(4) The semiconductor device is resin-molded and is press-connected onto the hybrid integrated circuit board when fixing the hybrid integrated circuit board and the case material. 1. The hybrid integrated circuit according to 1.
板は前記ケース材にビス止めされていることを特徴とす
る請求項１記載の混成集積回路。(5) The hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit board to which the semiconductor device is connected is screwed to the case material.
規制するための枠部が設けられていることを特徴とする
請求項１記載の混成集積回路。(6) The hybrid integrated circuit according to claim 1, wherein the insole plate of the case material is provided with a frame portion for positionally regulating the semiconductor device.
であることを特徴とする請求項１記載の混成集積回路。(7) The hybrid integrated circuit according to claim 1, wherein the hybrid integrated circuit board is an insulated metal substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31875388A JP2642718B2 (en) | 1988-12-16 | 1988-12-16 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31875388A JP2642718B2 (en) | 1988-12-16 | 1988-12-16 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02163988A true JPH02163988A (en) | 1990-06-25 |
| JP2642718B2 JP2642718B2 (en) | 1997-08-20 |
Family
ID=18102554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31875388A Expired - Lifetime JP2642718B2 (en) | 1988-12-16 | 1988-12-16 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2642718B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006104037A1 (en) * | 2005-03-28 | 2006-10-05 | The Furukawa Electric Co., Ltd. | Metal core substrate reinforcing structure and electric connection box |
-
1988
- 1988-12-16 JP JP31875388A patent/JP2642718B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006104037A1 (en) * | 2005-03-28 | 2006-10-05 | The Furukawa Electric Co., Ltd. | Metal core substrate reinforcing structure and electric connection box |
| US7505283B2 (en) | 2005-03-28 | 2009-03-17 | The Furukawa Electric Co., Ltd. | Reinforcing structure for metal core board and electric connection box |
| JP4956421B2 (en) * | 2005-03-28 | 2012-06-20 | 古河電気工業株式会社 | Metal core board reinforcement structure and electrical junction box |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2642718B2 (en) | 1997-08-20 |
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