JPH02162829A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To fix the output node of a CMOS dynamic circuit to a high or a low level and to prevent the increase in the current consumption attended with the stop of a clock pulse and latchup by detecting the stop state of the clock pulse. CONSTITUTION:A clock pulse phi is converted into a DC voltage V1 by a pulse rectifier circuit PD1 and inverted by an inverter circuit N1 and converted into a DC voltage V2 at a pulse rectifier circuit PD 2. The DC voltages V1, V2 are fed to voltage comparator circuits VC1, VC2 using an intermediate voltage V/2 of an operating power voltage V as a reference voltage and if the clock pulse phi is stopped at a high level, an output signal of the voltage comparator circuits VC1, VC2 goes to a high/low level and the output signal CS of the AND gate circuit G1 changes to a low level. Thus, the output node of the CMOS dynamic circuit is fixed to a high level and the increase in the current consumption and latchup attended with the stop of the clock pulse is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, for example, a CMO device.
The present invention relates to a technique that is effective for use in a semiconductor integrated circuit device having a built-in complementary MO3 (complementary type MO3) dynamic type circuit.

[Conventional technology]

An example of a CMOS dynamic logic circuit is disclosed in Japanese Patent Laid-Open No. 54-89558.

[Problem to be solved by the invention]

Semiconductor integrated circuit devices including conventional CMOS dynamic logic circuits and the like are constructed on the assumption that clock pulses are constantly supplied.
When the clock pulse stops due to some reason, the output node of the dynamic circuit goes into a floating state, and a large through current flows through the CMOS static circuit such as the CMOS inverter circuit that receives the intermediate level, reducing the current consumption. In addition to increasing CMO
This poses a problem of causing serious accidents such as inducing S latch-up and destroying the device.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a clock pulse stop detection circuit.

Another object of the invention is to
An object of the present invention is to provide a semiconductor integrated circuit device having an S dynamic type circuit with an added function of stabilizing the output level.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a rectifier circuit converts a clock pulse to a DC level, and a voltage comparison circuit determines its output voltage level based on a reference voltage to monitor whether or not the clock pulse has stopped.

[For production]

According to the above-mentioned means, by detecting the stop state of the clock pulse, it is possible to prevent the occurrence of inconvenient circuit operations accompanying the stop of the clock pulse, such as fixing the output node of a CMOS dynamic type circuit to a high level or a low level. It can be prevented.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a clock pulse stop circuit according to the present invention.

The circuit element of this embodiment is formed on a single semiconductor substrate such as single-crystal silicon along with other circuits as will be described later using known semiconductor integrated circuit manufacturing techniques.

Clock pulse φ is generated by diode D1 and capacitor c1.
The voltage is supplied to a first pulse rectifier circuit PDI consisting of a resistor R1 and a resistor R1, where it is converted into a DC voltage Vl. In this embodiment, although not particularly limited, the clock pulse φ is
The signal is inverted by the inverter circuit N1 and supplied to a second pulse rectifier circuit PD2 comprising a diode D2, a capacitor C2, a resistor R2, etc. similar to the above, where it is converted into a DC voltage 2.

The respective time constants of the capacitors CI, C2 and the resistors R1, R2 in the pulse rectifier circuits PDI and PD2 change when the clock pulse φ is supplied to the output level V1. V2 is made to have a relatively large time constant such that it is approximately the operating power supply voltage V. In other words, the pulse rectifier circuits PDI and PD2 perform a peak detection operation.

The above-mentioned DC voltages v1 and v2 are supplied to voltage comparison circuits VCI and VO2, which have an intermediate voltage V/2 of the operating power supply voltage (2) as a reference voltage, although not particularly limited thereto. That is, the reference voltage V/2 is supplied to the inverting inputs (-) of the voltage comparison circuits VCI and VO2, and the DC voltages v1 and v2 are supplied to the non-inverting inputs (+), respectively. Therefore, in a state where the clock pulse φ is being supplied, in other words, in a state where /) Cl Sokhals φ is periodically changing to high level/low level, for example, the clock pulse φ
When clock pulse φ is at a high level, the capacitor CI is charged up through the diode D1, and when the clock pulse φ is at a low level, the output of the inverter circuit N1 is at a high level, and the capacitor C2 is charged up through the diode D2. The charge that has been charged up in the capacitor CI as described above is discharged through the resistor R1 while the clock pulse φ is at a low level, and the charge that has been charged up in the capacitor C2 is
While the clock pulse φ is at a high level, it is discharged through the resistor R2. In this discharge operation, the time constants of the capacitors C1 and C2 and the resistors R1 and R2 are set to be sufficiently large with respect to the period of the clock pulse φ, as described above.Therefore, the DC voltages v1 and 2 are as follows: The operating power supply voltage V minus the forward voltage of the diodes D1 and D2 is set to a high level close to the operating power supply voltage ■. As a result, while the clock pulse φ is being supplied, the output signals of the voltage comparator circuits VCt and VO2 both become high level (logic "1°"), and the output of the AND gate circuit G1 that receives the signals outputs a high level clock signal. A pulse detection signal C8 is formed.

On the other hand, if the clock pulse φ is supplied from an external terminal, the clock pulse φ will stop due to a break in the signal line, poor contact, etc., or if the clock oscillation circuit is built in, the circuit stops operating, etc. In other words, when the level of the clock pulse φ is fixed at a high level or a low level, the DC voltages 1 and 2 become high/low. For example, when the clock pulse φ is at a high level. When the capacitor C1 is stopped in this state, the capacitor C1 continues to be charged up through the diode D1, so the DC voltage V1 becomes high level. Since the output signal of the inverter circuit N1 becomes low level in response to the high level of the clock pulse φ, the diode D2 is turned off, and the DC voltage 2 becomes low level because the charge in the capacitor C2 is discharged by the resistor R2. Therefore, the output signals of the voltage comparison circuits vC1 and VO2 become high/low level, and the output signal C8 of the AND gate circuit G1 changes to low level.

Furthermore, when the clock pulse φ is stopped at a low level, the output of the inverter circuit Nl becomes a high level, and the capacitor C2 is continuously charged up through the diode D2, so that the DC voltage v
2 becomes high level. Due to the low level of the clock pulse φ, the diode D1 is turned off, and the DC voltage 1 becomes low level because the charge in the capacitor C1 is discharged by the resistor R1. Therefore, the voltage comparator circuit VC
The output signals of I and VO2 become low level/high level, and the output signal C3 of the AND gate circuit G1 changes to low level.

In this way, the clock pulse stop detection circuit of this embodiment can detect whether the clock pulse φ is at high level or low level when it stops.

FIG. 2 shows a circuit diagram of an embodiment of a CMOS dynamic type circuit in which the clock pulse stop detection signal C8 is used.

Each circuit element in the figure is formed on a single semiconductor substrate such as single crystal silicon along with the above-described lock pulse stop detection circuit by a known CMO3 integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET consists of a source region, a drain region, and a polysilicon film formed on the semiconductor substrate surface between the source region and the drain 6H region with a thin gate insulating film interposed therebetween. A gate! Consists of poles. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

By this, a semiconductor substrate was formed on it? J
A common substrate gate for l N-channel MOS FETs is configured. The N-type well region constitutes the substrate gate of the P-channel MOS FET formed thereon. The substrate gate or N-type well region of the P-channel MOS FET is coupled to the N source terminal Vcc of FIG.

This circuit consists of a P-channel type precharge MOSFET QI that receives the clock pulse φ to precharge the capacitive load of the output node A, and an N-channel type discharge MOSFET Q2 that receives the clock pulse φ and controls its discharge operation. , both the above MOS
Provided between FETQ1 and Q2, logic block L
Multiple N channels M connected in series and parallel forming BI
O5FETQ3 to Q7 and output inverter circuit N2
It consists of The output inverter circuit is a known CMOS inverter circuit including a P-channel MOS FET and an N-channel MOS FET. Circuits similar to those described above are connected in multiple stages to form a so-called domino circuit.

In this circuit, during the precharge period when the clock pulse φ is set to low level, the precharge MOS
FETQ1'': Turn on Q8, turn off discharge MOSFETQ2 and Q9, and precharge output capacitors A, B, etc. to high level.In the discharge period when clock pulse φ is set to high level, , precharge MOSFETQ1
．． Q8 is turned off, discharge MOSFET Q2
．． By turning on Q9, for example, MOSFET Q3 or Q4 constituting the logic block LBI is turned on,
And when any one of MOSFETs Q5 to Ql is turned on, output node A is discharged to a low level. The low level signal of this output node A is
It is input to the next stage logic block LB2 through the output/impark circuit N2, and together with other similar inputs, the logic block LB2 determines whether or not to discharge the output node B.

In this way, in each logical block connected in multiple stages,
The above precharge MOSFET and discharge MOS
By operating the FET in a complementary manner using a clock pulse φ, a precharge operation and a discharge operation are alternately repeated to perform a logical operation according to the input signal.

In this embodiment, when the clock pulse φ is fixed at a high level and stops, the output inverter circuit N2. The precharge voltage stored in capacitive loads such as nodes A and B consisting of input capacitors such as N3 is applied to the MOS F.
It gradually decreases to an intermediate level due to the drain leakage current of the ET, etc. As a result, from the CMO3 circuit to the output inverter circuit N2. This causes the inconvenience that a through current flows through N3 and the like. Therefore, the above output node A.

P-channel MOSFETs QI O, Ql 1, etc. for pull amplifiers are provided between B, etc. and the power supply voltage Vcc, and the clock pulse stop detection signal C3 is supplied to their gates. When the clock pulse φ stops as described above, the clock pulse stop detection signal C8 changes to low level, and the P-channel MOSFET QI
Turn on O, Ql 1, etc. As a result, the output nodes A, B, etc. are maintained at a high level, so that the generation of the through current as described above can be prevented.

The effects obtained from the above examples are as follows. In other words, (1) A voltage comparator circuit determines the rectified voltage level that converts the clock pulse to a DC level based on the reference voltage, monitors whether or not the clock pulse has stopped, and sets the output node of the CMOS dynamic circuit to a high level. By fixing the voltage to the level, an effect can be obtained in that it is possible to prevent an increase in current consumption, a rough drop, etc. due to the stoppage of clock pulses in a CMOS dynamic type circuit.

(2) As a circuit for detecting whether or not a clock pulse has stopped, the clock pulse and its inverted pulse are each rectified and compared with a predetermined reference voltage, and a detection signal is obtained via an AND gate circuit such as an AND gate circuit. This provides the effect that it is possible to detect whether the clock pulse stops at either the high level or the low level.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the diode constituting the rectifier circuit may be a bipolar transistor in the form of a diode or a MOS FET. When using the above diode or a bipolar transistor equivalent thereto, it may be formed using the known Bi-0MO3 technology. . Furthermore, the voltage comparison circuit may be an inverter circuit or a logic gate circuit that uses a logic threshold voltage as a reference voltage. That is, in the embodiment of FIG.
By omitting the voltage comparator circuits VCI and VO2, the DC voltage Vl
and (2) may be directly input to the AND gate circuit G1. In this case, the logic threshold voltage of the AND gate circuit is used as the reference voltage. If the level of the clock pulse φ is fixed at a high level or a low level when the clock pulse φ is stopped, only one rectifier circuit and a level determination circuit as described above may be required. In this case, it is desirable to provide a lock pulse stop detection circuit as described above for each of them, and use the OR output of the respective detection outputs as the stop detection signal.

In addition to the fact that the clock pulse stop detection signal is used to pull up the floating level in the CMOS dynamic type circuit as described above to the high level of the circuit or to pull it down to the low level of the circuit,
This signal can be widely used as a detection signal for stopping the supply of clock pulses or stopping the operation of an oscillation circuit.

According to the present invention, the clock pulse stop detection circuit can be widely used in various semiconductor integrated circuit devices that operate using periodic pulses such as clock pulses.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the rectified voltage level that converts the clock pulse to a DC level is determined by a voltage comparison circuit based on a reference voltage, and the presence or absence of a stop of the clock pulse is monitored, and the CM
By fixing the output node of the OS dynamic type circuit to a high level, it is possible to prevent an increase in current consumption, a rough drop, etc. due to the stop of the clock pulse in the CMOS dynamic type circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a clock pulse stop detection circuit according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a CMOS dynamic type circuit in which the clock pulse stop detection circuit described above is used. It is a diagram. PDI, PD2...Pulse rectifier circuit, VC1゜VC2...
・Voltage comparator circuit, N1 to N3... input/sj-tor circuit,
Di, D2...Diode, C1, C2...Capacitor, R1, R2...Resistor, G1...And gate circuit, L
Bl, LB2...Logic block Figure 1 Figure 2

Claims (1)

[Claims] 1. A clock pulse stop that includes a rectifier circuit that receives a clock pulse and converts it to a DC level, and a voltage comparison circuit that determines the output voltage level of the rectifier circuit based on a predetermined reference voltage. A semiconductor integrated circuit device comprising a detection circuit. 2. The above clock pulse is supplied from an external terminal, and the stop detection signal formed by the clock pulse stop detection circuit is a CMOS dynamic type configured in the same integrated circuit that operates in response to the above clock pulse. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device controls a switch MOSFET that fixes an output terminal of the circuit at a high level or a low level. 3. The rectifier circuit is composed of a pair of circuits each receiving a clock pulse and its inverted pulse, and the output signals of a pair of voltage comparison circuits provided corresponding to the pair of rectifier circuits are input to an AND gate circuit, 3. The semiconductor integrated circuit device according to claim 1, wherein a clock pulse stop detection signal is obtained from the output thereof.