JPH02162751A - Analog/digital mingling lsi - Google Patents

Abstract

PURPOSE:To prevent crosstalk from generating in a digital signal and an analog signal by a method wherein the low-sensitivity analog terminals of an analog functional cell and the digital terminals of a digital functional cell are respectively led out on both of the upper and lower sides of both functional cells and an analog land wiring, a reference voltage wiring and an analog land wiring for shielding use are built in a standard cell. CONSTITUTION:In an analog functional cell, an analog land wiring region AGND wiring, a reference voltage wiring region VREF wiring and analog land wiring regions for shielding use AGS1 and AGS2 wirings are contained. An isolation region given the potential of the AGS2 wiring is formed in the lower layer of the AGS2 wiring. Moreover, a high-sensitivity analog terminal is led out on the upper side of the cell, low-sensitivity analog terminals are led out on both of the upper and lower sides of the cell by providing an equivalent circuit and a digital terminal is led out on the lower side of the cell. In a digital functional cell, analog land wiring regions for shielding use AGS1 and AGS2 wirings are built in. An isolation region given the potential of the AGS1 wiring is formed in the lower layer of the AGS1 wiring. Moreover, digital input/output terminals are led out on both of the upper and lower sides of the cell by providing an equivalent terminal. As a standard cell, an isolation cell is prepared.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to an LS in which analog circuits and digital circuits are mixed.
This paper relates to the layout design technology of I.

[Conventional technology]

When designing the layout of an LSI in which analog and digital circuits coexist, a group of circuits with a certain function is prepared in advance as a standard cell, and these are arranged and connected with each other with wiring to form a chip. There is a way to design the whole thing. This design method is called the standard cell method.In zero-line design, the performance and operation of the cells have been confirmed in advance, and only the wiring between cells is newly designed, resulting in improved productivity in a short period of time. <
LSI development becomes possible.

In LSI design using this standard cell method,
High-performance analog and
When designing the layout of a digital mixed LSI, there are the following requirements.

(1) Reduce the wiring resistance and parasitic capacitance of analog signal wiring.

(2) Reduce crosstalk between analog and digital signals.

(3) Preventing noise from entering analog elements and analog signal wiring from digital elements and digital signal wiring.

A layout design that does not meet these conditions will degrade the performance of the analog circuit, and the required distortion rate, S/N,
Characteristics such as signal band and signal dynamic range may not be obtained.

Conventionally, the layout design of an analog/digital mixed LSI using the standard cell method has been carried out using the following method, which cannot be said to satisfy all of the above conditions.

FIG. 6 shows an example of a conventional standard cell STD. Standard cell specifications are common for analog functional cells such as operational amplifiers, switches, capacitors, resistors, etc., and digital functional cells such as switch drivers, clock generation circuits, etc., and are used for a wide range of high potential power supplies. It has a built-in wiring area VDD and a low potential power wiring area VSS. For the terminals for connecting to other cell circuits, place the highly sensitive analog terminals (terminal 1, marked ■ in Figure 6), which are susceptible to noise, such as the input of operational amplifiers, on the upper side.
There are low-sensitivity analog terminals that are relatively unaffected by noise, such as the output of an operational amplifier (terminal 2, shown as a mouth in Figure 6), and digital terminals, such as the control terminal of a switch (
In Fig. 6, terminal No. 3 (indicated by .) is drawn out in different directions, such as terminal 3) and terminal 3 shown below. In FIG. 6, P is the origin of the cell, and AD is an analog circuit or a digital circuit.

FIG. 7 shows an example of the arrangement of conventional standard cells. In the figure, STD is a standard cell, 5TDT is a cell column, P is the cell origin, Sl is a low-sensitivity analog wiring area and digital wiring area, S2 is a high-sensitivity analog wiring area,
S3 is the low sensitivity analog wiring area and digital wiring area,
4 is a high-sensitivity analog wiring area, S5 is a low-sensitivity analog wiring area and a digital wiring area, S6 is a high-sensitivity analog wiring area, and the area surrounded by dotted lines indicates a circuit block. The arrangement example shown in FIG. 7 is an example in which cells are arranged in five stages and the terminals of the cells are wired to realize an analog/digital mixed LSI. The two power supplies built into the cells are connected to each other by arranging the cells without gaps. One of the odd-numbered and even-numbered standard cells is placed upside down, and the high-sensitivity analog terminals of the cells, as well as the low-sensitivity analog and digital terminals, face each other, and high-sensitivity analog wiring areas are provided between the cells. S2. S4. S6 and wiring area SL where low-sensitivity analog wiring and digital wiring are mixed.

S2. S3 is formed. Further, a circuit block made up of several standard cells is made up of one stage of cell rows.

Figure 8 shows an example of conventional wiring between standard cells. In the figure, 1 is a high-sensitivity analog terminal, the mouth is a low-sensitivity analog terminal, the fist is a digital terminal, STD is a standard cell, 5TDT is a cell column, THI is polysilicon.
Through hole between aluminum, B is reference voltage terminal, G is analog ground terminal, T is shield potential supply terminal, Wl is thick polysilicon wiring, W2 is thin polysilicon wiring, W
3 is aluminum wiring, C1 is bias wiring, C2 is tab wiring, C3 is low sensitivity analog wiring, C4 is analog ground wiring, C5 is digital wiring, and C is low sensitivity analog wiring. In FIG. 8, all the terminals of the standard cell are made of polysilicon, and the polysilicon wiring from the analog terminal is made thicker in order to lower the resistance. In a wiring area where low-sensitivity analog wiring and digital wiring coexist, wiring is classified into four types of hierarchy and wired in the following order.

■Reference voltage wiring ■Shield potential supply wiring ■Low-sensitivity analog wiring ■Analog ground wiring ■Digital wiring The wiring provides a shield between the low-sensitivity analog wiring (■) and the digital wiring (■).

[Problems to be Solved by the Invention] The conventional standard cells, their arrangement, and inter-cell wiring described above have the following drawbacks.

(1) Analog terminals such as low-sensitivity analog terminals, analog ground terminals, reference voltage terminals, etc. and digital terminals coexist on one side of the cell, so in wiring areas where low-sensitivity analog wiring and digital wiring coexist, these Analog wiring from analog terminals and digital wiring from digital terminals always intersect, resulting in crosstalk between digital and analog signals.

(2) Digital wiring between digital functional cells, such as wiring between a clock generation circuit and a switch driver, and between digital functional cells and analog functional cells that are directly connected to analog elements, such as wiring between a switch driver and a switch. and digital wiring, using the same wiring area where low-sensitivity analog wiring and digital wiring coexist. Therefore, the number of digital wires in this wiring region increases, the number of intersections and the wire length increase, and the noise, crosstalk, and delay characteristics of the digital wire signal between the digital functional cell and the analog functional cell deteriorate.

(3) Since the terminals are drawn out to either the top or bottom of the cell and do not have equivalent terminals, if the connection direction of the wiring does not match the direction of the terminal position of the cell, the wiring will be detoured, and the number of crossings of the wiring and the wiring length increases.

(4) Since the standard cell has only two built-in power supply wirings, and the analog ground wiring and reference voltage wiring are located in the intercell wiring area, the width of these wirings can be made wider and the resistance lowered by automation through program processing. It is difficult to plan. Further, when connecting cell terminals to analog ground and reference voltage wiring in the inter-cell wiring area, the wiring becomes long.

(5) The wiring area where low-sensitivity analog wiring and digital wiring coexist and the analog element area within the cell, and the high-sensitivity analog wiring area and the digital element area within the cell are separated only by the power supply wiring within the cell. Therefore, noise from the digital elements and digital signal wiring mixes into the analog signal wiring from the analog elements through the lower region of the power supply wiring and the substrate.

(6) When both an analog function circuit block and a digital function circuit block exist adjacent to each other in the same cell stage, noise from the digital function circuit block mixes into the analog function circuit block through the board. Also, different power supplies and grounds cannot be supplied to adjacent blocks.

(7) Since a circuit block is composed of a single row of cells, if the width of a cell is large or the number of cells is large, the length of wiring between cells in the circuit block becomes large.

(8) When attempting to connect wires across different wiring regions, highly sensitive analog wires and digital wires intersect, resulting in crosstalk. In order to prevent this crosstalk, the digital wiring must be detoured, which increases the wiring length.

(9) In a wiring area where low-sensitivity analog wiring and digital wiring coexist, the wiring order is fixed, and this restriction makes it unsuitable for automation through program processing.

In wiring areas where low-sensitivity analog wiring and digital wiring coexist, shielding between low-sensitivity analog wiring and digital wiring is achieved using reference voltage wiring and analog ground wiring. Digital noise mixes into the signal, causing voltage fluctuations.

All of the above-mentioned shortcomings of conventional standard cells, their placement, and interconnections between cells are factors that degrade the performance of analog circuits, such as S/N, signal bandwidth, and signal dynamic range, as well as constraints on automation through program processing. This has been an obstacle to the realization of high-performance analog/digital mixed LSIs through system design.

[Means to solve the problem]

In order to solve such problems, a first aspect of the present invention is to provide an analog/digital mixed LSI in which analog circuits and digital circuits coexist, which include an analog functional cell, a digital functional cell, and a separate cell, The analog ground wiring area for the shield, the analog ground wiring area, the reference voltage wiring area, the analog power wiring area, the high-sensitivity analog terminal provided on either the top or bottom, and the digital terminal provided on either the top or bottom, as well as the digital terminal provided on either the top or bottom. The digital function cell has an analog ground wiring area for shielding and a preliminary wiring klA9.
It has an M area, a digital power wiring area, and digital terminals provided on both the upper and lower sides, and the separated cell has an analog ground wiring area for shielding, an analog ground wiring area, a reference voltage wiring area, and an analog power wiring area. It is something.

Further, a second aspect of the present invention is an analog/digital mixed LSI in which analog circuits and digital circuits coexist. It has multiple cell stages composed of one or both of these functional cell rows, and the analog functional cells are connected to the analog ground wiring area for shielding, the analog ground wiring area, the reference voltage wiring area, and the analog power wiring area, either above or below. Same as the high-sensitivity analog terminal provided (it has a digital terminal provided on either the top or bottom and a low-sensitivity analog terminal provided on both the top and bottom), and the digital function cell has an analog ground wiring area for shielding, a spare wiring area, and a digital power supply. It has a wiring area and digital terminals provided on both the upper and lower sides, and the separation cell has an analog ground wiring area for shielding, an analog ground wiring area, a reference voltage distribution vA area, and an analog power distribution klA SI area, and has an analog function cell. A high-sensitivity analog wiring area that connects the high-sensitivity analog terminals of the cell, a low-sensitivity analog wiring area that connects the low-sensitivity analog terminals of the analog function cells, and an analog wiring area that contains a mixture of high-sensitivity and low-sensitivity analog wiring areas. , an analog-to-digital cell wiring area that connects the digital terminals of the analog functional cells and the digital terminals of the digital functional cells, a digital-digital cell wiring area that connects the digital terminals of the digital functional cells, and an analog-to-digital cell wiring area that connects the digital terminals of the digital functional cells. The wiring area between cell stages is composed of one or more of the digital wiring area where the digital wiring area and the digital-digital cell wiring area coexist, and the separated cells are the digital wiring area, the analog-digital cell wiring area, and the digital wiring area. - The high-sensitivity analog wiring area, the low-sensitivity analog wiring area, and the analog wiring area are arranged adjacent to the cell rows above and below the boundary between one of the digital cell wiring areas and the address wiring area, and the high-sensitivity analog wiring area, low-sensitivity analog wiring area, and analog wiring area are connected to the analog functional cell rows. The analog-to-digital cell wiring area constitutes the wiring area between the analog functional cell column and the digital functional cell column, and the digital-digital cell wiring area constitutes the wiring area between the digital functional cell column. A wiring area is configured, and a digital wiring area is configured to configure a wiring area that connects only the digital terminals of the analog functional cell array.

[Effect]

In the analog/digital mixed LSI according to the present invention, crosstalk between digital and analog signals occurs, and characteristics of noise, crosstalk, and delay of digital wiring signals between digital function cells and analog function cells are improved. do.

〔Example〕

The present invention incorporates an analog ground, a reference voltage, and an analog ground wiring for shielding into an analog standard cell, and broadly divides the inter-cell wiring area into two areas: the analog wiring area and the digital wiring area, and further divides the analog wiring area into The wiring is divided into two types: high-sensitivity analog wiring area and low-sensitivity analog wiring area, while the digital wiring area is divided into two types: analog-digital functional cell wiring area and digital-digital functional cell wiring area. It is characterized by interlayer shielding to prevent performance deterioration due to the intersection of analog wiring and digital wiring, thereby solving the drawbacks of the conventional technology.

An embodiment of a standard cell according to the first aspect of the present invention is shown in FIG. In FIG. 1, ■ is a high-sensitivity analog terminal, opening is a low-sensitivity analog terminal, * is a digital input terminal, ◯ is a digital output terminal, P is the origin of the cell, and hatching indicates a separation area.

The specifications of the standard cell are the analog function cell (Figure 1 (
a)) and the digital function cell (Fig. 1(b)). Two wide power supplies AVSS for analog function cells
, AVDD wiring, analog ground AGND wiring using one-layer aluminum, reference voltage REF wiring, and two analog ground AGSI and AGS2 wiring for shielding are built-in. Analog ground AGS for shielding on one side
An isolation region to which the potential of AGS2 is applied is formed below the two wirings. As terminals for connecting to other cell circuits, high-sensitivity analog terminals made of polysilicon or double-layer aluminum are provided on the top, low-sensitivity analog terminals are provided with equivalent terminals on both the top and bottom, and digital terminals are provided on the bottom. It's pulled out to the side.

On the other hand, in a digital function cell, two wide power supplies DV
In addition to the SS and DVDD wiring, two shielding analog ground wirings AGS1 and AGS2 using single-layer aluminum are built-in. Analog ground AC for shielding on one side
The lower layer of the 5l wiring is 19i due to the potential of AGSI.
It forms the tl region.

Digital input/output terminals made of polysilicon or double layer aluminum are used as terminals for connecting to other cell circuits.
Equivalent terminals are provided and pulled out both at the top and bottom.

In addition, as a standard cell, a separation cell is prepared in which the entire cell is an isolation region in order to separate the power supply and ground of the same stage, and to separate the analog function circuit block and the digital function circuit block.

FIG. 2 shows an example of the arrangement of standard cells according to the second aspect of the present invention. In the figure, A is an analog functional cell, AT is an analog functional cell column, P is the origin of the cell,
D is a digital functional cell, DT is a digital functional cell string, S
S is a separation cell, Sll, S15. S16 is a low sensitivity analog wiring area, 512 is a digital wiring area, S13
is a high-sensitivity analog wiring area, 314 and 318 are analog wiring areas, S17 is a digital wiring area, and 319. S20
is the wiring area between analog and digital functional cells, S21. S
22 is a wiring area between digital and digital functional cells.

Further, the area indicated by a thin dotted line is a circuit block, and the thick dotted line indicates a separation area. FIG. 2 is an example of realizing an analog/digital mixed LSI by arranging cells in five stages and wiring between the terminals of the cells. In this embodiment, the drawbacks of the prior art are solved by classifying the inter-cell wiring area into the following four types.

As an analog wiring area ■High-sensitivity analog wiring area ■Low-sensitivity analog wiring area As a digital wiring area ■Analog-digital function cell wiring area ■Digital-
Wiring area between digital function cells As a result, the following three combinations of wiring areas above and below a cell column can be created, taking into consideration that analog wiring and digital wiring do not coexist in the same wiring area.
It can be classified into the basic forms of species.

(1) High-sensitivity analog wiring area and low-sensitivity analog wiring area (2) Analog wiring area and digital wiring area (3) Analog-digital functional cell wiring area and digital-digital functional cell wiring area (1) is a digital terminal By applying this to the interconnection area between cells above and below analog function cell rows that do not include cell rows, and arranging one of the odd-numbered cell rows and even-numbered cell rows upside down, high-sensitivity analog terminals can be connected to each other, and low-sensitivity Analog terminals are formed facing each other. As an application of this basic form, low-sensitivity analog wiring can be mixed in the high-sensitivity analog wiring NiA 9M region to form an analog wiring area, and the wiring area can be divided into two areas, an analog wiring area and a low-sensitivity analog wiring area, and low-sensitivity analog wiring It is also possible to mix high-sensitivity analog wiring in the area to form an analog wiring area, and to have two wiring areas: a high-sensitivity analog wiring area and an analog wiring area.

(2) is applied to the inter-cell wiring area above and below the analog functional cell row containing digital terminals, and the analog terminals consisting of high-sensitivity analog terminals and low-sensitivity analog terminals and the digital terminals are formed facing each other. Ru. The analog standard cell used in the present invention has low-sensitivity analog terminals with equivalent terminals on both the top and bottom sides of the cell, so
It can support both (1) and (2) classifications of wiring areas.

As an application of this basic form, the wiring in the digital distribution MA TiJf area can be made to be only the wiring between analog and digital functional cells, or only the wiring between digital and digital functional cells.

(3) is applied to the HpI area between the cells above and below the digital function cell array, and using the equivalent terminals on both the top and bottom sides of the cell,
It is formed by dividing the wiring toward the analog functional cell and the wiring between the digital functional cells into upper and lower wiring regions.

Furthermore, the analog element area in the analog function cell, the low-sensitivity analog wiring area, the digital wiring '1tiA SI area,
And the wiring area between analog and digital function cells is the analog ground A for shielding built into the analog function cell.
They are separated by an isolation region below the GS2 wiring. Also,
The digital element area and analog wiring area in the digital functional cell, and the wiring area between digital and digital functional cells are analog ground A for shielding built into the digital functional cell.
They are separated by an isolation region below the GS 1 wiring. As an application of this basic form, analog-to-digital function cell interconnects are mixed in the digital-to-digital function cell interconnect area 'h'A 971 area to form a digital wiring area, and the wiring area is the analog-to-digital function cell interconnect area and digital wiring area. It is also possible to have two regions.

A circuit block made up of several standard cells is made up of one to two cell rows, and in a block made of two cell rows, different power supplies and grounds are used for the upper and lower cell rows. It is easy to do. Furthermore, by inserting separation cells between blocks, different power supplies and grounds can be used for blocks in which cell rows are adjacent on the left and right. By inserting separation cells between analog function circuit block cells and digital function circuit block cells arranged on the same level, and between an analog function cell column and the digital wiring area next to it, analog The element area, digital element area, and digital wiring area can be clearly separated. Furthermore, the two separated cells facing each other in the upper and lower rows are connected vertically in the separation area across the inter-cell wiring area, with the left side of the inter-cell wiring area being an analog wiring area and the right side being an analog-digital function inter-cell wiring area. This is achieved by separating the two wiring areas.

FIG. 3 shows three embodiments of inter-cell wiring according to the second aspect of the present invention. Standard cell terminals are polysilicon or double-layer aluminum, so the basic way to select wiring layers is to use single-layer aluminum for the horizontal wiring in the inter-cell wiring area, and polysilicon or double-layer aluminum for the vertical wiring. shall be. In addition, if there is no intersection with other two-layer aluminum wiring and two-layer aluminum can also be used for horizontal wiring,
The through hole between the aluminum layer and the aluminum layer is omitted, and the wiring is done using only the aluminum layer.

FIG. 3(a) is an example in which there is no digital functional cell in the standard cell row to be arranged, and the analog functional cell does not have a digital terminal. Analog functional cells are arranged in two stages as shown by the cell row AT, with the high-sensitivity analog terminals facing each other (the mouth is a low-sensitivity analog terminal), and the wiring area between the cells in the center is connected to the high-sensitivity analog wiring area M area HA, upper and lower. The wiring area is defined as a low-sensitivity analog wiring area LA. By using low-sensitivity analog equivalent terminals in the low-sensitivity analog wiring area LA, it is possible to clearly separate two types of wiring, high-sensitivity analog wiring and low-sensitivity analog wiring, and prevent high-sensitivity analog wiring and low-sensitivity analog wiring from intersecting. There isn't. Similarly, when the analog functional cell array AT is arranged in one stage, high-sensitivity analog wiring areas and low-sensitivity analog wiring areas can be separated and wired above and below the analog functional cells.

Figure 3) is an example where there is no digital functional cell row in the standard cell row to be placed (and some analog functional cells have digital terminals. Among the analog functional cells, those with digital terminals are shown below). The cells are arranged in two stages with the high-sensitivity analog terminals facing each other.The central inter-cell wiring area is the analog wiring area AW, the top is the low-sensitivity analog wiring area LA, and the bottom is the digital wiring area. D
Let it be W. , This allows analog wiring and digital wiring to be clearly separated and routed. When analog functional cells with digital terminals ○ and are arranged in two stages, upper and lower, the upper and lower wiring areas are both digital wiring areas, and the center is the analog wiring b'A 9M area. Similarly, when analog functional cells are arranged in one stage, analog wiring areas and digital wiring areas can be separated and wired above and below analog functional cells having digital terminals.

FIG. 3(C) is an example in which there are digital functional cells in the standard cell row to be arranged, and there are analog functional cells having digital terminals. In the figure, LAD is an open wA area between analog and digital functional cells, DT is a digital functional cell column, and DD is a wiring area between digital and digital functional cells.

Analog functional cells are arranged in two rows with high-sensitivity analog functional cells facing each other, and cells with digital terminals are arranged only in the second row of cells. Furthermore, the digital functional cells are arranged in one stage below the analog functional cell column AT with the inter-cell wiring area on the digital terminal side in between. As a result, there are four types of inter-cell wiring regions as follows. In other words, the low-sensitivity analog wiring area LA is wired between the low-sensitivity analog equivalent terminal ports of the first analog functional cell row from the top, and the wiring is wired between the analog terminals of the first and second analog functional cell rows from the top. analog wiring area AW, an analog-to-digital functional cell wiring area LAD that connects the digital terminals of the second analog functional cell row and the digital terminals of the third digital functional cell row, and the third digital function cell row. This is a digital-to-digital functional cell interconnect vAfIJI area LDD in which the digital terminals of the cells are wired. By dividing the wiring between analog and digital functional cells and the wiring between digital and digital functional cells into the upper and lower parts of the third stage digital functional cell row DT using equivalent terminals, analog-digital wiring that is directly connected to analog elements The number of intersections between functional cells and the wiring length are reduced, and the noise and wiring delay characteristics are improved. Also,
Equilateral terminals are also present at the low-sensitivity analog terminal ports of analog function cells, and can be used as wiring that passes up and down the cell row to connect the upper and lower wires of the cell row.

In addition, in FIG. 3, Wit is a polysilicon wiring, W
12 is a single-layer aluminum wiring, and W13 is a double-layer aluminum wiring.

FIG. 4 shows an embodiment of the method for connecting cell terminals and power supply/ground according to the present invention. FIG. 4(a) is an example of a terminal of an analog functional cell, and FIG. 4Tbl is an example of a terminal of a digital functional cell.

In conventional layout methods using standard cells, analog ground wiring, reference voltage wiring, and shield potential supply wiring are mixed with normal wiring between cells. In the analog standard cell used in the present invention, in addition to the power supply wiring, the analog ground wiring AGND, the reference voltage wiring V
REF, analog ground wiring AGS for two shields
I, AGS2 is built into the cell. Therefore, there is no need to mix wiring for supplying analog ground potential, reference voltage, and shield potential with normal wiring between cells. Furthermore, there is no need to route wires above and below the cell and then form through holes to connect to the cell terminals. It is only necessary to create through holes TH1 and TH2 at the intersections of the single-layer aluminum layers.

According to this method, it is easy to treat unused terminals by applying shielding analog ground potential to unused analog terminals or supplying power supply voltage to unused digital input terminals to prevent the influence of noise from unused circuits. possible. In addition, programmable resistors, in which resistors, capacitors, etc. are arranged in an array within a standard cell, and mutual connection wiring is selected using through holes to switch the resistance value and capacitance value.
Capacitive cells can also be easily realized.

In addition, in FIG. 4, Wit is a polysilicon wiring, W
13 is a two-layer aluminum wiring.

In the conventional layout method using standard cells, as shown in Figure 5, which shows an example of a wiring shield, special consideration is not given to the lower layer of high-sensitivity analog wiring and the intersection of analog wiring to prevent crosstalk. It had not been done.

In one embodiment of the layout according to the present invention, intersections of analog wiring are minimized by using four types of wiring areas, and furthermore, for unavoidable intersections,
Wiring shielding is used to suppress performance deterioration due to crosstalk, etc.

Figure 5 (al is an example of a high-sensitivity analog wiring shield. Along the high-sensitivity analog wiring in the analog wiring area,
A polysilicon layer applied with a shielding analog ground potential is placed below it to shield noise from entering the high-sensitivity analog wiring through the substrate.

Figure 5(b) shows the analog wiring AW in the digital wiring area.
This is an example of an I-shield. For the analog wiring that had to pass through the digital wiring area to shorten the wiring length, a part of the single-layer aluminum digital wiring was changed to polysilicon, and it was used as a shield between the eyebrows of the double-layer aluminum analog wiring. By sandwiching a single layer of aluminum supplied with an analog ground potential, it is possible to suppress noise from entering the analog wiring from the digital wiring due to crossing.

Figure 5(C) shows the digital wiring DW in the analog wiring area.
This is an example of an I-shield. For digital wiring that had to pass through the analog wiring area because there was no detour route,
A part of the single-layer aluminum analog wiring was changed to double-layer aluminum, and a part of the double-layer aluminum digital wiring was changed to polysilicon, and the intersection was made of single-layer aluminum with analog ground potential for shielding. Shield. This makes it possible to suppress noise from entering the analog wiring from the digital wiring due to crossing.

In FIG. 5, the same or equivalent parts as in FIGS. 3 and 4 are given the same reference numerals, SPS is polysilicon for shielding, SAJ 1 is single layer aluminum for shielding,
Tl is a digital terminal, and T2 is an address terminal.

In the wiring shield shown in FIGS. 5(a) to (C1), the analog ground potential is supplied to the shielding polysilicon and the single layer aluminum from the shielding analog ground wiring AGS IAGS2 inside the analog standard cell.

〔Effect of the invention〕

From what has been explained above, the present invention has the following advantages.

(1) In analog function cells, low-sensitivity analog terminals are drawn out to both the top and bottom sides of the cell, so the high-sensitivity analog wiring area and the low-sensitivity analog wiring area are separated depending on whether or not the cell row includes digital terminals. It is possible to select either to configure the analog wiring area and the digital wiring area separately, or to configure the analog wiring area and the digital wiring area separately, or to configure a mixture of both areas. Therefore, the analog wiring from the low-sensitivity analog terminal and the high-sensitivity analog terminal and the digital wiring from the digital terminal almost never cross, and crosstalk between the digital signal and the analog signal is less likely to occur.

(2) In digital function cells, the digital terminals are drawn out to both the top and bottom sides of the cell, so the digital wiring between digital function cells and the digital wiring between analog function cells and digital function cells that are directly connected to analog elements are , the wiring can be divided into a digital-to-digital functional cell wiring area and an analog-to-digital functional cell wiring area, respectively.

Therefore, the number of wires in each wiring region is reduced, the number of intersections, and the wire length are reduced, and the characteristics of noise, crosstalk, and delay of the digital wiring signal between the digital functional cell and the analog functional cell are improved.

(3) The low-sensitivity analog terminals of analog function cells and the digital terminals of digital function cells are drawn out to both the top and bottom sides of the cell, so no wiring detours occur even if the wiring connection direction is up or down. , the number of wiring intersections and the wiring length can be reduced. Furthermore, by utilizing the fact that the upper and lower equivalent terminals of the cell are connected within the cell, this can also be used as an upper and lower passing line for the cell column. Therefore, there is no need to leave spaces between cells for passing wiring (and a layout can be designed with a small area and short wiring length).

(4) In addition to the two power supply wirings, the standard cell has built-in analog ground wiring, reference voltage wiring, and analog ground wiring for shielding, and the width of these wiring is wider than the width of the intercell wiring to achieve low resistance. It is easy to achieve this goal. Also, when connecting cell terminals to analog ground, reference voltage, and shield analog ground wiring,
All you have to do is connect these wires at the intersections of the cell terminals, so
Wiring can be shortened.

(5) If a separation area is formed below the analog ground wiring for shielding the analog function standard cell, noise in the low sensitivity analog wiring area, digital wiring area, and the open '1IAjl area between analog and digital function cells can be reduced from the analog function cell. Contamination within the system is suppressed. Further, if a similar isolation region is formed below the analog ground wiring for shielding the digital function standard cell, it is possible to suppress noise from the digital function cell from entering the analog wiring area.

(6) By inserting separation cells between blocks, different power supplies and grounds can be used in blocks where cell rows are adjacent on the left and right.

(7) Even if both an analog function circuit block and a digital function circuit block exist adjacent to each other in the same cell stage, by inserting a separate cell between these blocks,
This prevents noise from digital function circuit blocks from entering analog function circuit blocks. Also, when digital wiring passes next to an analog functional cell row,
Even when analog wiring passes beside a digital functional cell row, inserting a separation cell at the end of the cell row prevents noise from the digital functional cells and digital wiring from mixing with the analog wiring and analog functional cells. It is prevented. Furthermore, by connecting two separated cells facing each other in the upper and lower stages with a separation region, it is possible to realize an intercell arrangement 'a' region in which the analog wiring region and the digital wiring region are separated left and right.

(8) The cell rows in a circuit block can be arranged in two stages instead of just one, so even if the cell width increases or the number of cells increases, the wiring length between cells in the circuit block can be kept small. It can be suppressed. Furthermore, even if multiple types of power supplies and grounds are used within the circuit block, the power supply wiring can be easily taken out.

(9) Even if analog wiring and digital wiring intersect,
Since a shield layer can be provided between both wiring layers, it is possible to suppress digital noise mixed into analog wiring. Furthermore, since there is no need to detour the digital wiring, the wiring length can be shortened.

Since there are no restrictions on the order of wiring in the Ql inter-cell wiring area, automation through program processing is easy.

Since shielding between the αD analog element and the digital wiring can be achieved using analog ground wiring dedicated to shielding, digital noise does not mix into the reference voltage line and analog ground wiring, and these voltages are stable.

From the above, the performance of analog circuits such as distortion rate, S/N, signal band, and signal dynamic range can be significantly improved, and if the present invention is used, a high-performance analog-digital mixed LSI with a standard cell design can be realized. It can be easily achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a standard cell according to the first invention of the present invention, FIG. 2 is a block diagram showing an embodiment of the arrangement and wiring of a standard cell according to the second invention of the present invention, and FIG. The figure is an explanatory diagram showing another example of standard cell arrangement and wiring, Figure 4 is a connection diagram showing an example of connection between cell terminals and power supply/ground, Figure 5 is a connection diagram showing an example of wiring shield, FIG. 6 is a configuration diagram showing a conventional standard cell, FIG. 7 is a configuration diagram showing the arrangement and wiring of a conventional standard cell, and FIG. 8 is a connection diagram showing wiring between conventional standard cells. AVSS, AVDD-7sl:l gummy source, AGND...
・Analog ground, VREF...Reference voltage source, AG
SI, AGS...analog ground for shield, DV
SS, DVDD...digital power supply, A...analog functional cell, AT...analog functional cell string, P...cell origin, D...digital functional cell, DT...digital functional cell string , SS... Separate cell, S11.515
S16...Low sensitivity analog wiring area, S12...Digital wiring area, S13...High sensitivity analog wiring area, S14. S18...Analog wiring area, S17...
・Digital wiring area, S19. S20...Analog-
Digital functional cell interconnection area, 321. S22...Digital-digital functional cell wiring area.

Claims (2)

[Claims] (1) An analog/digital mixed LSI in which analog circuits and digital circuits coexist is equipped with an analog function cell, a digital function cell, and a separate cell, and the analog function cell has an analog ground wiring area for shielding, an analog ground wiring area for shielding, and a reference voltage. The wiring area, analog power supply wiring area, high-sensitivity analog terminals provided on either the top or bottom, digital terminals provided on either the top or bottom, and low-sensitivity analog terminals provided on both the top and bottom, and the digital function cell is shielded. The separate cell has an analog ground wiring area for shielding, a preliminary wiring area, a digital power wiring area, and digital terminals provided on both the upper and lower sides. An analog/digital mixed LSI characterized by having a region. (2) In an analog/digital mixed LSI where analog circuits and digital circuits coexist, the function of either or both of an analog functional cell column consisting of a plurality of analog functional cells and a digital functional cell column consisting of a plurality of digital functional cells. It has multiple cell stages composed of cell rows, and the analog function cells are analog ground wiring area for shielding, analog ground wiring area, reference voltage wiring area, analog power wiring area, and high-sensitivity analog terminals provided on either the upper or lower side. It has a digital terminal provided on either the top or bottom and a low-sensitivity analog terminal provided on both the top and bottom, and the digital function cell has an analog ground wiring area for shielding, a spare wiring area, a digital power wiring area, and a digital terminal provided on both the top and bottom. The separated cell has an analog ground wiring area for shielding, an analog ground wiring area, a reference voltage wiring area, and an analog power wiring area, and has a high sensitivity analog terminal for connecting the high sensitivity analog terminals of the analog function cells. A wiring area, a low-sensitivity analog wiring area that connects low-sensitivity analog terminals of analog function cells, an analog wiring area where the high-sensitivity analog wiring area and low-sensitivity analog wiring area coexist, and digital terminals of analog function cells and digital function cells. A wiring area between analog and digital cells that connects the digital terminals of digital function cells, a wiring area between digital and digital cells that connects the digital terminals of digital function cells, and a wiring area between the analog and digital cells and a wiring area between digital and digital cells. The interconnection area between the cell stages is configured by one or more of the digital interconnection areas, and the separated cells are configured with any one of the digital interconnection area, the analog-to-digital cell interconnection area, and the digital-to-digital cell interconnection area. the high-sensitivity analog wiring area, which is arranged adjacent to the cell rows above and below the boundary with the address wiring area;
The low-sensitivity analog wiring area and the analog wiring area constitute a wiring area between analog functional cell columns, and the analog-to-digital cell wiring area constitutes a wiring area between an analog functional cell column and a digital functional cell column. , wherein the digital-to-digital cell wiring area constitutes a wiring area between digital functional cell arrays, and the digital wiring area constitutes a wiring area that connects only digital terminals of analog functional cell arrays.・Digital mixed L
S.I.