JPH02161730A - Trench isolation method in semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the generation of crystal deffect by a method wherein a first high concentration diffusion layer of a second conductivity type or the like is formed on one main surface of a semiconductor substrate of a first conductivity type, a trench isolation groove reaching the substrate while including a part of a second high concentration diffusion layer is dug, and a film having insulating property is buried in the groove. CONSTITUTION:By an ion implantation method and the like, N-type impurity is introduced into one main surface of a P-type semiconductor substrate 1, and a first N-type high concentration diffusion layer 2 is formed; thereon, an N-type semiconductor layer 3 of low impurity concentration is deposited; at a specified position on the layer 3, an ion implantation region 62 of P or the like is selectively formed; by performing heat treatment at a comparatively high temperature, a second N-type high concentration diffusion layer 6 is formed at a specified part of the layer 3. As far as a depth reaching the substrate 1 containing a part of the layer 6 from the layer 3 side, a trench isolation groove 4 is dug by etching. After a mask material 4 is eliminated, the inside of the groove 4 is filled with an insulating film 5 by CVD method or the like. Thereby, the generation of crystal defect or the like and the increase of leak current can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a trench isolation method in a semiconductor integrated circuit device.
The present invention relates to an improvement of a trench isolation method in a bipolar semiconductor integrated circuit device having a bipolar type semiconductor integrated circuit device.

[Prior Art] A numerical overview of the trench isolation structure in this type of bipolar semiconductor integrated circuit device is shown in FIG.

That is, in the device configuration shown in FIG.
is a semiconductor substrate of a first conductivity type, 2 is a first high concentration diffusion layer of a second conductivity type, 3 is a semiconductor layer of a second conductivity type,
These are sequentially stacked on the first conductivity type semiconductor substrate l. Further, 4 is a trench isolation groove dug from a predetermined position of the semiconductor layer 3 to a part of the semiconductor substrate 1, 5 is an insulating film that fills the trench isolation groove 4, and 6 is the semiconductor layer 3. This is a second high concentration diffusion layer of a second conductivity type formed in contact with the trench isolation groove 4 within the trench isolation groove 4 .

In addition, in the trench isolation structure shown in Fig. 2, the diffusion layers such as the base and emitter that are required to form a bipolar transistor are not made of wood, so they are difficult to use. is omitted.

Next, the outline of the trench isolation method in this type of semiconductor integrated circuit device, which has been conventionally implemented, will be explained in Section 3.
It is shown in the figure.

That is, FIGS. 3(a) to 3(g) are cross-sectional views each schematically showing the main steps of the conventional trench isolation method. This is an example commonly used when forming an npn type bipolar transistor on a substrate.

First, on one main surface of the p9 semiconductor substrate 1, an ion corporation method is applied. Alternatively, the first n-type high concentration diffusion layer 2 is formed by introducing Lilo type impurities by a diffusion method or the like (FIG. 3(a)). This first mouth-type high-concentration diffusion layer 2 is formed, for example, to lower the collector resistance of a bipolar type transistor. It may be formed on the entire surface of one main surface of the p-type semiconductor substrate 1, but for peace of mind, in 17, a process such as photo-making 1: retardation method is applied to selectively form a part of the −■=7 surface. Even if formed, there is no difference 17 support.

Is this the first 11-type high concentration diffusion layer in 11η? 11ζA1) Then, a q-hair conductor layer 3 having a relatively low impurity concentration is deposited on this mouth-shaped high-concentration diffusion layer 2 by epitaxial growth or the like (FIG. 2(b)).

Next, a mask material 41 such as photoresist or silicon oxide film is butter-formed at a predetermined position on the n-type semiconductor layer 3, and this mask material 41 is used as an etching mask to form trench isolation grooves by etching. 4 (Figure (C)). The digging depth of the trench isolation groove 4 in the case of 1: is at least 1'' for the device isolation of the bipolar transistor.
Continue until the f-conductor substrate l is reached.

Subsequently, after removing the mask material 41, the inside of the trench isolation groove 4 is filled with an insulated #j film 5 by, for example, a low-pressure CVD method or the like ((d) in the same figure). However, in this case, if the mask material 41 is an insulating film such as a silicon oxide film, it is possible to embed it without removing the stiffness. The insulating film 5 may be a composite film with other film materials as long as the portion in contact with the inner surface of the trench isolation trench 4 is insulated.

Furthermore, the entire surface treated as described above is planarized by, for example, an etch-back method, and the surface of the n-type semiconductor layer 3 including the portion of the insulating film 5 filling the trench isolation groove 4 is flattened. ((C) in the same figure).

Then, a resist pattern 61 is formed at a predetermined position using photolithography or the like, and using this resist pattern 61 as a mask, an n-type impurity such as phosphorus is ion-implanted into the ion-implanted region. Form 6z-t! ((f) in the figure), and then heat treatment is performed at a relatively high temperature to diffuse this ion-implanted region 62 into the mouth-type semiconductor layer 3 and form the second n-type high concentration diffusion layer 6.
((g) in the same figure).

That is, the desired trench isolation can be achieved in one or more ways, and then a bipolar transistor can be formed by known means.

[Problem to be solved by the invention]

However, in the conventional trench isolation method performed as described above, in this case, after filling the inside of the trench isolation groove 4 with the insulating film 5, the second n-type high concentration diffusion layer 6 is formed by diffusion. , so this second
Due to the heat treatment at a relatively high temperature when forming the n-type high concentration diffusion layer 6 of These differences often generate stress inside the device, and may cause crystal defects, for example, in the area indicated by reference numeral 7 in FIG. Increase the current and equipment characteristics,
In addition, this was a major problem for reliability engineers.

This invention was made to solve these conventional problems, and its purpose is to prevent the occurrence of crystal defects within the device structure and reduce junction leakage current. I made it possible. An object of the present invention is to provide a trench isolation method in this type of semiconductor integrated circuit device.

[Means to solve the problem]

In order to achieve the above object, a method for trench isolation in a semiconductor integrated circuit device according to the present invention includes a trench isolation method for a semiconductor integrated circuit device according to the present invention. A second high concentration diffusion layer of two conductivity type is formed by diffusion, so that heat treatment at a relatively high temperature is not required after filling the trench isolation groove with an insulating film.

That is, the present invention includes a step of sequentially forming a first high concentration diffusion layer of a second conductivity type and a semiconductor layer of a second conductivity type on at least a portion of the lifetime surface of a semiconductor substrate of a first conductivity type;
forming a second highly doped diffusion layer of a second conductivity type at a predetermined position on the semiconductor layer; A trench isolation method in a semiconductor integrated circuit device is characterized in that the method includes the steps of digging a trench isolation groove reaching the semiconductor substrate and filling the trench isolation groove with an insulating film.

[For production]

Therefore, in the method of the present invention, after forming the second high concentration diffusion layer of the second conductivity type into the semiconductor layer of the second conductivity type, digging a trench isolation groove and forming the trench isolation groove. Because embedding is performed using an insulating film inside the semiconductor substrate, the difference in thermal expansion coefficient between the semiconductor substrate and this insulating film during heat treatment as in the conventional method There is no risk of stress-based stress occurring, and the occurrence of crystal defects is suppressed.

(Embodiment) Hereinafter, an embodiment of the trench isolation method in a semiconductor integrated circuit device according to the present invention will be described in detail with reference to FIG.

1(a) to 1(f) are cross-sectional views each schematically showing the main steps of the trench isolation method to which this embodiment is applied. In the method of the embodiment of FIG. The same reference numerals as in the conventional method in the figure indicate the same or corresponding parts.

In this case as well, the trench isolation method according to this embodiment is applied to, for example, a case where an npnl bipolar transistor is formed on a silicon semiconductor substrate.

In this embodiment method as well, the operations up to the steps shown in FIGS. 3(a) and 3(b) in the conventional method are performed in exactly the same manner. That is, first, an n-type impurity is introduced into the entire surface of the p-type semiconductor substrate l or a selected required surface portion by ion implantation or diffusion to form a first n-type height. forming a concentration diffusion layer 2;
In addition, an n-type layer with a lower impurity concentration is added to this first n-type high concentration diffusion layer 2-t by epitaxial growth or the like.
A type semiconductor layer 3 is deposited.

After that, a resist pattern 61 is formed at a predetermined position on the n-type semiconductor layer 3 by photolithography, and using this resist pattern 61 as a mask, for example, an n-type impurity such as phosphorus is ionized. By implanting ions to selectively form an ion implantation region 62 (FIG. 1(a)) and heat-treating it at a relatively high temperature, a second ion implantation region 62 is formed in a selected predetermined portion of the n-type semiconductor layer 3. An n-type high concentration diffusion layer 6 is formed by diffusion (FIG. 2(b)).

Next, a mask material 41 such as photoresist or silicon oxide film is similarly patterned at a predetermined position on the n-type semiconductor layer 3 including the second n-type high concentration diffusion layer 6. Figure (C)), then this mask material 41
is used as an etching mask, the trench isolation groove 4 is etched from the n-type semiconductor layer 3 side to a depth that includes at least a part of the second n-type high concentration diffusion layer 6 and reaches the p-type semiconductor substrate l. ((d) in the same figure).

Next, the mask material 41 is removed, or if the material is an insulating film such as a silicon oxide film, the trench isolation is performed without removing the mask material 41, for example, by low pressure CVD. Provided that the inside of the groove 4 is filled with an insulating film 5 or that the portion in contact with the inner surface of the groove is insulated, other film members 1 such as a composite film with a polycrystalline silicon layer, etc., are used to provide insulation. 'f' that is buried in the material to form trench isolation ((C) in the same figure)
Then, if necessary, the entire surface is flattened by, for example, an etch-back method, and the 0
This exposes the surface of the type semiconductor layer 3 (FIG. 3(f)).
), the purpose of this surface flattening is to help form a junction or facilitate patterning in the process of forming a bipolar transistor in the trench isolation trench 4.

In other words, in this embodiment method, the expected 1.! After that, a bipolar transistor or the like is formed by known means.

Therefore, in the case of the method of this embodiment, the trench isolation trench 4 is dug after the second n-type high concentration diffusion layer 6 is formed by diffusion into the n-type semiconductor layer 3.

In addition, since the trench isolation groove 4 is filled with the insulating film 5, heat treatment during diffusion formation of the second mouth-type high-concentration diffusion layer 6 is difficult, as in the conventional method. , the p-type semiconductor substrate 1 and the trench isolation groove 4
The difference in thermal expansion coefficient between C and the insulating film 5 in which it is buried effectively suppresses the occurrence of stress and, in turn, the occurrence of crystal defects.

〔Effect of the invention〕

As described in detail above, according to the method of the present invention, in a semiconductor substrate of a first conductivity type, a first high concentration diffusion layer of a second conductivity type and a first high concentration diffusion layer of a second conductivity type are formed on at least a part of the main surface thereof. With the semiconductor layers of the second conductivity type sequentially formed, a second high concentration diffusion layer of the second conductivity type is formed at a predetermined position of the semiconductor layer, and a second high concentration diffusion layer of the second conductivity type is formed at a predetermined position of the semiconductor layer. 1. When a trench isolation groove reaching the V-conductor substrate is dug from one device and buried with an insulating film 7. A second high concentration diffusion layer of a second conductivity type in a semiconductor layer of a second conductivity type. Diffusion formation of.

In other words, after performing diffusion formation by heat treatment at a relatively high temperature, a trench isolation trench is dug that includes at least a part of this second high concentration diffusion layer and reaches the semiconductor substrate, and this trench isolation is performed. Since the trench is filled with an insulating film, some damage occurs during heat treatment.

It is possible to prevent the occurrence of stress due to the difference in thermal expansion coefficient between the semiconductor substrate and this insulating film, and thereby effectively and favorably suppress the occurrence of crystal defects inside the device. As a result, it becomes possible to perform trench isolation with less junction leakage in the element configuration, and it is possible to significantly improve device characteristics and reliability.
The manufacturing method itself also has the advantage of being extremely simple and easy to implement when compared to conventional methods.

[Brief explanation of the drawing]

Figures 1(a) to [) are cross-sectional views schematically showing the main steps of the trench isolation method used in this embodiment, and Figure 2 shows a general trench isolation structure. Schematic cross-sectional view, Figure 3 (a) to g)
2A and 2B are cross-sectional views sequentially schematically showing the main steps of the conventional trench dividing method. ■...p-type semiconductor substrate, 2...first n-type high concentration diffusion layer, 3...n-type semiconductor layer, 4...trench isolation groove, 41...butter coated mask material,
5... Insulating film (film having insulating properties), 6... Second n-type high concentration diffusion layer, 61... Resist pattern, 62... Ion corporate region. Agent Masuo Oiwa Figure 1 (I =
9/) p1 half-rumored sister treatment off n-type conductor layer resist I turn ion Tsujiiri 翿珀6: ri 2 ng Kanfeng cliff fA dispersion Figure 1 (zo 3) 5: #! Le Structure (Loquan Master 1 Chou 3 Lament) Figure 1 ('+, 7 Z)! Magooning Dan Water Mask Material Trench Threat Spout Group Book Figure 2 Figure 3 (f01) Figure 3 of Kure (3 of A)

Claims (1)

[Claims] a step of sequentially forming a first high concentration diffusion layer of a second conductivity type and a semiconductor layer of a second conductivity type on at least a portion of one main surface of a semiconductor substrate of a first conductivity type; forming a second highly doped diffusion layer of a second conductivity type at a predetermined position;
A semiconductor device characterized by comprising the steps of: digging a trench isolation groove that reaches the semiconductor substrate, including a part of the high concentration diffusion layer; and burying the inside of the trench isolation groove with an insulating film. Trench isolation methods in integrated circuit devices.