JPH02159097A - Multilayer printed wiring board and manufacture thereof - Google Patents
Multilayer printed wiring board and manufacture thereofInfo
- Publication number
- JPH02159097A JPH02159097A JP63314353A JP31435388A JPH02159097A JP H02159097 A JPH02159097 A JP H02159097A JP 63314353 A JP63314353 A JP 63314353A JP 31435388 A JP31435388 A JP 31435388A JP H02159097 A JPH02159097 A JP H02159097A
- Authority
- JP
- Japan
- Prior art keywords
- inner layer
- board
- chip
- printed wiring
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000011889 copper foil Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 239000004020 conductor Substances 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 239000010949 copper Substances 0.000 abstract description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- 229920000647 polyepoxide Polymers 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 2
- 239000011800 void material Substances 0.000 abstract description 2
- 238000007731 hot pressing Methods 0.000 abstract 1
- 238000012858 packaging process Methods 0.000 abstract 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- UFIKNOKSPUOOCL-UHFFFAOYSA-N antimony;cobalt Chemical compound [Sb]#[Co] UFIKNOKSPUOOCL-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- -1 etc. Chemical compound 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はプルアップあるいはプルダウン、電流制限等を
目的とした抵抗が内蔵された多層印刷配線板とその製法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a multilayer printed wiring board with built-in resistors for pull-up or pull-down, current limiting, etc., and a method for manufacturing the same.
従来、多層印刷配線板にプルアンプ、プルダウンを目的
とした抵抗の付設に際しては、回路形成した内ｊｓ板と
銅張積層板もしくは銅箔とがプリプレグを介して積層さ
れ、多層回路及びスルホール等が設けられた該多層印刷
配線板上に抵抗部品が実装されるのが一般的である。ま
九、該内層板の内層回路の間欠部に該抵抗を付設するこ
とも提案されている。Conventionally, when attaching resistors for the purpose of pull amplifiers and pull-downs to multilayer printed wiring boards, an inner JS board with a circuit formed thereon and a copper-clad laminate or copper foil were laminated via prepreg, and multilayer circuits and through holes were formed. Generally, resistive components are mounted on the multilayer printed wiring board. Furthermore, it has also been proposed to attach the resistor to the intermittent portions of the inner layer circuit of the inner layer plate.
上記のような多層印刷配線板においては、抵抗がＩＣ、
コンデンサー等の電子部品と同様に、該多層印刷配線板
上に設けられた外層回路に実装されるために、該外層回
路の省スペース化に伴う該多層印刷配線板の小型化、実
装工程の省力化の阻害となってい友。また、該内層回路
の間欠部に抵抗を付設する方法は、該多層印刷配線板の
小型化、実装工程の省力化の面では期待できるが、この
方法では、内層回路を形成する際に、それぞれの回路設
計にあわせて所要の抵抗をあらかじめ付設する必要があ
υ、マスプロダンシランが困離な昨今にあっては該多層
印刷配線板の製造工程が複雑になる恐れがある。In the multilayer printed wiring board as described above, the resistors are IC,
Like electronic components such as capacitors, it is mounted on the outer layer circuit provided on the multilayer printed wiring board, so the outer layer circuit saves space, which reduces the size of the multilayer printed wiring board and saves labor in the mounting process. A friend who is a hindrance to becoming a friend. Furthermore, the method of attaching resistors to intermittent parts of the inner layer circuit is expected to reduce the size of the multilayer printed wiring board and save labor in the mounting process, but in this method, when forming the inner layer circuit, each It is necessary to provide the necessary resistors in advance according to the circuit design of the multilayer printed wiring board, and in these days when massprodansilane is in short supply, the manufacturing process of the multilayer printed wiring board may become complicated.
本発明は上記のような従来技術の有する問題点に鑑み発
明されたもので、小型化、実装工程の省力化のみならず
、製造工程の合理化に貢献できる多層印刷配線板とその
製法を提供することを目的としている。The present invention was invented in view of the problems of the prior art as described above, and provides a multilayer printed wiring board and its manufacturing method that can contribute not only to miniaturization and labor saving in the mounting process, but also to rationalization of the manufacturing process. The purpose is to
上記の目的を達成するために、本発明は下記の如〈実施
される。以下実施例に従い詳細に説明する０
第１図はガラスエポキシ樹脂系の絶縁性の基板（４）上
にカーボン−レジン系の抵抗（２）と銅等の導体（３）
全一定のパターンで付設したチップ（５）の平面図で、
該チップ（５）は、第２図の平面図で示されているガラ
スエポキシ樹脂系の絶縁性の基板（４）上に内層回路（
８）を設けた内層板（りの空隙部（７）にはめ込まれる
。次に第３図の積層配置図に示されるように該チップ（
りをはめ込んだ該内層板（９の表裏にガラスエポキシ樹
脂系のプリプレグ（９）及び銅張積層板α＊′５ｒ：積
層し、熱圧成型して多層板とする。更に外層回路αυな
らびにスルーホール（６）等を設は本発明の多層印刷配
線板（υを製造する。In order to achieve the above object, the present invention is implemented as follows. A detailed explanation will be given below according to an example.0 Figure 1 shows a carbon-resin based resistor (2) and a conductor such as copper (3) on a glass epoxy resin based insulating substrate (4).
A plan view of chips (5) attached in a uniform pattern,
The chip (5) has an inner layer circuit (
The chip (8) is inserted into the cavity (7) of the inner layer plate (7) provided with the chip (8).Then, as shown in the stacking layout diagram of FIG.
Glass epoxy resin prepreg (9) and copper-clad laminate α*'5r are laminated on the front and back sides of the inner layer board (9) in which the inner layer is fitted with a circuit board (9), and the copper-clad laminate α*'5r is laminated and hot-press molded to form a multilayer board. Holes (6) etc. are provided to manufacture the multilayer printed wiring board (υ) of the present invention.
該チップ（ω上の該抵抗（２）は、該内層板（９にはめ
込む前に、回路設計に合わせて所要の抵抗以外の配線を
マイクロブラスト、ドリル、レーザー、超音波法等の切
断手段によって切断しておく。Before fitting the resistor (2) on the chip (ω) into the inner layer plate (9), wires other than the required resistors are cut by cutting means such as microblast, drill, laser, or ultrasonic method according to the circuit design. Cut it off.
本発明の抵抗には目的Ｖこ適合する抵抗値を示すもので
あれば、特に制約はないが、付設するに際し塗工性があ
り、導体と密着性のある材質であれば問題はない。例え
ば、カーボン粉末、金属粉末等の導電性材料を＠層性の
良いエポキシ、ウレタン、シリコン等の硬化性樹脂中に
、目的とする抵抗値を持つレベルに分散したレジンペー
ストを塗布、硬化させて抵抗体とすることができる。こ
のほか半田抵抗体又は熱可塑性樹脂ならびにその配合組
成物に前記のような導電性粉末を分散させたものを加熱
塗布して抵抗体を形成する方法、コバルトトアンチモン
、ゲルマニウム、モリブデン、タングステン等、クロム
とアンチモン、マンガン、セレン、テルル等、ニッケル
とアンチモン、ゲルマニウム、インジュウム、モリブデ
ン、パナジェウム等の合金からなるメツキ膜を形成する
方法、もしくは有形の抵抗体を導電性接着剤により接着
する方法等を採用してもよい。チップへの抵抗の付設形
状は何ら制約はな〈実施例の形状のほか適宜選定されれ
ばよい。There are no particular restrictions on the resistor of the present invention as long as it exhibits a resistance value that meets the purpose V, but there is no problem as long as it is made of a material that is coatable and adhesive to the conductor when attached. For example, a resin paste containing a conductive material such as carbon powder or metal powder dispersed in a hardening resin such as epoxy, urethane, or silicone with good layer properties to a level that has the desired resistance value is applied and cured. It can be a resistor. In addition, a method of forming a resistor by heating and applying a solder resistor or a thermoplastic resin or a blended composition thereof with conductive powder as described above dispersed therein, cobalt antimony, germanium, molybdenum, tungsten, etc. A method of forming a plating film made of an alloy of chromium and antimony, manganese, selenium, tellurium, etc., nickel and antimony, germanium, indium, molybdenum, panageum, etc., or a method of bonding a tangible resistor with a conductive adhesive, etc. May be adopted. There are no restrictions on the shape of the resistor attached to the chip; it may be appropriately selected in addition to the shape of the embodiment.
抵抗の抵抗値は回路設計に従い調整される。すなわち、
素材の組成のほか、抵抗の長さ、幅、厚み等によシ１０
Ω〜３００にΩ程度に調整される。The resistance value of the resistor is adjusted according to the circuit design. That is,
In addition to the composition of the material, it also depends on the length, width, thickness, etc. of the resistor10.
It is adjusted to about Ω to 300Ω.
更に、導体との接触性、接合性を確保するために導体表
面の酸化皮膜の除去、洗浄ならびにプライマー塗布等が
適時なされる。Further, in order to ensure contactability and bondability with the conductor, removal of the oxide film on the surface of the conductor, cleaning, and application of a primer are performed at appropriate times.
抵抗を付設したチップがはめ込まれる内層板は、回路設
計に従い、内層回路を設ける前に、該チップのサイズに
合わせて、ドリル、レーザー、超音波法プラスト等の切
断手段によって空隙部を設けておく。In the inner layer plate into which the chip with the resistor is fitted, according to the circuit design, a gap is created by cutting means such as a drill, laser, or ultrasonic plast according to the size of the chip before installing the inner layer circuit. .
このようにして本発明に係る抵抗を付設した小チップと
内層板は調製されるが、多層板に成型するに際し、抵抗
部にレジスト膜を付着するかあるいは付着しない状態で
プリプレグを介して銅張積層板あるいは銅箔等の外層材
を積層し、熱圧成把して多層板とする。更に外層回路及
びスルーホール等を設けて本発明の多層印刷配線板を得
る。In this way, a small chip and an inner layer board equipped with a resistor according to the present invention are prepared, but when molding into a multilayer board, either a resist film is attached to the resistor part or a resist film is not attached and a copper cladding is applied via a prepreg. Laminated boards or outer layer materials such as copper foil are laminated and compacted under heat to form a multi-layered board. Furthermore, outer layer circuits, through holes, etc. are provided to obtain the multilayer printed wiring board of the present invention.
本発明の多層印刷配線板は、抵抗の一部あるいは全部が
内層されている丸め、従来、外層回路上に実装されてい
た抵抗がなくな）、実装用のスペースが省略できる。従
って小型化がよ如−層容易になるほか、他の電子部品の
実装が容易になし、誤配線、取付はミスが避けられる。In the multilayer printed wiring board of the present invention, some or all of the resistors are internally layered (there is no resistor conventionally mounted on the outer layer circuit), and the mounting space can be omitted. Therefore, not only miniaturization becomes much easier, but also other electronic components can be easily mounted, and incorrect wiring and mounting errors can be avoided.
更に多層の内部に抵抗が位置しているため、湿度による
抵抗変化がなく、安定した抵抗が得られる。Furthermore, since the resistance is located inside the multilayer, there is no change in resistance due to humidity, and stable resistance can be obtained.
抵抗を付設したチップは、汎用のＤＩＰＳＳＩＰ。The chip with the resistor is a general-purpose DIPSSIP.
フラットパッケージ等に合せて製造されているので、部
品の共通化が可能となシ、従来の回路設計に従って抵抗
を付設する方法と異な夛、リードタイムが縮少され製造
工程が合理化できる。加えて、抵抗はチップを検査する
のみで足り、多層印刷配線板の歩留向上が期待できる。Since it is manufactured to suit flat packages, etc., it is possible to use common parts, which is different from the method of attaching resistors according to conventional circuit design, and the lead time can be shortened and the manufacturing process can be streamlined. In addition, the resistor only needs to be used to test the chip, which can be expected to improve the yield of multilayer printed wiring boards.
第１図は、抵抗と導体が付設された標準的な実施例のチ
ップ（ト）の平面図、第２図は、該チップがはめ込まれ
る内層板■の平面図、第３図は該チップ（ト）と内層板
（！りにプリプレグ及び銅張積層板の積層された配置図
、第４図は本発明の多層印刷配線板■の要部断面図であ
る。
１・・・多層印刷配線板 ２・・・抵抗３・・・導体
４，４′・・・基板４・・・抵抗と導体
が付設されたチップ庁・・・内層板 ７・・
・空隙部８・・・内層回路 ９・・・プリプレ
グ１０・・・銅張積層板 １１・・・外層回路１
２・−・スルーホール
特許出願人 アイカニ業株式会社
第１図
第２図
第ａ図FIG. 1 is a plan view of a standard embodiment chip (G) equipped with a resistor and conductor, FIG. Fig. 4 is a cross-sectional view of the essential parts of the multilayer printed wiring board (1) of the present invention. 1... Multilayer printed wiring board 2...Resistor 3...Conductor 4, 4'...Substrate 4...Chip board with resistor and conductor attached...Inner layer board 7...
・Void portion 8... Inner layer circuit 9... Prepreg 10... Copper clad laminate 11... Outer layer circuit 1
2.--Through hole patent applicant Aikanigyo Co., Ltd. Figure 1 Figure 2 Figure a
Claims (2)
ップが、絶縁性の基板上に内層回路が設けられた内層板
内の空隙部にはめ込まれていることを特徴とする多層印
刷配線板。1. A multilayer printed wiring board characterized in that a chip having a flat resistor attached to an insulating substrate is fitted into a cavity in an inner layer board having an inner layer circuit provided on the insulating substrate. .
状の抵抗を絶縁性基板のチップ上に付設し、回路設計に
合せて所要抵抗以外の配線を切断した該チップを、絶縁
性の基板上に内層回路を設けた内層板内の空隙部にはめ
込んだ後に、表裏にプリプレグを介して銅張積層板ある
いは銅箔等の外装材を積層し、外層回路及びスルーホー
ル等を設けることを特徴とする多層印刷配線板の製法。2. A flat resistor is attached in advance to a chip on an insulating substrate in a pattern that matches the existing device, and the inner layer circuit is placed on the insulating substrate after cutting the wiring other than the required resistance according to the circuit design. A multilayer printed wiring, which is fitted into a gap in a prepared inner layer board, and then laminated with an exterior material such as a copper-clad laminate or copper foil on the front and back sides via a prepreg, and is provided with an outer layer circuit, through holes, etc. The manufacturing method of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314353A JPH02159097A (en) | 1988-12-13 | 1988-12-13 | Multilayer printed wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314353A JPH02159097A (en) | 1988-12-13 | 1988-12-13 | Multilayer printed wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02159097A true JPH02159097A (en) | 1990-06-19 |
Family
ID=18052308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63314353A Pending JPH02159097A (en) | 1988-12-13 | 1988-12-13 | Multilayer printed wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02159097A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135767A (en) * | 2007-12-27 | 2008-06-12 | Dainippon Printing Co Ltd | Manufacturing method of printed wiring board, and printed wiring board |
-
1988
- 1988-12-13 JP JP63314353A patent/JPH02159097A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135767A (en) * | 2007-12-27 | 2008-06-12 | Dainippon Printing Co Ltd | Manufacturing method of printed wiring board, and printed wiring board |
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