JPH02156546A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent disconnection and short-circuit in a wiring metallic film and to decrease parasitic capacity by bonding electrodes to metallic bumps with projections and recesses on the wiring metallic film opposed to corresponding recesses and projections on a semiconductor substrate. CONSTITUTION:A wiring board 7 is provided with projections and recesses complementary with projection and recesses of a semiconductor substrate 1. Then, a wiring metallic film 5 is formed on the wiring board 7. Metallic bumps 11 are provided at positions corresponding to an electrode 61 on the semiconductor substrate 1 and to an electrode 4 on an epitaxial layer formed in an island shape on the semiconductor substrate 1. The projections and recesses of the wiring board 7 are opposed to the recesses and projections on the semiconductor substrate complementary therewith so that electrodes are bonded to the metallic bumps 11. Since the electrodes 4, 61 on the semiconductor substrate 1 are bonded to the metallic wiring film 5 through the metallic bumps 11, they can be bonded with increased power and still with a certain distance therebetween. Accordingly, parasitic capacity between the semiconductor substrate and the metallic wiring film can be decreased substantially.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device used in a central processing unit of a computer, an optical communication device, a communication relay device, and the like.

[Conventional technology]

FIG. 3 is a cross-sectional structural diagram of a semiconductor device having a conventional MO3 type transistor control circuit. In FIG. 3, 1 is a p-type Si substrate which is a semiconductor substrate, and a GaAs buffer layer 21 is formed on one end side of the Si substrate 1. n-type GaAs layer 22
and a p-type GaAs layer 23 are stacked in this order to form the light emitting diode 2. Furthermore, an insulating layer 3 of SiO□ having a gap of an appropriate width is laminated on the p-type GaAs layer 23 so as to cover these layers, and a light emitting diode electrode 4 is formed between the gaps.

On the other hand, on the other end side of the p-type Si substrate 1, a MOS transistor is formed as follows. That is, a Sing insulating layer 65 is laminated on the p-type Si substrate 1, and a polysilicon layer 64 is laminated on the upper surface thereof. Then, a SiO□ insulating layer 3 having a gap of an appropriate width is laminated on the polysilicon layer 64 so as to cover these layers, and on the polysilicon layer 64 including between the gears,
A gate electrode 62 is formed. In the p-type Si substrate 1 on both sides of the layer having the gate electrode 62, there is an n° buried layer 66 which is a source region on the light emitting diode 2 side, and a drain layer 66 on the side opposite to the layer having the gate electrode 62 between them. An n-buried layer 67, which is a region, is formed. Said n
``A source electrode 61 is formed on the upper surface of the p-type Si substrate 1 corresponding to the buried layer 66, including a part of the upper surface of the insulating layer 3 on the light emitting diode 2 and the insulating layer 3 on the polysilicon layer 64. On the upper surface of the p-type Si substrate 1 corresponding to the n° buried layer 67, there is an insulating layer 3 laminated on the p-type St substrate 1.1 with an insulating N3 on the polysilicon layer 64 and a gap of an appropriate width from this layer. A drain electrode 63 is formed including a part of the upper surface of. In addition, the insulation N3 including the light emitting diode electrode 4
A wiring metal film 5 made of an Al thin film is laminated thereon, and is connected to a drain electrode 61.

A method for manufacturing a semiconductor device having such a configuration is as follows. First, on the inside of a p-type Si substrate 1 on which a MOS transistor 6 (described later) is formed, there is an n° buried layer 66, which is a source region, on the side where a layer of a light emitting diode 2 (described later) is formed, with a gap of an appropriate width. However, on the opposite side of the gap, there is an n° buried layer 6 which is a drain region.
7 are respectively formed by diffusion. and p-type St substrate 1
A GaAs buffer layer 21. A p-type GaAs layer 22 and an n-type GaAs layer 23 are epitaxially grown in this order, and the resulting epitaxial layer is etched into an island shape to form a light emitting diode 2. Further, on the other end side of the p-type St substrate 1, a SiO□ insulating film 65 and a polysilicon layer 64 are laminated in this order by the CVD method at a position corresponding to the gap between the n+ buried layer 66 and the n° buried layer 67. . After laminating an insulating layer 3 on the entire p-type Si substrate 1 obtained in this way by a method such as vapor growth, a portion on the n-type GaAs layer 23 where the light emitting diode electrode 4 is formed, The portions where the upper source electrode 61 and drain electrode 63 are to be formed and the portion on the polysilicon layer 64 where the gate electrode 62 is to be formed are etched into predetermined shapes, and the insulating layer 3 is removed.

Then, a light emitting diode electrode 4 is formed on the part where the insulating layer 3 is removed. Source electrode 61. A drain electrode 63 and a gate electrode 62 are each deposited by a method such as an electron beam evaporation method.

Furthermore, Aβ is vacuum-deposited on the insulating layer 3 including the light emitting diode electrode 4 using a lift-off method to form a wiring metal film 5 made of an Af thin film and connected to the source electrode 61.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, when an epitaxial layer made of GaAs is etched into an island shape, the end face of the epitaxial layer often becomes an inverted mesa shape, and the GaAs epitaxial layer is not heat-treated at high temperatures. Therefore, the stenop coverage method of the insulating layer 3 was often insufficient.

As a result, the A1 thin film, which is a metal film for wiring, is disconnected at the part A in FIG. This has caused a problem in that the manufacturing yield of semiconductor devices is significantly reduced due to short circuits.

Furthermore, since the dielectric constant of the insulating layer used in conventional semiconductor devices is usually large, the parasitic capacitance associated with wiring becomes large.
Another problem was that the transient response characteristics deteriorated.

The present invention has been made in view of the above circumstances, and provides a semiconductor device that can reduce disconnections and short circuits in the wiring metal film connecting a light emitting diode electrode and a source electrode, and can also reduce parasitic capacitance. The purpose is to provide a manufacturing method.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which an electrode on a semiconductor substrate and an electrode on an epitaxial layer formed in an island shape on the semiconductor substrate are connected using a wiring substrate. , forming unevenness on the wiring substrate in a complementary relationship with the unevenness on the semiconductor substrate;
A process of forming a metal film for wiring on the upper surface thereof, a process of forming metal bumps at positions on the metal film for wiring corresponding to each of the electrodes of the semiconductor substrate, and an unevenness of the metal film for wiring and the semiconductor substrate. In the method for manufacturing a semiconductor device of the present invention, first, the method for manufacturing a semiconductor device includes the step of bonding the electrode and the metal bump with the unevenness of the semiconductor substrate facing each other. After forming related irregularities on the wiring substrate, a wiring metal film is formed. Then, metal bumps are formed at positions corresponding to the electrodes on the semiconductor substrate and the electrodes on the epitaxial layer formed in an island shape on the semiconductor substrate, so that the unevenness on the wiring substrate and the unevenness on the semiconductor substrate are complementary to the unevenness on the wiring substrate. The electrode and the metal bump are bonded so that they face each other.

In this way, a metal wiring film having a shape corresponding to the surface shape of the semiconductor substrate can be formed. Furthermore, since the electrodes of the semiconductor substrate and the metal wiring film are coupled via the metal bumps,
The bonding force between the former and the latter is increased, and the metal wiring film can be arranged on the semiconductor substrate with a constant spacing,
The parasitic capacitance associated with the wiring between the semiconductor substrate and the metal film for wiring can be reduced.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof. FIG. 1 is a structural cross-sectional view schematically showing a semiconductor device manufactured by the manufacturing method according to the present invention. In FIG. 1, reference numeral 1 denotes a p-type Si substrate as a semiconductor substrate, and on one end side of the upper surface thereof, a buffer 7, a GaAs layer 21. n-type G
aAs layer 22. N-type GaAs layers 23 are laminated in this order. Further, on the upper surface of the n-type GaAs layer 23, Au-
Light emitting diode electrodes 4 made of Zn/In are laminated, and metal bumps 11 made of Au, Sn, Pb-3n solder or the like are formed on the upper surface thereof. On the other hand, p-type Si substrate I
An insulating film 65 made of SiO□ is laminated on the other end side of the top, and a polysilicon layer 64 is formed on the upper surface thereof. A gate electrode 62 made of AJRIn is formed on the upper surface of the polysilicon layer 64.
In the p-type Si substrate l on both sides of the layer having the gate electrode 62, there is a buried layer 66 which is a source region on the side of the light emitting diode 2, and a buried layer 66 which is a drain region on the side opposite to the layer having the gate electrode 62. ``A buried layer 67 is formed respectively. At positions on the upper surface of the p-type Si substrate 1 corresponding to the n° buried layer 66 and the n° buried layer 67, there are source electrodes 61. made of A E /In. A drain electrode 63 made of A j2 /In is formed.

Further, a metal bump 11 is bonded to the upper surface of the source electrode 61, and the upper surface of the metal bump 11 and the light emitting diode electrode 4 are connected to each other.
A common wiring metal film 5 made of a metal such as Al, Cu, or Au is formed on the upper surface of the upper metal bump 11.
A passivation film 10 made of SiO2 or the like is formed on the lower surface of the metal film 5 for wiring.

Next, regarding the method of manufacturing a semiconductor device having such a configuration,
The process will be explained based on FIG. 2 showing the process.

As shown in FIG. 2(a), a light emitting diode 2 is formed on one end of a p-type Si substrate 1, and a MOS transistor 6 is formed on the other end using a normal MO5 manufacturing method.

First, a buried layer 66, which is a source region, is formed on the light emitting diode 2 side with a gap of an appropriate width inside the p-type Si substrate 1 in which a MOS transistor is formed, and a drain layer 66 is formed on the opposite side across the gap. area n°
A buried layer 67 is formed by diffusion. Then, a buffer GaAs layer 21 is formed on one end side of the p-type Si substrate l by a method such as MOCVD. n-type GaAs layer 22 and n-type G
The aAs layer 23 is epitaxially grown and laminated in this order, and the resulting epitaxial layer is etched into an island shape to form a layer of the light emitting diode 2 on the p-type Si substrate 1.

Furthermore, a light emitting diode electrode 4 is disposed on the n-type GaAs layer 23.
form. Further, on the other end side of the p-type Si substrate 1, n
An insulating layer 65 and a polysilicon layer 64 are laminated in this order at a position corresponding to the gap between the buried layer 66 and the buried layer 67, and a gate electrode 62 is deposited on the upper surface thereof.

Then, a source electrode 61,
A drain electrode 63 is formed by vapor deposition. The upper surface of the p-type Si substrate 1 formed in this manner has irregularities of about 5 μm. Next, in Fig. 2 (bl) wiring board 7 made of quartz.
On the upper surface, phosphor glass 8 is formed with unevenness that is complementary to the unevenness on the p-type Si substrate 1, that is, has a position and a height that compensates for the unevenness on the p-type Si substrate 1. The procedure is as follows. Phosphorous glass 8 is deposited on a quartz wiring substrate 7 by CVD method, and a p-type Si substrate 1 is formed.
The unevenness complementary to the unevenness is formed by etching. After etching, the phosphor glass 8 is heat-treated at a high temperature to make the end surface smooth, and a peeling film 9 of a resist used in photolithography with a thickness of 2 μm and removable with acetone is formed on the upper surface. Further, by depositing i on the upper surface of the peeling film 9 and etching it into a predetermined shape, the film thickness is reduced to approximately 1.
μm1 width is 10A! A wiring metal film 5 made of an Al thin film having a thickness of m is formed.

Then, metal bumps 11 made of Au and having a height of about IO μm are formed by electroplating on the wiring metal film 5 at positions corresponding to the light emitting diode electrodes 4 and the source electrodes 61 on the p-type Si substrate 1, respectively. Formed by a method such as At this time, as shown in FIG. 2(b), a passivation film IO of 5 iOz or the like may be laminated on the wiring metal film 5 (the passivation film 10 may be laminated via metal bumps 11, which will be described later). Even if slack occurs in the wiring metal film 5 when connecting the wiring metal film 5 with the light emitting diode electrode 4 and the source electrode ff161, it is formed so as not to come into direct contact with the conductive portion on the Si substrate.The wiring made of quartz The side having the above-described structure on the substrate 7 is crimped to the layered side of the Al p-type Si substrate 1 in FIG. The source electrodes 61 are bonded to each other.Then, the peeling film 9 is removed using a hot material such as acetone.Therefore, the wiring plate 7 is also removed at this time.Then, the wiring metal film 5 and the passivation film laminated thereon are removed. 2 (C1), the light emitting diode electrode 4 of the light emitting diode 2 of the p-type Si substrate 1 and the source electrode 61 of the -OS transistor 6 are connected, leaving only the light emitting diode 10 remaining, to manufacture a semiconductor device.

In the method for manufacturing a semiconductor device described above, the metal bumps 1
After bonding 1 to the light emitting diode electrode 4 and source electrode 61, the wiring substrate 7 is removed because a large number of chips, which are semiconductor devices, are usually arranged on the p-type Si substrate 1, so chip division is necessary. This is to facilitate the process and to reuse the wiring board 7. Transparent quartz is suitable for the wiring board 7, and the reason for this is that wiring materials such as metal bumps can be seen from the back side of the wiring board 7, making it easy to align with the Si substrate 1, which is a semiconductor substrate. It will be done.

Although a quartz plate is used for the wiring board 7 in this embodiment, the present invention is not limited to this, and materials such as a silicon plate that are commonly used in the semiconductor field may be used instead.

〔effect〕

As detailed above, in the method of manufacturing a semiconductor device of the present invention, the end surface of the phosphor glass formed on the upper surface of the wiring substrate can be made smooth, so that the metal film for wiring formed on the upper surface can be Even if the difference in unevenness is large, the wire will not be disconnected and can be obtained inexpensively and easily. In addition, the shape of the wiring metal film formed on the wiring substrate is complementary to the unevenness of the semiconductor substrate, so it is possible to maintain a constant spacing on the semiconductor substrate without adjusting the height of the metal bumps. A metal film for wiring can be placed. As a result, parasitic capacitance associated with wiring can be reduced, and a high-speed semiconductor device can be obtained. In addition, short circuits between the wiring metal film and the GaAs and Si of the semiconductor device can be prevented without the presence of an insulating film on the top surface of the light emitting diode and the top surface of the MOS l-transistor, which improves manufacturing yield and enables low-cost semiconductor devices. The present invention has excellent effects such as the following.

In this example, a peeling film is formed between the wiring board and the wiring metal film, and this has the effect that the wiring board and the wiring metal film can be peeled off quickly and easily. has.

[Brief explanation of the drawing]

FIG. 1 is a structural cross-sectional view schematically showing a semiconductor device manufactured by the method of the present invention, FIG. 2 is a schematic cross-sectional view showing the method of the present invention in the order of steps, and FIG. 3 is a structural cross-sectional view of a conventional semiconductor device. It is. 1... St substrate 4... Light emitting diode electrode 5...
・Metal film for wiring 61... Source electrode 7... Substrate for wiring 8... Phosphorus glass 9... Peeling film 11... Metal bump patent Applicant Sumitomo Metal Industries Co., Ltd. Agent Patent attorney Kawa No Noboo's funeral map

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which an electrode on a semiconductor substrate and an electrode on an epitaxial layer formed in an island shape on the semiconductor substrate are connected using a wiring substrate, comprising: A step of forming unevenness on a wiring substrate in a complementary relationship with the unevenness of the semiconductor substrate, a step of forming a metal film for wiring on the upper surface thereof, and a step of forming the metal for wiring corresponding to each of the electrodes of the semiconductor substrate. A semiconductor device comprising the steps of: forming a metal bump at a position on the film; and bonding the electrode and the metal bump with the unevenness of the wiring metal film facing the unevenness of the semiconductor substrate. Production method.