JPH02156534A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent depletion or inversion of the interface of a silicon film on the side of a semiconductor layer by implanting an element such as aluminum or calcium into the silicon film for thermally oxidizing the same and generating fixed charge in the silicon insulating film thus obtained for making the interface on the side of the semiconductor layer storable. CONSTITUTION:A silicon layer 5 is deposited on a P-type semi conductor layer 2 and aluminum(Al) is implanted therein. The silicon layer 6 is then annealed within argon gas and heated in the atmosphere of oxygen to be oxidized, whereby the Al is diffused uniformly within the silicon layer 5 while the silicon is oxidized to be SiO2. Thus, an insulating layer 1 of SiO2 containing Al diffused uniformly is obtained. Within the insulating layer 1, the oxygen is combined with the aluminum to produce alumina which breaks the amorphousness of the insulating layer 1 and produces a kind of stress. Accordingly, the insulating layer 1 is charged with minus electricity. As a result, a P<+> type layer 2a is produced at the interface of the insulating layer 1 with the substrate 2. In this manner, the interface region of the semiconductor layer becomes storable and depletion or inversion of this region can be prevented.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device and a method for manufacturing the same, the purpose is to easily control the charge distribution at the interface between an insulating film and a semiconductor layer, and a silicon film containing aluminum, calcium, etc. The structure includes forming an insulating film having fixed charges for accumulating the surface of the semiconductor layer by injecting a substance and thermally oxidizing it.

[Industrial application field]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including an insulating film such as a LOGO3, a trench-type element isolation layer, a gate oxide film, and a method of manufacturing the same.

[Conventional technology]

LOGOS (local oxidation
fSk), for example, as shown in FIG. 20, a window 72 is formed in a nitride (StsN4) film 71 stacked on a p-type silicon substrate 70, and the The surface of the silicon substrate 70 is thermally oxidized to form an isolation layer 7 made of silicon dioxide (SiO).
3 is formed, and the space between the isolations 73 is used as an element forming region 74.

By the way, sto! formed by thermal oxidation! Since a positive interface level is generated by unreacted silicon at the interface between the film and the silicon substrate 70, negative charges are often induced at the interface of the substrate 70, causing inversion and depletion. There is.

In order to solve this problem, before forming the isolation 73, group Ⅰ elements such as boron and aluminum should be added to the nitride film 73.
These elements are implanted through the window 72 of No. 1, and the p° layer 70a formed at the interface of the substrate 70 prevents inversion and depletion, but these elements are thermally oxidized as shown in FIG. At this time, there is a problem in that it diffuses into the element formation region 74, narrowing its effective area.

In addition, when forming the isolation ramp 73 using LOGO3, the isolation ramp 3 is formed using a bird's beak.
There is a problem that the degree of integration cannot be sufficiently increased because of the widening of the area.

On the other hand, when separating the elements by groove-type isolation, as shown in FIG. 21, the inner surface of the groove 76 formed in the substrate 75 is thermally oxidized to grow SiO After forming the film for 7 days, the groove 76 is filled with polysilicon 79, and the LOGO
There is no need to consider the stress and bird's beak as in 3, and the width of the element bone N region can be formed narrow.

However, the SiO□ film 77 on the inner surface of the groove 76 has LOCO
Similar to 3, interface states are generated, so it is necessary to eliminate depletion and inversion caused by the interface states by doping the group ■ element around it in advance to generate p''Ji75a. When the film 77 is formed by thermal oxidation, there is the same problem as in LOGO 8 that the element forming region 80 is narrowed due to the diffusion of the group Ⅰ elements.

By the way, the phenomenon that the interface on the substrate 70, 75 side becomes depleted or inverted due to the provision of the isolation for element isolation as described above is caused by the gate oxide film 81 made of the Sing of the MOSFET as shown in FIG. exists at the interface of the silicon substrate 82, thereby causing the MOSFE
Problems occur such as the T malfunctioning and the dark value fluctuating.

As a means to prevent the generation of depletion layers and inversion layers caused by the above-mentioned interface states, LOCO51 groove type eye
tsuresion, aluminum is implanted into the Si0g film that constitutes the gate oxide film of the MOSFET.
A method of using a film as a negative fixed charge layer has been proposed.

[Problem to be solved by the invention]

However, when implanting an element such as aluminum into the SiO film, the element exists in a Gaussian distribution in the SiO film, so if aluminum is implanted only into the SIO film, the amount of aluminum near the interface becomes extremely small, making it difficult to adjust the amount of fixed charge generated by aluminum.

In this case, it may be possible to apply heat to the SiJ film into which aluminum is implanted to cause diffusion, but in reality, the distribution does not change even after heating, and the amount of elements at the interface remains small. This does not solve the problem that the adjustment range of the amount of charge is narrow.

In particular, in MOS FETs, it is difficult to adjust the dark value because the implanted elements exist in a Gaussian distribution.
This film needs to be formed extremely thin, on the order of 500 layers, and if the amount of elements implanted is increased, another problem arises in that the implanted elements penetrate through the gate oxide film and reach the substrate.

In addition, in trench type isolation, since elements are implanted from above, there is a problem that even if the implant direction of the element changes sufficiently, depletion and inversion above the trench cannot be sufficiently prevented in the lower part of the sidewall. There is.

The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device in which the element distribution at the interface with an oxide film can be easily controlled.

[Means to solve the problem]

The problem described above is that in a semiconductor device equipped with an insulating layer formed directly on the semiconductor layer or via an insulating film, a diffusible element that generates a fixed charge to accumulate on the surface of the semiconductor layer is added to the silicon layer. A semiconductor device characterized by comprising an insulating layer formed by injection into a semiconductor layer and thermally oxidizing the semiconductor device, or a semiconductor device including a step of depositing an insulating layer directly or through an insulating film on the semiconductor layer. In the manufacturing method, a step of forming a silicon layer directly on the semiconductor layer or via the insulating film, and a step of diffusing to generate fixed charges in the silicon layer for accumulating the surface of the semiconductor layer. The present invention is solved by a method for manufacturing a semiconductor device, which comprises a step of implanting a diffusible element, and a step of thermally oxidizing the silicon layer into which the diffusible element is implanted to form an insulating layer.

[For production]

In the above invention, if a silicon film is deposited directly or indirectly on the semiconductor layer and an insulating layer is formed by thermal oxidation with elements such as aluminum and calcium injected into the silicon film, this silicon-based insulator The layer generates a negative fixed charge and has a fixed charge of opposite polarity to the P-type semiconductor layer, so at the interface on the semiconductor layer side, this region becomes depleted as the semiconductor layer accumulates. This means that it can be prevented from changing or reversing.

Furthermore, by using vA particles such as aluminum and calcium that thermally diffuse in silicon films, it is possible to make the element distribution uniform inside the insulating layer formed from the silicon film. In this case, since fixed charges are generated in an amount substantially proportional to the amount of implanted elements, it is easy to adjust the amount of fixed charges iPl at the interface on the semiconductor layer side.

Thereby, even when this embodiment is applied to the gate oxide film of a MOS FET, it is possible to adjust the dark value and make the dark value uniform.

Furthermore, when this insulating film is used for isolation for element isolation, there is no treatment such as implantation of an element for inversion prevention, such as boron, before forming this isolation, so the element for inversion prevention is heat-treated. Therefore, the phenomenon of diffusion and intrusion into the element formation area does not occur, and the element formation area is not narrowed.

[Example] (a) Description of the first embodiment of the invention FIG. 1 is a sectional view of a device showing the first embodiment of the invention, in which the reference numeral 1 indicates a P-type semiconductor layer 2. This is an insulating layer laminated directly on the top ((a) of the figure) or via an insulating film 3 ((b) of the same figure). It is formed by thermally oxidizing a material injected with diffusible elements such as aluminum and calcium, and has a negative fixed charge.

In this example, a p layer 2a is generated at the interface on the semiconductor N2 side due to negative fixed charges in the insulating layer 1 (
This 21st layer 2a is also called an accumulation layer).

Next, an example of the manufacturing process of the insulating layer 1 will be described.

First, a polycrystalline, single-crystalline, or amorphous silicon layer 5 is laminated on a p-type semiconductor layer 2, and after implanting aluminum (^1) into this layer (Fig. 2(a)), this silicon layer 5 is laminated on a p-type semiconductor layer 2. When the layer 5 is annealed in argon gas and then heated and oxidized in an oxygen atmosphere, ^ within the silicon layer 5.
As l diffuses uniformly, silicon oxidizes to 5i0
2, so 5iOt with uniformly distributed aluminum
An insulating layer 1 consisting of the following is formed.

In this insulating layer 1, oxygen and aluminum combine to generate alumina, which destroys the amorphous nature of the insulating layer 1 and generates a type of stress, so this insulating layer 1 becomes negatively charged (second Figure (b)).

As a result, the interface on the substrate 2 side becomes a p'' layer 2a.

Next, this embodiment will be explained in more detail.

Silicon dioxide (Sing) is deposited on the surface of the p-type semiconductor layer 2.
An insulating film 3 made of the following is laminated to a thickness of 100 layers, and a polycrystalline silicon layer 5 is formed thereon to a thickness of about 2000 layers.

From above, add 40 ^l [EVL 5X10” pieces/cd
After injecting these into an argon gas atmosphere and performing thermal diffusion treatment, thermal oxidation is performed, and an electric current is formed on this to create a MOS diode D, and its C-V characteristics are measured. Figure 3(a)).

FIG. 3(b) shows a MOS diode D C-
■Characteristics and CV characteristics of a conventional MOS diode device (not shown) without aluminum implantation, which is a characteristic diagram showing the relationship between gate voltage (V,) and diffusion temperature when the amount of surface charge becomes zero. , the white plot is silicon film 5
The case where ^1 is not injected is shown, and the black plot is the case where AI is injected.

According to this diffusion temperature/V characteristic diagram, even when aluminum is injected into the silicon layer 5 and no thermal diffusion treatment is performed,
Gate voltage VFI than without aluminum implantation
It was found that the voltage V□ shifted by about 0.3 [V], and it became clear that when heat was added to this, the voltage V□ shifted even more.

Therefore, by changing the doping amount of aluminum and the diffusion temperature, it is possible to set the interface on the P-type semiconductor layer 2 side to 29, and it is possible to prevent this region from being depleted or inverted.

Moreover, since aluminum is diffused by heat and distributed uniformly in the silicon layer 5, a fixed charge is generated in the insulating layer l in approximately proportion to the amount of aluminum implanted, and the semiconductor layer 2 side Adjustment of the 29 layers 2a at the interface becomes easy.

As a result, by applying this embodiment to the gate oxide film of a MOSFET, it is possible to adjust the threshold value and make the dark value uniform.

Furthermore, when the insulating layer l is applied to isolation for element isolation, the inversion blocking element is not implanted into the semiconductor substrate before forming the isolation layer, so the inversion blocking element is not injected into the semiconductor substrate. The phenomenon of diffusion within the substrate 2 and invasion of the element formation area due to heat treatment does not occur, and according to the present invention, the element formation area is not narrowed.

(b) Description of the second embodiment of the present invention FIG. 4 is a cross-sectional view of the LOCO 8 showing the second embodiment of the present invention. This isolation 6 is formed by thermally oxidizing a silicon film doped with aluminum, and the inside thereof is a negative fixed charge layer, and the interface of the substrate 7 is P0. Therefore, inversion and depletion are prevented.

Next, a method for forming the isolation 6 will be explained based on FIG. 5.

First, a polysilicon film 9 is laminated on the S10□ film 8 on the surface of the p-type silicon substrate 7, and positively ionized aluminum (AI) is implanted using an ion implantation device (not shown).
FIG. 5(a)), in this case AI" is a polysilicon film 9
will exist according to a Gaussian distribution.

Further, a nitride film 10 is laminated thereon, and then aluminum is diffused by annealing.

After that, the portion located in the element isolation region 6a is etched to form a window 11 (FIG. 5(b)), and when a thermal oxidation treatment is performed after this, the surface of the silicon substrate 7 in the element isolation region 6a and the polysilicon 11 are etched. ! J9 thermally expands to form isolation 6 (Fig. 5(c)). During this thermal oxidation, ^1 combines with oxygen to form alumina inside isolation 6. Alumina destroys the amorphous nature of the isolation 6 and causes a kind of stress, resulting in the formation of a negative fixed charge layer inside.

Thereafter, the nitride film 10 is removed with phosphoric acid and the unnecessary polysilicon film 9 is removed by photolithography or the like, thereby completing the device as shown in FIG.

Although aluminum was thermally diffused in this manufacturing process, it can also be used without being diffused.

Next, the operation of the above-mentioned isolation 6 will be described.

In the above-mentioned embodiment, as a result of the isolation 6 having a negative charge, the interface on the substrate 7 side is converted to p'.
No depletion layer or inversion layer is generated at the interface. Therefore, there is no need to pre-dope p-type elements such as boron into the element isolation region 6a, and these diffuse during thermal oxidation to form the element. The problem that the formation area 12 becomes narrower will be solved.

Furthermore, since the polysilicon film 9 is formed on the silicon substrate 7 and oxidized, the growth in the thickness direction is fast, the bird's beak is also small, and invasion into the element forming region 12 is suppressed.

(C) Description of the third embodiment of the invention FIG. 6 is a sectional view of LOGO 3 showing the third embodiment of the invention, in which reference numeral 13 indicates the element bone gl on the surface of the silicon substrate 14. This is isolation formed in the region 13a.

This isolation 13 is for the element Ii! sI area 13
A polysilicon film is formed in the gap between the two side walls 15 made of 5ksNa provided on both sides of the upper part of the film, and the film is doped with aluminum and thermally oxidized. This is a negative fixed cylindrical layer, and since the interface of the 14 substrates is changed to P°, inversion and depletion are prevented.

Note that the reference numeral 16 in the figure indicates a silicon dioxide (SiOz) film.

Next, a method for forming this isolation 13 will be explained based on FIG. 7.

After sequentially stacking the first nitride film 17 and the Sing film 18 on the 5i02 film 16 on the surface of the p-type silicon substrate 14, the element isolation region 13a portion of these films 17.18 is etched to form the window 19. is provided, and a second nitride film 20 is laminated thereon (FIG. 7(a)).

Thereafter, anisotropic etching is performed to remove the second nitride film 20 leaving only the inner peripheral surface of the window 19, and the second nitride film 20 remaining on the sides is used as the sidewall 15. At this stage, the surface of the silicon substrate 14 in the element bone NwI region 13a is exposed (FIG. 7(b)).

Furthermore, a polysilicon film 21 is formed on this by CVD method or the like.
After laminating, this is etched back and element bone # area 1
Two side walls 1 on both sides of the upper part of the substrate 14 of 3a
The second polysilicon film 21 is made to remain in the gap 5. After that, when positively ionized AI is doped,
A1 in the polysilicon film 21 in the sidewall 15
0 exists according to a Gaussian distribution (Figure 7 (
c) ).

Here, by annealing, A1 is removed from the polysilicon film 21.
It may be diffused and evenly distributed within the interior.

After that, the oxide film 18 is removed.

If thermal oxidation treatment is performed at this stage, the polysilicon film 21 between the sidewalls 15 and the surface of the substrate 14 below it will oxidize and expand, forming the isolation 13 (FIG. 7(d)).
*As a result, the isolation 13 has a negative fixed charge as in the second embodiment.

Finally, the first nitride film 1 is etched by wet etching or the like.
7 is removed, the device as seen in FIG. 6 is completed.

The operation of the isolation 13 formed in this way will be described.

In the above-described embodiment, the isolation 13 has a negative characteristic, and as a result, the interface on the substrate 14 side is made p°, so that no depletion layer or inversion layer is generated at the interface.

For this reason, there is no need to dope the P-type element into the substrate 14 as in the second embodiment, and the problem of narrowing the element formation region is solved.

Moreover, since the two sidewalls 15 are formed on the substrate 14 and the isolation 13 is grown between them, bird's beaks do not occur and the element isolation region 13a does not extend into the element formation region.

(d) Explanation of the fourth embodiment of the invention FIG. 8 is a cross-sectional view of LOGO3 showing the fourth embodiment of the invention, in which reference numeral 22 indicates a structure formed on the surface of a silicon substrate 23. This isolation 22 is made by directly doping aluminum from the Sing film 24 on the surface of the silicon substrate 23 and thermally oxidizing it, and the isolation 22 is a negative fixed charge layer as in the above embodiment. On the other hand, since a small amount of AI'' remains at the bottom without being thermally oxidized, the interface of the 23 substrates becomes ppo.

Therefore, even if the doping amount of A1 is reduced, inversion and depletion of the substrate 23 can be prevented.

A method of forming this isolation 22 will be explained based on FIG. 9.

First, an upper film 25 is stacked on the Sing film 24 on the surface of the silicon substrate 23, and a portion thereof located in the element molecule Mell region 22a is etched to form a window 26, exposing the stow film 24 in the element isolation region 22a. (Figure 9(a)
)).

After this, positively ionized aluminum (^l) is shallowly implanted into the surface layer of the substrate 23 (FIG. 9(b)).

The doping amount needs to be adjusted in advance to such an extent that AI will not diffuse into the element formation region during the subsequent heat treatment.

After this impurity implantation step, the surface of the substrate 23 is thermally oxidized to form the isolation 22 (FIG. 9(C)).
, it is necessary to perform heat treatment for a period of time long enough for the A1 element to remain at the bottom. During this thermal oxidation, negative fixed charges are generated inside the isolation 22 as in the second embodiment.

Next, the operation of the above-mentioned isolation 22 will be explained.

In the embodiment described above, as a result of the isolation 22 having a negative fixed charge, the interface of the substrate 23 becomes po, and since AI has been doped into the silicon substrate 23 in advance to become Pl, due to the synergistic effect, The interface is P''
Since the doping amount is 1, elements can be sufficiently isolated with a small amount of doping.

(e) Fifth embodiment of the present invention FIG. 10 is a sectional view of field isolation showing a fifth embodiment of the present invention. In the isolation run, this isolation 26 covers 5 holes on the surface of the substrate 27.
It is formed by doping aluminum into the polysilicon film formed on the t-film 28 and then thermally oxidizing only this polysilicon film. At the interface of the substrate 27, a p'' layer 27a is formed on the SiO□ film 28.

In the drawing, reference numeral 29 indicates an n'' layer formed in the element formation region 30 of the substrate 27, and 31 indicates a gate electrode.

Next, a method for forming this isolation 26 will be explained based on FIG. 11.

An eight polysilicon film 32 is laminated on the SiO□ film 28 on the surface of the P-type silicon substrate 27, and aluminum <
AI) is positively ionized and implanted. In this case, AI'' exists in the polysilicon film 32 according to a Gaussian distribution (FIG. 11(a)).

In this state, the AI may be diffused by annealing treatment to uniformly distribute the AI within the polysilicon film 32.

Next, thermal oxidation treatment is performed to make the polysilicon film 32 a negative fixed charge layer as in the second embodiment, but unlike the second embodiment, the oxidation is reduced to prevent the surface of the base Fi27 from being oxidized. (Figure 11(b)).

Further, the oxidized polysilicon film 32' is removed by dry etching except for the element bone N region, and the remaining portion is used as the isolation 26 (FIG. 11(C)).

Note that hydrofluoric acid is used to remove the 5i02 film on the surface of the substrate 27, and this hydrofluoric acid treatment also serves to remove damage to the substrate surface caused by dry etching.

The operation of the isolation 26 formed in this way will be described.

In this embodiment, as a result of the isolation 26 having a negative fixed charge, the interface on the substrate 27 side immediately below it has a p°
A layer 27a is generated, and two 10 layers 2 formed on both sides thereof
9. Electrons do not move between the two, which prevents malfunctions.

(f) Sixth embodiment of the present invention FIG. 12 is a cross-sectional view of field isolation showing a sixth embodiment of the present invention, in which reference numeral 33 is formed above a silicon substrate 34. This isolation 33 is formed by laminating a polysilicon film on the nitride film 35 on the substrate 34, doping aluminum into this film, and thermally oxidizing it. has a negative fixed charge as in the fifth embodiment, and a 5i02 film 3 is provided at the interface of the substrate 34 below it.
6, an accumulation layer 34a is formed.

In the drawing, reference numeral 37 indicates an n'' layer formed on the third day in the element formation region of the substrate 34, and 39 indicates a gate electrode.

Next, a method for forming this isolation 33 will be explained based on FIG. 13.

A thin nitride film 35 is formed on the SiO□ film 36 on the surface of the p-type silicon substrate 34, and a polysilicon film 40 is laminated thereon, and aluminum (AI) is positively ionized and implanted from above ( Figure 13(a)).

In this case, At'' exists in the polysilicon film 40 according to a Gaussian distribution.

In this state, A1 may be diffused by annealing treatment to uniformly distribute AI within the polysilicon film 40.

Next, the polysilicon film 40 is thermally oxidized to form a negative fixed charge layer as in the fifth embodiment (see FIG. 13).
b)). This produces an accumulation layer 34a at the interface of the substrate 34.

Furthermore, using a photomask (not shown), the oxidized polysilicon film 40' was dry-etched except for the element isolation region, and then the nitride film 35 in the element formation area was removed with phosphoric acid, and the remaining The portion is designated as isolation 33 (FIG. 13(c)).

Note that hydrofluoric acid is used to remove the 5tO2 film 36.

In the isolation 33 formed in this way, the nitride film 35 prevents oxidation of the surface of the substrate 34, making it easier to adjust the oxidation temperature and heating time compared to the fifth embodiment.

The effect of this embodiment is similar to that of the fifth embodiment, and it prevents negative charges from moving between the n+ layers 37 formed on both sides thereof.

(g) Description of Seventh Embodiment of the Invention FIG. 14 is a sectional view of a groove type isolation showing a seventh embodiment of the invention, in which reference numeral 41 indicates the surface of a silicon substrate 42. This isolation 41 is formed by forming a SiO□ film 44 on the entire inner surface of the groove 43. A polysilicon film 45 is sequentially formed, and the polysilicon film 45 is doped with aluminum and thermally oxidized.
The inside of 5' is a negative fixed charge layer, and an accumulation layer 43a is induced at the interface of the substrate 42 via the 5iO1 film 44.

Note that reference numeral 46 indicates non-doped polysilicon buried in the groove 43.

Next, a method for forming this isolation 41 will be explained based on FIG. 15.

First, a mask 47 is formed on the surface of a p-type silicon substrate 42, and element isolation regions 41 are etched by reactive etching.
A groove 43 is formed in the groove a (FIG. 15(a)). Then, after removing the mask 47, thermal oxidation is performed to uniformly form a 5iOt film 44 on the inner surface of the groove 43 (FIG. 15(b)).

Furthermore, if a polysilicon film 45 is stacked on the 5iO1 film 44 by the CVD method and positively ionized A1 is implanted from above, AI will exist in this film 45 according to a Gaussian distribution (Fig. 15). (C)).

In this state, A1 may be diffused by annealing treatment to uniformly distribute AI within the polysilicon film 40.

When thermal oxidation is then performed, the oxidized polysilicon film 45'
A negative fixed charge is generated in the groove 43 as in the first embodiment, and when the groove 43 is then filled with non-doped polysilicon, an isolation 4 as shown in FIG.
1 is completed. This produces an accumulation layer 43a at the interface of the substrate 42 examples.

Note that the polysilicon film 46 on the surface of the substrate 42 is removed by dry etching.

In the embodiment described above, the isolation 41 within the groove 43 has a negative fixed charge on its outside, resulting in
Since the interface on the substrate 42 side is made p0, no depletion layer or inversion layer is generated at the interface. For this reason, there is no need to implant elements such as boron into the element isolation region in advance.
The problem that this element diffuses during thermal oxidation and narrows the device formation area does not occur.

According to this embodiment, even if a sufficient amount of aluminum is not supplied to the lower part of the side wall of the groove 43, the diffusion coefficient is high.
Since 1 is sufficiently diffused in the polysilicon film 45 by heat treatment, it is finally distributed uniformly.

(h) Description of Eighth Embodiment of the Present Invention FIG. 16 shows a groove-type element isolation device showing an eighth embodiment of the present invention, in which reference numeral 48 denotes a groove 50 on the surface of a silicon substrate 49. This is the isolation formed within.

This isolation 48 is provided on the entire inner surface of the groove 50 by 5i.
OJjJ 51 and a nitride film 52 are sequentially formed, a polysilicon film 53 is further formed thereon by CVD, aluminum is doped into this polysilicon film 53, and this is thermally oxidized. ,
The inside of the oxidized polysilicon film 53' is a negative fixed charge layer, and 5iOill! is formed at the interface on the substrate 49 side. 51
An accumulation layer 50a is induced through the .

Note that reference numeral 54 indicates non-doped polysilicon buried in the groove 50.

Next, a method for forming this isolation for 4 days will be explained based on FIG. 17.

First, as in the seventh embodiment, a groove 50 is formed in the pixel bone M6N region using a mask 55, and a 5ift film 51 formed by thermal oxidation and a nitride film 52 formed by vapor phase growth are uniformly laminated on the inner surface of the groove 50. (Fig. 17(a), (b)).

Furthermore, a polysilicon film 53 is laminated by CVD method,
When positively ionized AI is implanted from above, ^10 will exist in the polysilicon film 53 according to a Gaussian distribution (FIG. 17(C)).

In this state, AI may be diffused by annealing.

Then, by thermal oxidation treatment, groove-shaped isolation 4 is formed.
8 forms a negative fixed charge layer as in the seventh embodiment. As a result, the accumulation layer 50a is formed at the interface of the substrate 49.
occurs.

Finally, the inside of the trench 50 is filled with non-doped polysilicon 54, and then the non-doped polysilicon 54 around the trench 50 is removed by etching back.

In the embodiment described above, the surface of the substrate 49 is covered with the nitride film 5.
2 prevents oxidation, making it easier to adjust the oxidation temperature and oxidation time compared to the seventh embodiment.

Further, the lower part of the side wall of this groove 50 and the groove bottom are doped with A.
Even when the I concentration is low, since AI having a high diffusion coefficient is sufficiently diffused in the polysilicon layer 53 by heat treatment, its distribution becomes uniform in the end.

Furthermore, as a result of the eye-flag 95 in the groove 50 having a negative fixed charge on the outside thereof, the interface on the substrate 49 side is converted into a p-oxide, so that a depletion layer or an inversion layer is generated at the interface. Therefore, there is no need to implant an element such as boron into the element isolation region in advance, and there is no problem that this element diffuses during thermal oxidation and the element formation region becomes narrower.

(i) Description of the ninth embodiment of the present invention FIG. 18 shows a MOSFET showing the ninth embodiment of the present invention.
In this cross-sectional view, reference numeral 56 indicates a Si formed in an element formation region 58 on the surface of a silicon substrate 57.

A second gate insulating film 59 is formed on the first gate insulating film. This second gate insulating film 59 is made by thermally oxidizing a polysilicon film doped with aluminum, and has a negative fixed charge layer inside, and an accumulation layer at the interface on the substrate 57 side. Therefore, inversion and depletion due to stress, interface states, etc. are prevented.

In the figure, reference numeral 60 indicates a gate electrode formed on the second gate insulating film 59, 61 indicates an insulating film for isolation between elements, and 62 indicates a gate electrode formed on the second gate insulating film 59.
indicates the drain, and 63 indicates the source.

Next, a method for forming the second gate oxide film 59 will be explained based on FIG. 19.

A 5ift film 64 and a polysilicon film 65 are formed on the surface of the silicon substrate 57 (FIG. 19(a)), and when ^l is injected into the polysilicon film 65 and subjected to thermal diffusion treatment,
Aluminum is polysilicon I! ! 65 and is distributed in a −-like manner (FIG. 19(b)).

After this, when the polysilicon film 65 is thermally oxidized, a second
The gate oxide film 59 becomes a gate oxide film 59, and negative fixed charges are generated inside the gate oxide film 59.

Furthermore, after forming a polysilicon film 66 for a gate electrode thereon (FIG. 19(c)), the polysilicon film 66 and oxide films 59 and 64 other than the area where the gate electrode is to be formed are removed, and the substrate 57 is removed. Polysilicon film 6 remaining on the top layer of
6 is used as the gate electrode 60 shown in FIG. 18, and the SiO□ film 64 is used as the first gate insulating film 56.

Finally, arsenic is ion-implanted into both sides of the gate electrode 60 in a self-aligned manner to form a source 63 and a drain 62 (FIG. 19(d)).

According to this embodiment, the aluminum distribution in the second gate electrode 59 can be made uniform, and the accumulation layer at the interface on the semiconductor substrate side can be easily adjusted, and the threshold value of the MOSFET can be adjusted and the dark value can be made uniform. can be achieved.

(j) Description of other embodiments In the embodiments described above, A1 was implanted into the polysilicon film, but other elements such as calcium, potassium, and strontium were doped to provide isolation with a negative fixed charge layer. It is also possible to do so.

Furthermore, in the above embodiments, a negative fixed charge is applied to the insulating film, but when an n-type substrate is used, a positive fixed charge is applied to prevent inversion and depletion on the substrate side. It is also possible to prevent it.

Further, in the above embodiments, the film formed above the semiconductor substrate is a polycrystalline silicon film, but it may also be a single crystal silicon film or an amorphous silicon film.

Note that, in addition to silicon, germanium or the like can also be used for the semiconductor substrate on which the insulating film is formed.

〔Effect of the invention〕

As described above, according to the present invention, by implanting elements such as aluminum and calcium into a silicon film and thermally oxidizing the silicon film, an interface on the semiconductor layer side is formed in a silicon-based insulating film formed by thermal oxidation. Since the fixed charge that accumulates is generated, when this insulating film is used for isolation for element isolation, an element is added to the semiconductor layer to prevent inversion and depletion at the interface on the semiconductor layer side. There is no need to implant the element into the layer in advance, and the phenomenon that elements diffuse into the element forming region due to heat treatment does not occur, making it possible to suppress the element isolation region to a desired width.

In addition, since this insulating film is formed based on a silicon layer, elements such as aluminum and calcium that are implanted into this insulating film can be diffused in advance by annealing. The internal element distribution can be made uniform, and a fixed charge will be generated at the interface on the insulating layer side in an amount that is approximately proportional to the amount of the implanted material, making it possible to adjust the accumulation layer at the interface on the semiconductor side. As a result, it becomes easy to adjust the dark value of the MOSFET.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a device showing the first embodiment of the present invention, FIGS. 2(a) and (b) are manufacturing process diagrams of the device of the first embodiment of the present invention, and FIG. 3( a) and (b) are cross-sectional views of a diode formed based on the first embodiment of the present invention, and enlarged r! ia degree/■□ characteristic diagram, Figure 4 is a sectional view of LOGOS showing the second embodiment of the present invention, Figures 5 (a) to (C) are the diagrams of the device of the second embodiment of the present invention. 6 is a cross-sectional view of LOGOS showing the third embodiment of the present invention; FIGS. 7(a) to 7(d) are manufacturing process diagrams of the device of the third embodiment of the present invention; FIG. 8 is a sectional view of LOGOS showing the fourth embodiment of the present invention, FIGS. 9(a) to (c) are manufacturing process diagrams of the fourth embodiment of the present invention, and FIG. 10 is , sectional view of field isolation showing the fifth embodiment of the present invention, FIGS. 11(a) to (C) are manufacturing process diagrams of the fifth embodiment of the present invention, FIG. 13(a) to (C) are manufacturing process diagrams of a device according to a sixth embodiment of the present invention; FIG. 14 is a cross-sectional view of a field isolation device showing a sixth embodiment of the present invention. 15(a) to 15(d) are manufacturing process diagrams of a device according to a seventh embodiment of the present invention; FIG. 17(a) to (d) are manufacturing process diagrams of the eighth embodiment of the present invention, and FIG. 18 is the ninth embodiment of the present invention. MOSFET showing an example of
19(a) to 19(d) are manufacturing process diagrams of the ninth embodiment of the device of the present invention. FIG. 20 is a sectional view showing the first example of the conventional device.
The figure is a sectional view showing a second example of the conventional device, and FIG.
FIG. 7 is a sectional view showing a third example of a conventional device. (Explanation of symbols) 1... Insulating layer obtained by thermally oxidizing a silicon film into which elements are implanted, 2... Semiconductor layer, 3... Insulating layer obtained by oxidizing silicon, 5... Silicon layer, 6.13. 22...Isolation, 7.14.2
3...Silicon substrate, 9.21...Polysilicon film, 26.33...Isolation, 27.34...Silicon base substrate, 32.40...Polysilicon film, 32', 40'...oxidized polysilicon film, 41.
48... Isolation, 2a, 27a... Pi degree, 34a, 43a, 50a... Accumulation layer 45.53... Polysilicon film, 45', 53'... Oxidized polysilicon film, 44.
49... Silicon substrate, 56... First gate insulating film, 57... Silicon substrate, 59... Second gate insulating film, 65... Polysilicon film.

Claims (2)

[Claims] (1) In a semiconductor device equipped with an insulating layer formed directly on the semiconductor layer or via an insulating film, a diffusible element that generates a fixed charge to accumulate on the surface of the semiconductor layer is added to the silicon layer. 1. A semiconductor device comprising an insulating layer formed by injecting into the material and thermally oxidizing the insulating layer. (2) A method for manufacturing a semiconductor device including a step of depositing an insulating layer directly or through an insulating film on the semiconductor layer, the step of forming a silicon layer directly on the semiconductor layer or through the insulating film. a step of implanting into the silicon layer a diffusible element that generates a fixed charge for accumulating the surface of the semiconductor layer; and thermally oxidizing the silicon layer into which the diffusive element has been implanted. A method for manufacturing a semiconductor device, comprising the steps of forming an insulating layer.