JPH0215631A - Al wiring part in semiconductor device - Google Patents

Al wiring part in semiconductor device

Info

Publication number
JPH0215631A
JPH0215631A JP16524988A JP16524988A JPH0215631A JP H0215631 A JPH0215631 A JP H0215631A JP 16524988 A JP16524988 A JP 16524988A JP 16524988 A JP16524988 A JP 16524988A JP H0215631 A JPH0215631 A JP H0215631A
Authority
JP
Japan
Prior art keywords
wiring
alloy
wiring part
semiconductor device
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16524988A
Other languages
Japanese (ja)
Inventor
Zenichi Akiyama
善一 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP16524988A priority Critical patent/JPH0215631A/en
Publication of JPH0215631A publication Critical patent/JPH0215631A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the generation of a hillock by a method wherein the maximum Al wiring width between an Al wiring part and an Al alloy wiring part in a semiconductor device and the mean grain size of Al in the case where an Al thin film is formed by a vacuum deposition method are set in a specified relation. CONSTITUTION:When the mean grain size of Al in the case where an Al thin film is formed by a vacuum deposition method is assumed to be d(ev), the maximum Al wiring width W between an Al wiring part and an Al alloy wiring part in a semiconductor device is within an extent of W<=5Xd(ev) and when the mean grain size of Al in the case where the Al thin film is formed by a sputtering method is assumed to be d(sp), the maximum Al wiring width W is within an extent of W<=50Xd(sp). In such a way, the wiring width between the Al wiring part consisting of an Al film and the Al alloy wiring part consisting of an Al alloy film in the semiconductor device is controlled by the mean grain size of Al. By limiting the absolute quantities of the distortions of the films and the absolute quantity of a grain boundary which is regarded as an active point of the generation of a hillock by a wiring width, the generation of a hillock is prevented.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はヒロックを防止し得る半導体装置のAl配線に
関し、多結晶シリコン薄膜トランジスタ全般に応用でき
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to Al wiring for semiconductor devices that can prevent hillocks, and is applicable to polycrystalline silicon thin film transistors in general.

〔従来の技術〕[Conventional technology]

近年、半導体装置の高集積化に伴い配線メタル技術にお
いては、多層配線化が進み、一方、多結晶シリコン、を
絶縁性基板に堆積させる大面積化デバイス、例えば薄膜
トランジスタデバイスが新しい技術分野として開発され
てきている。
In recent years, as semiconductor devices have become more highly integrated, multi-layer wiring has progressed in metal wiring technology, while large-area devices such as thin film transistor devices, in which polycrystalline silicon is deposited on an insulating substrate, have been developed as a new technological field. It's coming.

これに伴い、配線用Alff4においては、ヒロック発
生の問題がクローズアップされていきた。
Along with this, the problem of hillock occurrence in wiring Alff4 has been brought into focus.

すなわち、多層配線メタル構造においては1層メタル/
層間膜/2層メタルでのヒロックによる層間リークがデ
バイスの歩留りおよび信頼性に悪影響をもたらしていた
。また、大面積化デバイス、例えばその応用例としてセ
ンサー駆動用TPT、液晶パネルおよびELパネル駆動
用TPT等では、共通して薄膜トランジスタ部形成の後
にその上層部にデバイスが形成されて完成されるもので
ある。従って、前述の多層配線メタル構造のものと同様
に層間リーク等の故障、不良がヒロックにより生ずる問
題点を有するものであった。
In other words, in a multilayer wiring metal structure, one layer metal/
Interlayer leakage due to hillocks in interlayer films/two-layer metals has had a negative impact on device yield and reliability. In addition, large-area devices, such as sensor drive TPTs, liquid crystal panels, and EL panel drive TPTs, are commonly completed by forming a device on the upper layer after forming a thin film transistor section. be. Therefore, similar to the multilayer wiring metal structure described above, there are problems in that failures and defects such as interlayer leakage occur due to hillocks.

このようなヒロック発生の防止対策としてはAn合金、
すなわちAlに数%のSi、Cu。
As measures to prevent the occurrence of such hillocks, An alloy,
That is, several percent of Si and Cu are added to Al.

T x + M g等を合金化したものをマグネトロン
スパッタ法により形成してAl合金膜を得る方法が知ら
れている。例えば、J 、 Vac、 Sci、Tec
hnol、A5 (4)、July/Aug1987゜
” 5ubstrate Tell1perature
 Dependence ofHillock、 Gr
ain、and Crystal○rientatio
nin 5puttered A 12−alloy 
Films” 、これは合金成分であるAlとは異種の
原子はAlグレインの粒界に偏在し、プロセス上の熱履
歴でAlが再結晶化するときに、例えば合金原子がCU
ならばCu A Q、の金属間化合物を晶出し粒界成長
を妨げ、結果としてヒロック防止に役立っている。
A method is known in which an Al alloy film is obtained by forming an alloy of T x + M g or the like by magnetron sputtering. For example, J, Vac, Sci, Tec
hnol, A5 (4), July/Aug1987゜” 5ubstrate Tell1perature
Dependence of Hillock, Gr.
ain, and Crystal○rientatio
nin 5 puttered A 12-alloy
Atoms of a different type than Al, which is an alloy component, are unevenly distributed at the grain boundaries of Al grains, and when Al recrystallizes due to the thermal history of the process, for example, alloy atoms
In this case, the intermetallic compound of Cu A Q is crystallized and grain boundary growth is hindered, and as a result, it helps prevent hillocks.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、Al合金膜を配線材料として使用する場
合、次のような問題点を有する。すなわち、コンタクト
抵抗が上昇すること、エツチング工程でエツチング残さ
が生ずること、アフターコロ−ジョンが生じやすく信頼
性が悪くなることである。さらに、スパッタ法による合
金膜はストレスマイクレージョンによりスリット状のク
ラックを生じやす(、配線の断線故障を生ずる。これが
大面積薄膜トランジスタではさらに深刻な問題となる。
However, when using an Al alloy film as a wiring material, there are the following problems. That is, contact resistance increases, etching residue is produced in the etching process, and after-corrosion tends to occur, resulting in poor reliability. Furthermore, alloy films produced by sputtering are susceptible to slit-like cracks due to stress micro-crash (causing disconnection of interconnects), which becomes an even more serious problem in large-area thin film transistors.

そこで、本発明は配線材料としてAlまたはΔα合金を
使用した場合の熱履歴によるヒロック発生を防止し、プ
ロセスの歩留りおよび信頼性を向上させ得、上記した問
題点を解消した半導体装置のAl配線を提供することを
目的とするものである。
Therefore, the present invention can prevent the occurrence of hillocks due to thermal history when Al or Δα alloy is used as a wiring material, improve process yield and reliability, and provide Al wiring for semiconductor devices that solves the above-mentioned problems. The purpose is to provide

〔問題点を解消するための手段〕[Means to resolve the problem]

本発明では上記課題を達成するために、半導体装置内の
AlおよびAn合金配線の最大AlQ線幅Wが、該へΩ
蒲膵が真空蒸着法で形成された場合のAfl平均クレー
ンサイズをd  (ev)とすると、W≦5Xd (e
v)の範囲とし、該Al薄膜がスパッタリング法で形成
された場合のAlQ均クレーンサイズをd(sp)とす
るとW≦50Xd(sp)の範囲とされたものとされる
In the present invention, in order to achieve the above object, the maximum AlQ line width W of Al and An alloy wiring in a semiconductor device is
If the Afl average crane size when the pancreas is formed by vacuum deposition method is d (ev), then W≦5Xd (e
v), and if the AlQ average crane size when the Al thin film is formed by sputtering is d (sp), then W≦50Xd (sp).

このように、本発明では半導体装置内のAlおよびAl
合金膜の配線幅をAlQ均クレーンサイズにより規制す
るものである。すなわち。
In this way, in the present invention, Al and Al in the semiconductor device
The wiring width of the alloy film is regulated by the AlQ average crane size. Namely.

AlまたはAlQ金薄膜を真空蒸着法で製膜する場合、
そのAl平平均クイインサイズd  (eV)とすると
、最大配線幅Wは、W≦5Xd(e v)の範囲、好ま
しくはWS2.8Xd  (eV)の範囲でデザインす
る。また、AlまたはAlQ金薄膜をスパッタ法で製膜
する場合、そのAlQ均クレーンサイズをd(sp)と
すると、WはW≦50Xd (sp)の範囲、好ましく
はW≦20×d(sp)の範囲でデザインする。
When forming an Al or AlQ gold thin film by vacuum evaporation method,
Assuming that the Al average queen size is d (eV), the maximum wiring width W is designed in the range of W≦5Xd (eV), preferably in the range of WS2.8Xd (eV). In addition, when forming an Al or AlQ gold thin film by sputtering, and assuming that the AlQ average crane size is d (sp), W is in the range of W≦50×d (sp), preferably W≦20×d (sp). Design within the range of.

このことは、膜のもっている歪の絶対量およびヒロック
発生の活性点となるグレイン粒界の絶対量を線幅で限定
することによりヒロック発生を防止するものである。
This prevents the occurrence of hillocks by limiting the absolute amount of strain in the film and the absolute amount of grain boundaries, which are active sites for hillock generation, by line width.

半導体装置内の電源ライン等の大電流が流れる部分は、
先のAfl最大配線幅を利用して複数本化にデザインで
きる。Al配線は電流密度10’ A / cd以下に
なるようにデザインされるが、これでは先のΔQ最最大
配置幅上り広くなってしまう。この場合にはW以下の幅
を有する配線を複数本化することで解決する。
Parts where large currents flow, such as power lines in semiconductor devices,
It is possible to design multiple wires by using the Afl maximum wiring width mentioned above. The Al wiring is designed to have a current density of 10' A/cd or less, but this increases the maximum arrangement width of ΔQ mentioned above. In this case, the problem can be solved by using a plurality of wirings each having a width of W or less.

次に実施例を示す。Next, examples will be shown.

実施例 真空蒸着法でAl膜を基板温度、室温(25℃)、10
0℃、200℃で製膜し、マグネットロンスパッタ法で
Al膜を基板温度、室@(25℃)、200℃。
Example: Al film was deposited by vacuum evaporation method at substrate temperature, room temperature (25°C), 10
The film was formed at 0°C and 200°C, and the Al film was deposited using magnetron sputtering at the substrate temperature in a room @ (25°C) and 200°C.

400℃で製膜し、同じくマクネトロンスパッタ法でA
 Q−0,5Ut%Cu合金膜を基板温度、室温(25
℃)、200℃、400℃で製膜した。
The film was formed at 400°C and A
Q-0.5 Ut% Cu alloy film was deposited at substrate temperature and room temperature (25
℃), 200°C, and 400°C.

その後、配線幅を2μm、5μm、10μm、20μm
に、そして長さはそれぞれ3000μmにフォトリソグ
ラフィーエツチングでパターニングし、450℃、60
分間、N2雰囲気中でアニールし、ヒロック密度および
サイズ(直径)を光学顕微鏡から求め、クレーンサイズ
はS E M (Scanning Electron
 Microscopy)像から求めた。
After that, the wiring width was changed to 2 μm, 5 μm, 10 μm, and 20 μm.
and patterned by photolithography etching to a length of 3000 μm, and heated at 450°C and 60°C.
The hillock density and size (diameter) were determined using an optical microscope, and the crane size was determined using an SEM (Scanning Electron
It was determined from microscopic images.

これらのうちヒロック密度を第1図に、クレーンサイズ
を第2図にそれぞれ基板温度との関係で示す。これら、
第1図および第2図において、それぞれ(a)は真空蒸
着法によりAlを、(b)はマグネトロンスパッタ法に
よりAlを。
Among these, the hillock density is shown in FIG. 1, and the crane size is shown in FIG. 2 in relation to the substrate temperature. these,
In FIGS. 1 and 2, (a) shows Al by vacuum evaporation, and (b) shows Al by magnetron sputtering.

そして(C)はマクネトロンスパッタ法によりA Q−
0,5wt%Cuを製膜した場合を示す。そして、第1
図における丸印は配線幅20μmの場合を、四角印は配
線幅lOμmの場合を示す。
And (C) is AQ- by the Macnetron sputtering method.
The case where 0.5wt% Cu was formed into a film is shown. And the first
In the figure, circles indicate the case where the wiring width is 20 μm, and square marks indicate the case where the wiring width is 10 μm.

これら第1図および第2図より、クレーンサイズが大き
い程、ヒロック密度は小さいことがわかる。また、どの
サンプルも5μm以下の配線幅ではヒロックが認められ
なかった。
From these FIGS. 1 and 2, it can be seen that the larger the crane size, the smaller the hillock density. Furthermore, no hillock was observed in any of the samples with a wiring width of 5 μm or less.

〔発明の作用・効果〕[Action/effect of the invention]

以上のように本発明では、最大配線幅Wを真空蒸着法お
よびスパッタ法で製作する場合、それぞれW≦50×d
  (evンおよびW≦50Xd(s p)で規定する
ため、Afl配線におけるヒロックが完全に防止され、
プロセス加工上の歩留りが向上し、さらに半導体装置の
信頼性も向上する。
As described above, in the present invention, when the maximum wiring width W is manufactured by vacuum evaporation method and sputtering method, W≦50×d
(even and W≦50Xd(sp), so hillocks in Afl wiring are completely prevented,
Process yields are improved, and the reliability of semiconductor devices is also improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は真空蒸着法およびマク不)−ロンスパッタ法に
てAlおよびAl合金を製膜した場合における基板温度
とヒロック密度の関係図である。 第2図は真空蒸着法およびマグネトロンスパッタ法にて
AlおよびAl合金を製膜した場合における基板温度と
クレーンサイズの関係図である。
FIG. 1 is a diagram showing the relationship between substrate temperature and hillock density when Al and Al alloy are formed into films by vacuum evaporation and Macron sputtering. FIG. 2 is a diagram showing the relationship between substrate temperature and crane size when Al and Al alloy are formed into films by vacuum evaporation and magnetron sputtering.

Claims (1)

【特許請求の範囲】[Claims] 1、半導体装置内のAlおよびAl合金配線の最大Al
配線幅Wが、該Al薄膜が真空蒸着法で形成された場合
のAl平均クレーンサイズをd(ev)とすると、W≦
5×d(ev)の範囲とし、該Al薄膜がスパッタリン
グ法で形成された場合のAl平均クレーンサイズをd(
sp)とするとW≦50Xd(sp)の範囲とされたこ
とを特徴とする半導体装置のAl配線。
1. Maximum Al of Al and Al alloy wiring in semiconductor devices
If the wiring width W is the average crane size of Al when the Al thin film is formed by vacuum evaporation method, then W≦
5 x d(ev), and the average Al crane size when the Al thin film is formed by sputtering method is d(
An Al wiring for a semiconductor device, characterized in that, where W≦50Xd(sp), the range is W≦50Xd(sp).
JP16524988A 1988-07-01 1988-07-01 Al wiring part in semiconductor device Pending JPH0215631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16524988A JPH0215631A (en) 1988-07-01 1988-07-01 Al wiring part in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16524988A JPH0215631A (en) 1988-07-01 1988-07-01 Al wiring part in semiconductor device

Publications (1)

Publication Number Publication Date
JPH0215631A true JPH0215631A (en) 1990-01-19

Family

ID=15808716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16524988A Pending JPH0215631A (en) 1988-07-01 1988-07-01 Al wiring part in semiconductor device

Country Status (1)

Country Link
JP (1) JPH0215631A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320024A (en) * 1991-03-20 1992-11-10 Samsung Electron Co Ltd Manufacture of semiconductor device
JP2009010052A (en) * 2007-06-26 2009-01-15 Kobe Steel Ltd Method of manufacturing display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320024A (en) * 1991-03-20 1992-11-10 Samsung Electron Co Ltd Manufacture of semiconductor device
JP2009010052A (en) * 2007-06-26 2009-01-15 Kobe Steel Ltd Method of manufacturing display device

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