JPH02155268A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve integration density by incorporating a special functional cell group region in addition to a basic cell group in an inner functional cell region. CONSTITUTION:This circuit is a gate array type semiconductor integrated circuit having the following regions: peripheral buffer regions 2 which are aligned at the peripheral part of a semiconductor chip 1; and an inner cell region 3 which is surrounded with said peripheral buffer regions 2. The inner functional cell region 3 incorporates the following regions: a basic cell group region 4a wherein basic cells 4 are aligned in an array pattern; and a special cell group region 5 wherein functional cells for a RAM which are different from the basic cell 4 are aligned in order to form the RAM. The functional cells constituting the RAM can be realized in area less than 1/6 of the area of the basic cells 4. The integration density of the entire RAM is 1/6 X word number X bit number. Therefore, the more the word number and the bit number are increased, the larger the difference in integration densities between this RAM and a conventional device becomes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is utilized for pattern layout of a gate array type semiconductor integrated circuit.

The present invention relates to gate array type semiconductor integrated circuits, and in particular to ROM (read only memory), RAM (
The present invention relates to semiconductor integrated circuits including special function cells such as random access memory (random access memory) and PLA (programmable logic array).

〔overview〕

The present invention provides that in a gate array type semiconductor integrated circuit, a ROMS is
The degree of integration is improved by providing a special functional cell group area in which functional cells different from the basic cells constituting specific circuits such as RAM and PLA are arranged.

[Conventional technology]

Conventionally, this type of gate array type semiconductor integrated circuit, as shown in FIG. 3, has been constructed of basic cells 4 that implement special function cells such as ROM, RAM, and PLA to form logic circuits. In FIG. 3, 1 is a semiconductor chip, 2 is a peripheral buffer region, 3 is an internal functional cell region, and 4a is a basic cell group region.

[Problem that the invention seeks to solve]

In the conventional gate array type semiconductor integrated circuit described above, the basic cell 4 constitutes special function cells such as ROM, RAM, and PLA, so it has the disadvantage that the degree of integration is significantly lower than that of optimized RAM, etc. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array type semiconductor integrated circuit which improves the degree of integration by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a gate array type semiconductor integrated circuit comprising a peripheral buffer region arranged around the periphery of a semiconductor chip and an internal functional cell region surrounded by the peripheral buffer region, in which the internal functional cell region basically It is characterized by comprising a basic cell group area in which cells are arranged in an array, and a special functional cell group area in which functional cells different from the basic cells are arranged to constitute at least one specified circuit. do.

Further, in the present invention, the basic cell group region may include a wiring region having a height equal to or less than two times the diffusion region of the basic cell.

[Effect]

In the special function cell group area, for example, a RAM is configured using function cells with an appropriate configuration.

Incidentally, the area of the functional cells constituting the RAM is extremely smaller than the basic cell, for example, 1/6 of the size.

Therefore, the required chip area is smaller than when the RAM is configured using the basic cells, and the degree of integration can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic pattern layout diagram showing a first embodiment of the present invention.

This embodiment is a gate array type semiconductor integrated circuit including a peripheral buffer region 2 arranged around the periphery of a semiconductor chip 1 and an internal functional cell region 3 surrounded by the peripheral buffer region 2. The functional cell area 3 includes a basic cell group area 4a in which basic cells 4 are arranged in an array, and an RA
In order to configure M, a special function cell group area 5 is included in which RAM function cells different from the basic cells 4 are arranged.

The feature of the present invention is that, in FIG. 1, a special function cell group area 5 constituting the RAM is provided.

In this embodiment, the functional cells constituting the RAM can be realized with an area less than 176 of the basic cell 4, and the RAM as a whole has a degree of integration of 1/6 x the number of words x the number of bits. Therefore, as the number of words and bits increases, the difference in degree of integration from the conventional example becomes larger.

FIG. 2 is a pattern layout diagram showing the main part of a second embodiment of the present invention, and shows an internal functional cell area.

The second embodiment has four special function cell group regions 5a to 5d.
are arranged in the internal functional cell area 3, and the basic cell group area 4a fills in the space between them. Here, the special function cell group areas 5a' to 5b s5C and 5d are provided with ROM, RAM, using function cells having shapes appropriate for the respective configured circuits.

PLA and hard macro are configured.

The feature of the present invention is that, in FIG. 2, special function cell group regions 5a to 5d are provided.

According to the second embodiment, the degree of integration is significantly improved and the chip size is reduced compared to the case where the random logic is normally configured with one rectangular block.

In the first and second embodiments, the basic cell group area includes a wiring area with a height less than or equal to the diffusion area of the basic cell 4, so that efficient wiring can be achieved without taking up a large wiring area. It can be carried out.

〔Effect of the invention〕

As explained above, the present invention has the effect of improving the degree of integration by including a special function cell group area within the internal function cell area, separate from the basic cell group area.

[Brief explanation of the drawing]

FIG. 1 is a schematic pattern layout diagram showing a first embodiment of the present invention. FIG. 2 is a schematic pattern layout diagram showing the main parts of a second embodiment of the present invention. FIG. 3 is a schematic pattern layout diagram showing a conventional example. 1... Semiconductor chip, 2... Peripheral buffer area, 3
...Internal functional cell area, 4...Basic cell, 4a...
- Basic cell group area, 5.5a to 5d...Special function cell group area. Agent Patent Attorney Nao Takashi Ide Second Example

Claims (1)

[Scope of Claims] 1. In a gate array type semiconductor integrated circuit comprising a peripheral buffer region arranged around the periphery of a semiconductor chip and an internal functional cell region surrounded by the peripheral buffer region, the internal functional cell The area includes a basic cell group area in which basic cells are arranged in an array, and a special function cell group area in which functional cells different from the basic cells are arranged to configure at least one specified circuit. A semiconductor integrated circuit characterized by: