JPH02153765A - Image forming apparatus - Google Patents

Abstract

PURPOSE:To simplify the constitution of a video interface by providing an input means for inputting divided image data, an assembling means for assembling said divided data into the original one image data and a recording means for recording a multigradation image according to said one image data. CONSTITUTION:For example, a controller divides 8-bit image data VD0 - VD7 into four higher rank bits and four lower rank bits to successively send out the same. These data are inputted to a printer engine as 4-bit image data VID EO. A demultiplexer 3 distributes these image data to memories 1, 2 to be alternately written therein on the basis of a control clock CCLK. From the memory not on the writing side, the reading due to an image clock signal VCLK is performed and image data D1, D2 are successively latched by a latch circuit 4 to be converted to 8-bit image data. Image data VD is inputted to a pulse width modulation circuit 5 to enter a comparator 12 from a D/A converter 10 and a signal LD having the pulse width corresponding to image density is formed to perform printing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus that inputs multi-valued image data and forms a multi-tone image.

[Prior Art] FIG. 7 is a diagram illustrating an image data transfer method between a printer controller and a printer engine in a conventional image forming apparatus. In FIG. A signal specifying the writing timing) is sent to the printer controller 101. On the other hand, the printer controller 101
The clock generation circuit 103 on the side receives this horizontal synchronizing signal H3Y.
Upon receiving the NC, a controller clock signal CCLK is generated in synchronization with this, and image data is sequentially read out from the image memory 102 in synchronization with the CCLK signal to generate an image signal V.
It is sent to the printer engine 104 as IDEO.

[Problems to be Solved by the Invention] However, as the number of bits N of one image data increases, the wiring between the controller and the engine and the associated interface circuit become complicated.

Further, if the image data is transferred serially, problems such as wiring can be solved, but on the other hand, the transfer speed becomes N times that of parallel transfer, which increases the cost in addition to the technical difficulty of high-speed processing.

[Problems to be Solved by the Invention] The present invention eliminates the drawbacks of the prior art described above, and its purpose is to provide an image forming system that has a simple configuration related to the image data interface and can perform high-speed recording of images. The goal is to provide equipment.

[Means for Solving the Problems] In order to achieve the above object, the image forming apparatus of the present invention has the following features:
The present invention includes an input means for inputting divided image data, an assembling means for assembling the input plurality of divided data into original one image data, and a recording means for recording a multi-tone image according to the assembled one image data. The outline is as follows.

Preferably, one aspect of the recording means is to record pixels corresponding to the one image data using a number of recording pixel areas equal to the number of divided data constituting the original one image data.

Further, in order to achieve the above object, the image forming apparatus of the present invention includes an input means for inputting divided image data, an assembling means for assembling the inputted plurality of divided data into one original image data, and an assembling means for assembling the inputted plurality of divided data into one original image data. an interpolated data forming means for obtaining interpolated data based on the assembled one image data and the one image data assembled at a previous point in time, and a recording means for recording a multi-gradation image according to the assembled one image data and the obtained interpolated data. This is the summary.

[Operation] In the above configuration, the input means inputs the divided image data. That is, the zero assembling means, which requires a small number of image data transfer lines, assembles the plurality of input divided data into one original image data. The recording means records a multi-tone image according to the assembled single image data.

Preferably, the recording means records pixels corresponding to the one image data using a number of recording pixel areas equal to the number of divided data constituting the original one image data. Therefore,
As the number of bits (number of gradations) of one image data increases, the recording pixel area used to form one pixel also increases, and the number of recording gradations also increases.

In the above configuration, the input means inputs the divided image data, and the assembling means assembles the plurality of input divided data into one original image data. The interpolation data forming means obtains interpolation data based on the assembled one image data and the one image data assembled at a previous point in time. The recording means records a multi-gradation image according to the assembled single image data and the obtained interpolation data. Therefore, even if the recording interval of the original image data is doubled, for example, the pixels between them are interpolated, so that the entire recording pixel area is effectively recorded.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram of a printer engine of an image forming apparatus according to a first embodiment. In FIG. When VIDEO is input, memory 1 for one pixel is stored every cycle of controller clock signal CCLK.
Or divide into 2. 4 is a latch circuit, and memory l
and 2, each of the 4-bit image data DI- and D2 are combined to form 8-bit image data VD. On the other hand, 8 is a phase synchronization oscillation circuit, and the controller clock signal CC is synchronized with the rising edge of the horizontal synchronization signal H3YNC.
A video clock signal VCLK having the same period as LK is generated. 6 is a device control circuit, which controls the allocation of the demultiplexer 3 according to the controller clock signal CCLK, and controls the data writing of the memories 1.2, and 7 is a device control circuit, which controls the memory 1.2 according to the image clock signal VCLK. 2. Performs data succession control.

Reference numeral 9 denotes a frequency dividing circuit, which generates a clock signal HvCLK obtained by dividing the frequency of the image clock signal VCLK by 1/2.

For example, a controller (not shown) generates one 8-bit image data for each two pixel (dot) area in the main scanning direction according to the resolution of the printer engine.For example, if the resolution of the printer engine is 300 DPI (dots/inch).
In this case, the density of image data generated by the controller in the main scanning direction is 150 DPI. The controller sends such 8-bit image data VDO to VDT to the upper level.

The lower 4 bits are divided into 4 bits each, and this is synchronized with the controller clock signal CCLK.The upper 4 bits of image data VD7 to VD4 are used for the first CCLK and the next CCLK.
Then, at the next CCLK, the lower 4 bits of image data VD3 to VDO, and then at the next CCLK, the upper 4 bits of the next image data VD7
-VD4, and further, in the next CCLK, the lower 4 bits of the next image data, VD3-VDO, are sequentially transmitted. These are 4
The data is input to the printer engine as bit image data VIDEO. The demultiplexer 3 converts the input image data VIDEO into the upper 4 bits of image data VD7 to VD.
4 is the lower 4 bits of image data VD3 to V in memory l.
The DO is allocated to memory 2 and written to memories 1 and 2 alternately by controller clock ccLK.

On the other hand, reading from the memory 1.2 that is not on the writing side is performed using the image clock signal VCLK. Read image data DI.

D2 is sequentially latched by the latch circuit 4 and converted into 8-bit image data.

FIG. 2 is a circuit diagram showing details of the latch circuit 4 of the embodiment. In FIG. 0, 13 is a 4-bit latch, and 14 is an 8-bit latch. Image data D read from memory l
1 is latched in latch 13, and 1 image clock signal VC
Next, the read timing of memory 2 is delayed by one clock than the read timing of memory l, so the image data in latch 13 and the image data from memory 2 are synchronized. is taken and latched into the latch 14 by the clock signal station VCLK. That is, the image data sent from the controller by being divided into 4 bits each of upper and lower bits is assembled here to become 8-bit image data VDO to VDT.

Returning to FIG. 1, the image data VD is input to the pulse width modulation circuit 5, converted to an analog signal by the D/A converter 10, and input to one terminal of the comparator 12. On the other hand, a triangular wave signal generated by the triangular wave generating circuit 11 is input to a child terminal of the comparator 12 . The comparator 12 generates a signal LD having a pulse width corresponding to the image density by comparing these signals, and printing is performed using the signal LD according to a well-known electrophotographic process.

FIG. 3 is an operation timing chart of the configuration shown in FIG. 1. In FIG. 0, IA, 2A, 3A, .
IB, 2B, 3B... are the above-mentioned IA, 2A, 3A...
The lower 4 bits correspond to the lower 4 bits. Further, the symbol rWJ attached to the memory signal column indicates a write operation, and the symbol rRJ
8 bits (256 gradations) can be expressed using 2 bits of the printer as a unit by an operation of 0 or more indicating a read operation. By doing this, the gradation expression ability per dot of the printer can always be maximized.

Incidentally, in the above embodiment, an example was shown in which 8-bit image data is divided into 4 bits and transferred, but the present invention is not limited to this. In addition, 4-bit image data is also available.

It may be divided into lower 2 bits each, or 6-bit image data may be divided into 3 parts each into upper, middle, and lower 2 bits. In this case, iterator circuit 9 should be made into a % frequency divider circuit. .

Further, in the above-described embodiment, an example in which pulse width modulation is performed is shown, but the present invention is not limited to this. For example, a method in which the amount of light is changed by varying the laser drive current may also be used.

Furthermore, although the above-described embodiments have described a laser beam printer, the present invention is not limited to this. It may also be applied to other LED printers and the like.

[Second Embodiment] The second embodiment relates to interpolation of image data in the main scanning direction. In the first embodiment, two bits on the printer engine side are used for one input image data. Therefore, even with a 300DPI engine, the resolution in the main scanning direction is 150DPI.

FIG. 4 is a block diagram of the printer engine of the image forming apparatus according to the second embodiment. Components that are the same as those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

In the figure, reference numeral 15 denotes an interpolation circuit, which interpolates the input image data VD in the main scanning direction.For simplicity of explanation, a controller (not shown) inputs 4-bit image data VD.
It is assumed that DO to VD3 are divided into upper and lower 2 bits and sent.

FIG. 5 is a circuit diagram of the interpolation circuit of the second embodiment. In FIG. 0, 16 is a flip-flop, and the clock signal [
The most significant bit VD3 of the 0 image data VD, which is obtained by dividing VCLK by two and outputting the clock signal %VCLK, is alternately latched in latches 21 and 22 by the clock signal IVcLK.

Similarly, the remaining bits VD2-VDO of the image data are alternately latched into two latches in each of the latch circuits 18-20, respectively. Therefore, the latch circuits 17 to 20 store the current image data and the immediately previous image data. 23 is a full adder which adds the contents of two consecutive image data. By taking the upper 4 bits from the 5 bits of the addition result, the addition result is halved, and as a result, the average value of two consecutive image data is determined.

Reference numeral 24 denotes a select circuit, which outputs image data at the previous time, intermediate average value data, and image data at the present time by controlling switching terminals 25 to 28. As a result, image data and interpolation data are assigned to the two dots on the printer engine side, respectively, and as a result, the resolution in the main scanning direction becomes 300 DPI.

FIG. 6 is a timing chart of interpolation processing in the second embodiment.
, j, k..., average value data is formed between each image data and inserted between each image data.

In the second embodiment, the image data is 4 bits, but the invention is not limited to this. Alternatively, it may be 6 bits or 8 bits, for example.

[Effects of the Invention] As described above, according to the present invention, the configuration of a so-called video interface can be simplified and the interface can be made easier.

[Brief explanation of the drawing]

1 is a block configuration diagram of the printer engine of the image forming apparatus of the first embodiment, FIG. 2 is a circuit diagram showing details of the latch circuit 4 of the embodiment, and FIG. 3 is an operation timing chart of the configuration of FIG. 1. , FIG. 4 is a block diagram of the printer engine of the image forming apparatus of the second embodiment, FIG. 5 is a circuit diagram of the interpolation circuit of the second embodiment, and FIG. 6 is a block diagram of the printer engine of the image forming apparatus of the second embodiment.
Timing Chart of Interpolation Processing in Embodiment FIG. 7 is a diagram illustrating an image data transfer method between a printer controller and a printer engine in a conventional image forming apparatus. In the figure, 17... is a latch circuit. Figure 2 +01 No. 71

Claims (3)

[Claims] (1) An input means for inputting divided image data; an assembling means for assembling the input plurality of divided data into original one image data; and recording a multi-tone image according to the assembled one image data. An image forming apparatus comprising a recording means. (2) The recording means uses a number of recording pixel areas equal to the number of divided data constituting one original image data.
2. The image forming apparatus according to claim 1, wherein pixels corresponding to image data are recorded. (3) an input means for inputting divided image data; an assembling means for assembling the plurality of inputted divided data into original one image data; and one image data assembled at a point preceding the assembled one image data. An image forming apparatus comprising: interpolation data forming means for obtaining interpolation data based on the above; and recording means for recording a multi-tone image according to the assembled single image data and the obtained interpolation data.