JPH0215298A - Musical sound synthesizing device - Google Patents

Abstract

PURPOSE:To simplify the constitution of the musical sound synthesizing device which changes in timbre with time by controlling the number of words of delay data corresponding to musical sound pitch. CONSTITUTION:A musical sound waveform from an initial waveform generator 1 is circulated in a digital filter 5 of each cycle and varied with time. The musical waveform circulated in the filter 5 is written in a first-in first-out FIFO 3 through a shift register 4 and then read out and outputted to a sound system 6. At this time, clock pulses phiO of a clock pulse generator 80 are passed intermittently through a gate 83 to generate master clock pulses phiG, which are frequency-divided by the number of bits per word of waveform memory ROMs 11-13 and the register 4 and inputted to an address counter 83 so as to control the delay time of the register 4 corresponding to the musical sound pitch. Consequently, the address variation and pulses phiG are synchronized with each other. A musical sound which varies in timbre with time is generated with the simple constitution.

Description

[Detailed Description of the Invention] The present invention relates to a musical tone synthesizer that generates musical tones whose timbre changes over time, and in particular, by controlling the number of words of delay data, musical tone pitch can be controlled with a simple configuration. It is something.

Regarding electronic musical instruments that generate musical tones whose amplitude changes over time and whose timbre (waveform) also changes at the same time, the Applicant of the present application filed an application on December 16, 1975.
It is explained in detail in Patent Application No. 149148 (Japanese Unexamined Patent Publication No. 73721/1989) entitled "Electronic Musical Instrument" (hereinafter referred to as "Hikari Application"). In the electronic musical instrument shown in this earlier application, the musical waveform generating means has a data circulation path in which a shift register and a digital filter are connected in a closed loop, and the digital waveform data is circulated through the data circulation path. data is extracted as musical waveform data. In order to control the delay time of the delay circuit consisting of a shift register in accordance with the tone pitch, the frequency of the clock pulse of the shift register is controlled in accordance with the tone pitch.

However, it is not easy to variably control the frequency of the clock pulse in response to various pitches of musical tones, resulting in the disadvantage of complicating the structure.

An object of the present invention is to enable tone pitch control with a simple configuration.

This invention has a data circulation path in which a data delay means and a digital filter are connected in a closed loop, and by circulating waveform data through this data circulation path, the data being circulated is extracted as musical waveform data. The musical tone synthesizer is provided with a pitch instruction means for instructing a musical tone pitch, and a word number control means for controlling the number of words of delay data in the data delay means in response to the musical tone pitch instructed by the pitch instruction means. The present invention is characterized in that musical waveform data having a musical pitch is taken out from a data circulation path.

According to the configuration of the present invention, the frequency of the tarokku pulse for delay control may be constant even if the pitch of the musical tone varies;
This has the advantage of simplifying the configuration.

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing an electronic musical instrument according to an embodiment of the present invention. In the figure, IO is a common information transmission path, and 20 is a CPU. The CPU referred to in this specification is equipped with a control circuit, an arithmetic circuit, and a register, and together with a memory device located outside the CPU, general-purpose data that can process data input from the input device of a terminal and output it to the output device of the terminal. means a device equipped with processing functions. Further, a microprocessor is assumed to be used as a preferred design example. Data processing by the CPU 20 is determined by programs stored in the memory device 22 and control signals given from the CPU control panel section 24.

Therefore, by changing these appropriately, the data processing method can be changed freely.

In FIG. 1, 30 is a keyboard section, 32 is a tone control panel section,
34 is a musical tone generator, 36 is a display panel, 38 is a modulation/demodulation circuit (MODEM) for a communication line, and 39 is a timer for supplying time information for data processing. What should be noted here is that in conventional electronic musical instruments, the keyboard section, timbre control panel section, musical tone generation section, etc. are interconnected by dedicated wiring, but in this invention, instead of these wiring, By providing a common information transmission path 10, it is possible to reduce the number of wiring lines and make the system multifunctional.

Note that 21.25.31.33.35.37 is the information transmission path 10 common to the CPU 20, CPU control panel section 24, keyboard section 30, tone control panel section 32, musical tone generation section 34, and display panel section 36, respectively. The operations of these circuits will be described together with the operations of the CPU and each terminal device.

In the apparatus shown in FIG. 1, various signals output between each device via a common information transmission path 10 are
Classified as shown in the table.

In Table 1, the signal SI2 includes control signals for writing and reading given from the CPU 20 to the memory device 22, and the signal 5l11 is generated by the CPU 20 based on signals S3+ and S41, which will be described later, and is generated by the musical tone generator. The signal S21 includes signals such as instructions and data sent to the CPU 20, and the signal S31 includes keys pressed in response to key operations on the keyboard section 30. It includes a key on/off signal and a key data signal as information, the signal S41 includes a tone data signal as tone selection information generated in response to a tone selection operation on the tone control panel 32, and the signal S32+342 is a memory signal. Signal S36 includes key on/off signals and key data signals; Signal 546 includes tone data signals; Signal S5+ includes program selection, CPU direct control, etc. signals.

Here, signals 33B and 346 are similar to signals S3+ and S41, respectively, but signals S31 and 541
Rather than being supplied to the CPU 20 as in the example shown in FIG.

Signals S17+ 37+ 847 are each signal S1
It is the same as or similar to 6°336+348.

Further, the signals S 18+ 338+ 3411 are signals for displaying the status of the CPU 20 and the terminal equipment (in this case, the keyboard section 30 and the tone control panel section 32), respectively. If the status of the appropriate event is displayed on the display panel 36, it will be convenient for control in the next stage.

In Table 1, the signal S 12+ 21+ 361 is a similar signal exchanged in computers that process office data or technical data, and is well known in the technical field, so we will explain it here. is omitted. Further, an external storage device, an external data processing device, etc. may be connected to the common information transmission path 10 shown in FIG. Signals may be sent and received between these devices and the devices shown in Table 1, but the parts related to external storage devices and external data processing devices are within the field of general computer technology. Since it is well known, its explanation will be omitted.

The format of these signals and the format of the common information transmission path determined according to the format can be freely selected by design. The signals shown in Table 1 can be divided into an address part, a data part, and an instruction part. If there are multiple units, such as a musical tone generator, they can be divided into a device address that specifies which one of them it is, and a data address that specifies which register in the device the input is to be input to.For example, a signal that includes all of these can be divided into It is also possible to transmit the data in a bit serial format and use the common information transmission path 10 as a single line transmission path. In such a case, interrupt priorities are determined for each device, and interrupts are controlled according to the priorities. In addition, the CPU 20 changes (selects) the stupid program that accepts and processes these interrupts.
Jumping, stopping, waiting, etc. Since these matters should be determined by design as to how to configure the electronic musical instrument of the present invention, their explanation will be omitted.

Next, the configuration of the musical tone generator 34 will be explained.

The signals to be input to the musical tone generator 34 from the common information transmission path IO are a timbre data signal, a key data signal, and a key on/off signal, that is, an envelope start signal and a release start signal. The fundamental frequency of the musical tone generated by the musical tone generator 34 is determined by the key data signal, the attack waveform is started by the envelope start signal, and the release waveform is started by the release start signal. The shapes of the attack waveform and release waveform, that is, the shape of the musical tone amplitude envelope and the musical sound waveform, are determined by the timbre data signal.

By the way, rather than generating similar musical sound waveforms throughout the entire sound generation period from the envelope start (the start of sound generation) to the release finish (the end of sound generation), the musical sound waveforms gradually change during the attack and release periods, and the harmonics of the sound waves change gradually during the attack and release periods. It is known that by changing the wave content rate, it is possible to obtain musical tones with preferable tones similar to those of musical instruments such as pianos, harps, and pianos. Since it is easy to change, it is most suitable for generating such musical tones.

FIG. 2 is a block diagram showing an example of the configuration of the musical tone generating section 34, and in the figure, the following signals (a) to (e) are applied to the musical tone generating section 34 from the outside. There is something.

(a) Key code indicating the turned-on key This key code contains an octave code OCC indicating the octave to which the turned-on key belongs, and a note code indicating the name of the note corresponding to the turned-on key among the 12 note names within the octave. The octave code oCC is stored in the register 800, and the note code NTC is stored in the register 500.

(b) Parameter code A1 for determining the initial waveform of musical tone. A2, A3 These codes A+, A2, A3 are stored in registers 140.150.11i0, respectively.

(c) Parameter codes P and Q for determining the characteristics of digital filter 5 These codes PQ are stored in registers 520540, respectively.

(d) Tone waveform switching signal S for switching the tone waveform from the initial waveform to the cyclic waveform. This signal S is a 1-bit signal and is stored in the register 21.

(e) Musical tone output enable signal E for enabling musical tone generation This signal E is a 1-bit signal and is stored in the register 71.

Block 1 surrounded by a dotted line represents the initial waveform generator, and the second
The example shown in the figure has memories 11, 12, and 13 storing different tone waveforms, multiplication circuits 14, 1516, and addition circuits 17, and includes multiplication parameter codes A, , A2, .
By changing A3, the initial waveform can be arbitrarily changed. Also, as a numerical example for convenience of explanation, memory 1
1.12.13, a 16-bit digital code (including positive and negative signs) representing the amplitude at each sample point obtained by dividing one period of a musical sound waveform into 1,024 equal parts is stored at an address in the phase order of the sample point. Suppose that it is a ROM (read-only memory).

2 is a selector, 3 is a first-in, first-out type memory (hereinafter abbreviated as FIFO memory), 4 is a shift register, and block 5 surrounded by a dotted line is a digital filter. The shift register 4 and the filter 5 are circuits for circulating the musical sound waveform output from the selector 2 through the filter 5 every cycle and gradually changing the musical sound waveform according to the characteristics of the filter 5. Details are given in the earlier application. This is what I explained.

In the embodiment shown in FIG. 2, the filter 5 includes a register 51,
It is a regression type one-stage digital filter composed of multiplication circuits 52, 54 and addition circuits 53, and the characteristics of the filter 5 can be changed by changing parameter codes P and Q. For example, by setting the value p of the parameter code P to p>O, low-order harmonics are hardly attenuated,
High-order overtones can be made to have a characteristic of rapidly attenuating over time, and can simulate the musical sounds of pianos, guitars, and the like. Further, by setting various values q of the parameter code Q, the gain and attenuation rate can be controlled, and the waveforms of the rising and falling edges of musical tones can be simulated.

Furthermore, by setting p=Q and q=1, it is possible to simulate the continuous waveform of a musical tone.

6 is a sound system including a D/A converter, an output amplifier, a speaker, etc.; 7 is a gate circuit for controlling the output of musical tone signals from the FIFO memory 3;

80 is a clock pulse generator, 81 is an AND gate, 8
2 is a frequency dividing circuit, 83 is an address counter, 85 is an address counter output connection control device, 86 is a flip-flop, 501 is a read clock pulse generator, 502 is an FI
A counter 503 is a counter for controlling the writing of the FO memory 3, and a counter 503 is a counter for controlling the reading of the FIFO memory 3.

The musical tone generator 34 shown in FIG. 2 is characterized by the fact that musical waveforms are written into the FIFO memory 3 at a constant clock speed, and are read out at a variable or locked speed within a range that does not exceed the writing clock speed, and that the octave code The object of the present invention is to include word number control means for changing the number of samples or the number of words in one period of a musical tone waveform by controlling the oCC.

The operation of the circuit shown in FIG. 2 will be explained below using numerical examples.

Table 2 shows specific examples of the chord structure of the octave code oCC, the octaves it represents, and the number of samples in one cycle of the musical sound waveform for each octave.

The clock pulse generator 80 in the table generates a clock pulse φ0 having a frequency of around 2 [MHz] (hereinafter abbreviated as 2 [MHz] for simplicity). This 2 [MHz] clock pulse φ. As will be described later, what passes through the gate 81 intermittently is the master clock pulse φ for the initial waveform generator 1, digital filter 5, and shift register 4. used as. Since ROM II, 12.13 and shift register 4 store 16 bits of data per word, the master clock pulse φ. is divided into 1/16 by the frequency dividing circuit 82 and input to the address counter 83. In this way, address change and master clock pulse φ. Which synchronization can be done.

The number of words in one cycle of the musical waveform must be changed in the shift register 4 according to Table 2, so for convenience, the shift register 4 uses a RAM (random access memory), which is stored in the ROM II.12.1
The capacity is the same as 3, < 1,024 words x 16 bits.

Note that the register 51 has a capacity of 1 word x 16 bits.

The address counter 83 has ten binary stages connected in cascade, and its output is connected by an address counter output connection control device 85 as shown in FIG.

In FIG. 3, ce + ca +...C' l +Co are the parallel outputs of the address counter 83 shown in order from MSB to LSB, and a9 + aa +... a l
+aO indicates the 10 bits of the address of the ROM1.12.13 and the write and read address of the RAM4 in order from MSB to LSB.

For example, if the octave code OCC is in logic r100J, only the lower 6 bits 05-co of 09-Co are output, and this is the upper 6 bits a9-a of a9-a0.
4, and "0°' is output to bits 83 and below. Therefore, each time the input pulse to the address counter 83 increases by one, the addresses of ROM11, 12.13 and RAM4 change by 16, and therefore, the address is not read out. address is 0,
1632, .

The FIFO memory 3 is a 64 word x 16 bit memory in which writing is performed intermittently and reading is performed continuously using a clock pulse having a lower frequency than the write clock pulse.
The generation frequency of is the third regardless of the octave code OCC.
As shown in the table. Note that the read clock pulse generator 501 uses a variable frequency dividing circuit in this embodiment, and receives the clock pulse φ from the relock pulse generator 80.

is frequency-divided in accordance with the note code NTC to generate 12 types of read clock pulses corresponding to 12 note names.

Table 3 The read clock pulse frequencies in Table 3 are all FIF
○Frequency 2 of the write clock pulse of memory 3 [MHz
The frequency is lower than ko/16=125 [KHz]. An example of the time relationship between writing and reading of the FIFO memory 3 is shown in FIG. A pulse waveform P 503 in FIG. 4 shows a change in the count of the readout control counter 503, and every time the count reaches number 0 (number 64), the flip-flop 86 outputs P from the counter 503. Set in response to N pulse. Then, the output Q of the flip-flop 86
The control signal Gaa becomes "1" and turns on the AND gate 81. This causes the master clock pulse φ and the address counter output connection control device 85.
Since the address signal is output from the selector 2, code data representing a musical tone waveform is output from the selector 2 and written into the FIFO memory 3. Pulse P 602 in FIG. 4 represents the output pulse from frequency divider circuit 82, and this output pulse is
It is supplied to the counter 502 for write control of the IFO memory 3.

Since the pulse frequency of P 503 is lower than that of P 502, when the first pulse of P 503 arrives at the FIFO memory 3, the first pulse of P s02
At least one word of data has already been written into the FIFO memory 3 by the pulse number. Therefore, FIFO
Reading of the memory 3 can be performed continuously. Thus, during the period when the signal Ga6 in FIG.
When the count of 2 reaches number 64 (number 0), flip-flop 86 receives P from counter 502. , F pulse. Then P. Writing to FIFO memory 3 is stopped until flip-flop 86 is set again by the N pulse, during which time only reading is performed.

In this way, writing to the FIFO memory 3 is interrupted every 64 words, and for example, in the octaves A1 to G1# in Table 2, A is written every 64/1,024 cycles of the musical sound waveform.
In the octave from 7 to G7#, the musical waveform is 1i4/16
Writing is interrupted every cycle, but in either case, reading is performed continuously to generate a musical sound waveform.

Also, for example, the frequency of the clock pulses generated by the read clock pulse generator 501 is the same < 28.16
Octave code OCC even in the case of 0 [KHz]
is logical rooOJ1. : At some point, the fundamental frequency of the musical sound waveform read from the FIFO memory 3 is 28.160 [
K Hz / 1,024 = 27.5 [Hz], and when the octave code OCC is in logic rllOJ, 28.160 [K Hz ] / 16 = 1.7
[io[Hz].

The digital code of the musical sound waveform outputted from the FIFO memory 3 is input to the sound system 6 via the gate circuit 7, where it is converted into an analog voltage, and, if necessary, various performance effects are added and the sound is produced. Since the sound system is well known, a description thereof will be omitted.

As is clear from the above description, the musical tone generator 34 of the embodiment shown in FIG.

Octave code OCC, parameter code A+, A
2, A3. By providing P and Q, it is possible to generate a musical tone having a desired timbre at the fundamental frequency corresponding to the pressed key. Furthermore, due to the nature of these data, note code NTC and octave code Occ are kept constant during musical sound generation, but it is common practice to change parameter codes P and Q as appropriate to form a preferred musical sound waveform in the attack and release parts. It's by design. Parameter code A 1. Although it is meaningless to change A2 and A3 after the selector 2 is switched, they may be changed as appropriate before the selector 2 is switched.

Data NTC and OCC are generally sent from the keyboard section 3o to a common information transmission path 1o. Any conventionally known circuit may be used to generate and send this data, one example of which is shown in FIG. In the same figure, 10.30.31
represent the same reference numerals and the same parts in FIG. 1, and the common information transmission path 1o is address bus A (101), data bus B (lo2), and control bus C (103).
It is divided into two parts.

In addition, in the design example of FIG. 5, the interface 31 has an octave code of 0CC as shown in Tables 2 and 3.
Although it has the capacity to detect the states of 12 types of note codes NTC, that is, 12×8=96 keys for 8 types, the case is shown in which 61 keys are mounted on the keyboard section 30.

The pulse generator 316 supplies the scanning clock pulse φ1 to the counter 312, and the pulse generator 316 and the counter 3
12, a decoder 311, an OR gate 313, a shift register 314, and a latch 315 constitute a key state detection device. The lowest four stages of the counter 312 have a hexadecimal connection, and the decoder 311 has a corresponding connection. Furthermore, the outputs of the decoder 311 other than those corresponding to the 61 keys can be omitted. With such a counter configuration, the lower 4 bits of the latch 315 directly represent the note code NTC, and the upper 3 bits directly represent the octave code OCC.

In the example shown in FIG. 5, the keys are connected in order of priority, and a voltage of logic "1°" is supplied from the terminal 301 only to the key with the highest priority among the keys that are turned on at the same time. When the count value of the counter 312 reaches the value corresponding to the key, a logic "1" pulse is output from the OR gate 313 via each AND gate. The shift register 314 is for delaying these pulses by one scan period, and the output of the AND gate 319 means that a pulse that was not present in the previous scan has been detected in the current scan. Therefore, pulse K represents the key-on point. N, which is the envelope start signal. Similarly, the output of the AND gate 320 is a pulse K representing the key-off point, since it means that the pulse that existed during the previous scan has disappeared in the current scan. F
P, that is, a release start signal. Output pulse K of AND gate 319. When the output of the counter 312 is input to the latch 315 at N, the output of the latch 315 becomes the note code NTC and the octave code OCC. The output of the latch 315 is read out through the gate 318 when a predetermined address signal arrives at the address decoder 317. Note that the gate 318 also has a control bus C.
A gate enable signal GE given from (103) is added.

An example of the configuration of the timer 39 is shown in FIG. In the timer shown in the figure, the readout control pulse Pso3 of the FIFO memory 3
(see FIGS. 2 and 4) is input to the frequency divider 386,
A selector 387 selects a predetermined bit of the frequency-divided output data of the frequency divider 386 using the data OCC,
Since the pulse of this selected bit is used to measure time, the unit of time measurement is 1 of the musical waveform.
It becomes a cycle. In FIG. 6, 388 is an address decoder, 389 is a counter, 390 is a comparator, and 391
392 and 393 are latches, 394.395.3 respectively
96 is an AND gate, which sends a data latch pulse to the corresponding latch 3!11.392.393, and outputs the data on the data bus B (102) to the latch corresponding to the output content of the address decoder 388 at that time. Enter. The latch 391 has an octave code O.
CC, the latch 392 receives the control signal of the counter 389, and the latch 393 receives time data t+, t2 . ts etc. are input, which will be explained in a later section.

When the data of the counter 389 and the data of the latch 393 match, the comparator 390 outputs P timer in FIG.
It outputs a pulse represented by , and interrupts the CPU 20, which will be explained in a later section.

Above, an example of signal usage in the terminal equipment has been explained with reference to FIG. 2, and an example of signal exchange between the common information transmission path 10 and the keyboard section 30 has been explained with reference to FIG.
0. The mechanism for transmitting and receiving signals between the memory device 22 and various terminal devices via a common information transmission path lO is well known in the technical field of electronic computers, and the electronic musical instrument shown in FIG. A similar signal exchange mechanism can also be used in the present invention, so a description thereof will be omitted.

Furthermore, since the interruption (interruption) from the terminal device to the CPU 20 and its processing are performed in the same way as in a general computer, a general explanation will be omitted.
For example, K in Figure 5. NK OFF pulse and 6th
FIG. 8 shows a flowchart for generating a musical tone having the waveform shown in FIG. 7 T6 by interrupting with the pulse Ptl□ in the figure.

The main program in the flowchart is a program that repeatedly performs scanning of the tone control panel 32, polling of the display panel 36, etc., as shown on the left end of FIG. 8, and it goes without saying that the program returns to the main program when the interrupt is completed. .

When interrupted by KOH, an address is sent to address decoder 317 (FIG. 5), and note code NTC and octave code OCC are read through gate 318. Next, state = 0 is set as the initial value, and C
P U 20 sends out parameter codes Al, A2, A3, note code NTC, octave code OCC, parameter codes P, Q (represented by P+, Q+ in FIG. 8) corresponding to state = 0, and also as signal S. sends out S=゛0°°, so the selector 2 inputs the output of the initial waveform generator 1 to the FIFO memory 3 during this period. Also, the time data t1 is sent to the latch 393.
(FIG. 6), a counter control signal is input to latch 392 to reset and enable counter 389 in response to counter reset signal CR and counter enable signal CE.

Next, a musical tone output enable signal E is sent to make the gate circuit 7 conductive, and the output of the FIFO memory 3 is supplied to the sound system 6. This is K. The interrupt by N ends and returns to the main program.

Next, when the counter 389 reaches a count value corresponding to the time data t1, the comparator 390 outputs a pulse P tlm
er outputs and an interrupt by P tlmar occurs. In the case of an interrupt by P timer, after determining which value the state is at, the state is advanced by 1, and when the state = 1, the signal S is set to S = "1°°,
Selector 2 stores the musical sound waveform that has circulated through filter 5 as FIFO.
The seventh parameter code is input to memory 3, and the parameter code P+ and Q+ input by the previous KON interrupt are input.
A waveform as shown in state 1 in the figure is generated. Further, the time data t2 is sent out and inputted to the latch 393, and the counter 389 is reset and enabled in the same way as before, and then the process returns to the main program.

Next, when the counter 389 reaches a count value corresponding to the time data t2, the comparator 390 outputs a pulse P tlm
ar is output and an interrupt is generated by Ptl□, 1 is added to the state and the state becomes 2, the corresponding parameter codes P and Q (represented by P2.Q2 in Figure 8) are sent out, and the A waveform shown in state 2 in FIG. 7 is generated. Also, disable timer 39 (
(counter 389 is disabled), an interrupt by P_tlmar will not occur as time passes.

After state = 2, an interrupt occurs due to K OFF, setting state = 3, sending out the corresponding parameter codes P and Q (represented by P3.Q3 in Figure 8), and changing to state 3 in Figure 7. Generates the waveform shown in . Then, after sending the time data t3 to the latch 393 and resetting and enabling the counter 389, the program returns to the main program.

Next, when the counter 389 reaches a count value corresponding to the time data t3, an interrupt is generated by the P timer. At this time, the state becomes 4, and the signal E causes the gate circuit 7 to
becomes non-conductive, disables musical tone output, and returns to the main program.

Therefore, a waveform as shown in FIG. 7 is generated overall.

Parameter code A+, A2 that determines the tone of the performer
, A3. If it is desired to change P and Q or to change the CPU control program, the switches on the tone control panel 32 or the CPU control panel 24 may be operated as appropriate. In this way, an interrupt is generated and a musical tone generation operation is performed in accordance with the changing operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a musical tone generating section in the electronic musical instrument, and FIG. 3 is an address in the musical tone generating section. A connection diagram for explaining the connection control operation of the counter output, FIG. 4 is a time chart for explaining the write/read operation of the FIFO memory in the musical tone generation section, and FIG. 5 is a diagram of the keyboard section and its FIG. 6 is a block diagram showing an example of a configuration of an interface circuit; FIG. 6 is a block diagram showing an example of a timer configuration in the electronic musical instrument; FIG. 7 is a waveform showing an example of a musical sound waveform generated by the musical tone generator. FIG. 8 is a flowchart showing some interrupt processing for the main program. 10... Common information transmission path, 20... CPU, 22
...Memory device, 24...CPU control panel section, 30.
...Keyboard section, 32... Tone control board section, 34... Musical tone generation section, 36... Display board section, 38... Modulation/demodulation circuit,
39...Timer. Applicant Yamaha Co., Ltd. Company Representative Patent Attorney Satoshi Izawa Figure 8

Claims (1)

[Claims] It has a data circulation path in which a data delay means and a digital filter are connected in a closed loop, and by circulating waveform data through this data circulation path, the data being circulated is extracted as musical waveform data. A musical tone synthesizer comprising: (a) a pitch instruction means for instructing a musical tone pitch; and (b) a number of words for controlling the number of words of delay data in the data delay means in response to the musical tone pitch instructed by the pitch instruction means. 1. A musical tone synthesis apparatus, comprising: a control means, and is adapted to take out musical waveform data having a specified musical pitch from the data circulation path.