JPH02152244A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02152244A
JPH02152244A JP63306547A JP30654788A JPH02152244A JP H02152244 A JPH02152244 A JP H02152244A JP 63306547 A JP63306547 A JP 63306547A JP 30654788 A JP30654788 A JP 30654788A JP H02152244 A JPH02152244 A JP H02152244A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
semiconductor device
thin part
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63306547A
Other languages
Japanese (ja)
Inventor
Eiji Kobayashi
栄治 小林
Atsushi Obuchi
大渕　淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63306547A priority Critical patent/JPH02152244A/en
Publication of JPH02152244A publication Critical patent/JPH02152244A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To adjust a difference in level between the surface of a semiconductor chip and a substrate face to a thickness of a thin part by a method wherein the thin part is formed in at least two or more parts of the semiconductor chip and the thin part is fixed to the substrate face. CONSTITUTION:At a semiconductor chip 6a, a thick part 6e of the semiconductor chip 6a is inserted into a chip-positioning hole 2a made in a die bonding pad 2a of a lead frame 2; a thin part 6b is fixed to the die bonding pad 2a by using an adhesive 3. Al electrode terminals formed on the surface of the semiconductor chip 6a and outer leads 2b of the lead frame 2 are connected by using Au wires 4. This assembly is sealed by using a resin 5 for protective use; a semiconductor device is completed.

Description

【発明の詳細な説明】 ［産業上の利用分野コ この発明は、半導体装置の構造に係り、特に半導体チッ
プを導電体又は絶縁体基板上へ固定させる調整構造を提
供する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to the structure of a semiconductor device, and particularly provides an adjustment structure for fixing a semiconductor chip onto a conductive or insulating substrate.

［従来の技術］ 第４図は従来の半導体装置を示す断面図で、図において
、Ｉａは半導体チップで、第５図に示す断面形状の半導
体ウェハ１を個々の半導体チップｌａに切断分離させた
後（第６図）、ダイポンドバット２ａＥＬび外部リード
線部２ｂを有する金属板（リードフレーム）２の前記ダ
イボンドパッド２ａに接着剤３にて半導体チップ１ａの
裏面を固定させている。さらに、半導体チップ１ａの表
面に形成されたＡＩ電極端子とリードフレーム２の外部
リード線部２ｂをＡｕ線４にて接続し、さらに保護用の
樹脂５にて封止して第４図に示す断面構造を有する半導
体装置を完成させていた。[Prior Art] FIG. 4 is a cross-sectional view showing a conventional semiconductor device. In the figure, Ia is a semiconductor chip, and a semiconductor wafer 1 having the cross-sectional shape shown in FIG. 5 is cut and separated into individual semiconductor chips la. Afterward (FIG. 6), the back surface of the semiconductor chip 1a is fixed with an adhesive 3 to the die bond pad 2a of the metal plate (lead frame) 2 having the die bond butt 2aEL and the external lead wire portion 2b. Furthermore, the AI electrode terminal formed on the surface of the semiconductor chip 1a and the external lead wire portion 2b of the lead frame 2 are connected with an Au wire 4, and further sealed with a protective resin 5, as shown in FIG. He had completed a semiconductor device with a cross-sectional structure.

［発明が解決しようとする課題］ 従来の半導体装置は以上のように構成されていたので、
半導体ウェハの大口径化にともない板厚の増加が必要と
なっており、半導体チップ上の電極と外部リード配線す
るＡｕ線の半導体チップエッヂ部との接続の不具合の発
生及び外形寸法特に厚み方向での寸法の増加等の問題点
があった。[Problem to be solved by the invention] Since the conventional semiconductor device was configured as described above,
As the diameter of semiconductor wafers becomes larger, it becomes necessary to increase the plate thickness, and problems occur in the connection between the electrodes on the semiconductor chip and the Au wire for external lead wiring at the edge of the semiconductor chip, and the external dimensions, especially in the thickness direction, There were problems such as an increase in the size of the

この発明は上記のような問題点を解決するためになされ
たもので、半導体チップの板厚の増加分を半導体チップ
の外周部の肉薄部の調整によって解消することを目的と
するものである。This invention has been made to solve the above-mentioned problems, and it is an object of the present invention to eliminate the increase in the thickness of a semiconductor chip by adjusting the thinned portion at the outer periphery of the semiconductor chip.

［課題を解決するための手段および作用］この発明の半
導体装置は半導体チップの少くとも２箇所以上の辺に肉
薄部を形成させ、この肉薄部を基板面に固定させること
により半導体チップ表面と基板面の段差を肉薄部の厚み
を調整することにより、従来の半導体チップの板厚によ
って決定されていた段差を所望の寸法に調整するもので
ある。[Means and effects for solving the problem] The semiconductor device of the present invention forms thin parts on at least two sides of a semiconductor chip, and fixes the thin parts to the substrate surface, so that the semiconductor chip surface and the substrate By adjusting the thickness of the thin portion of the surface level difference, the level difference, which was conventionally determined by the board thickness of the semiconductor chip, can be adjusted to a desired dimension.

［実施例］ 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

第１図はこの発明に係る半導体装置の一実施例を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

図において、６ａは半導体チップで、第２図に示す断面
を有する半導体ウェハ６を切断分離させて成る。第３図
は切断分Ｓ後の半導体チップ６ａを示す斜視図で、６ｂ
は半導体チップ６ａの肉薄部を示す。In the figure, 6a is a semiconductor chip, which is formed by cutting and separating a semiconductor wafer 6 having the cross section shown in FIG. FIG. 3 is a perspective view showing the semiconductor chip 6a after cutting S, and 6b
indicates a thin portion of the semiconductor chip 6a.

半導体チップ６ａはリードフレーム２のダイボンドパッ
ド部２ａに形成されたチップ位置決め穴２ｃに半導体チ
ップ６ａの肉厚部６ｃを挿入させるとともに肉薄部６ｂ
を接着剤３によりダイボンドバット２ａに固定させる。The semiconductor chip 6a is inserted into the chip positioning hole 2c formed in the die bond pad portion 2a of the lead frame 2 by inserting the thick portion 6c of the semiconductor chip 6a into the thin portion 6b.
is fixed to the die bond batt 2a with adhesive 3.

そして半導体チップ６ａ表面に形成されたＡｌ電極端子
とり−トフレーム２の外部リード線部２ｂをＡｕ線４に
て接続する。そして、保護用の樹脂５にて封止させるこ
とにより半導体装置を完成させる。Then, the external lead wire portion 2b of the Al electrode terminal frame 2 formed on the surface of the semiconductor chip 6a is connected with the Au wire 4. Then, the semiconductor device is completed by sealing with a protective resin 5.

［発明の効果］ 以上の様にこの発明によりば、半導体チップの外周に肉
薄部を形成し、その肉薄部をリードフレーム面に固定さ
せることにより、半導体チップ面とリードフレーム表面
の段差を調整して小ざくすることが出来るので、Ａｕ線
と半導体チップの接触防止及び封止樹脂厚も薄く出来る
ため外形寸法の小形化の実現が可能となる。[Effects of the Invention] As described above, according to the present invention, by forming a thin part on the outer periphery of a semiconductor chip and fixing the thin part to the lead frame surface, the level difference between the semiconductor chip surface and the lead frame surface can be adjusted. Since it can be made smaller, it is possible to prevent contact between the Au wire and the semiconductor chip, and the thickness of the sealing resin can be reduced, making it possible to reduce the external dimensions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明に係る半導体装置の一実施例を示す断
面図、第２図はこの発明に係る半導体ウェハの断面図、
第３図はこの発明に係る半導体チップの斜視図、第４図
は従来の半導体装置の断面図５第５図は従来の半導体ウ
ェハの断面図、第６図は従来の半導体チップの斜視図で
ある。 図において、２はリードフレーム、２ａはダイボンドパ
ッド、２ｂは外部リード線部、２Ｃはチップ位置決め穴
、３は接着剤、４はＡｕ線、５は封止樹脂、６は半導体
ウェハ、６ａは半導体チップ、６ｂは肉薄部、６ｅは肉
厚部を示す。 なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of a semiconductor wafer according to the present invention,
3 is a perspective view of a semiconductor chip according to the present invention, FIG. 4 is a sectional view of a conventional semiconductor device, 5 is a sectional view of a conventional semiconductor wafer, and FIG. 6 is a perspective view of a conventional semiconductor chip. be. In the figure, 2 is a lead frame, 2a is a die bond pad, 2b is an external lead wire section, 2C is a chip positioning hole, 3 is an adhesive, 4 is an Au wire, 5 is a sealing resin, 6 is a semiconductor wafer, and 6a is a semiconductor In the chip, 6b indicates a thin portion, and 6e indicates a thick portion. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップの外周部に肉薄部を形成し、この肉薄部を
基板面へ固定させ、前記半導体チップ表面と基板面の段
差を前記肉薄部の厚みを変えることにより所望の寸法に
することを特徴とする半導体装置A thin wall portion is formed on the outer periphery of the semiconductor chip, the thin wall portion is fixed to the substrate surface, and the level difference between the semiconductor chip surface and the substrate surface is made to a desired dimension by changing the thickness of the thin wall portion. semiconductor device
JP63306547A 1988-12-02 1988-12-02 Semiconductor device Pending JPH02152244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63306547A JPH02152244A (en) 1988-12-02 1988-12-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63306547A JPH02152244A (en) 1988-12-02 1988-12-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02152244A true JPH02152244A (en) 1990-06-12

Family

ID=17958353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63306547A Pending JPH02152244A (en) 1988-12-02 1988-12-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02152244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06104294A (en) * 1992-09-17 1994-04-15 Nec Corp Lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06104294A (en) * 1992-09-17 1994-04-15 Nec Corp Lead frame

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