JPH02151782A - Method of testing semiconductor device - Google Patents

Abstract

PURPOSE:To widen a testing range for guaranteeing limiting minimum clock frequency of a semiconductor testing device or the like by a method wherein two kinds of clock signals having the same frequency and different in logic levels are input and internal clock signals are generated and tested. CONSTITUTION:A clock signal terminal 26 is always applied with low-level signals while external clock signals CLK1, CLK2 are input to clock signal input terminals 27, 28 respectively. With input of low-level signals to the terminal 26, a transistor (TR) Q1 is turned off and a TRQ2 is turned off, so that emitter output signals of a TRQ3 remains at low level during test. In an interval that base potential of the TRQ10 is higher than base potential of the TRQ11, the TRQ10 is turned on and the TRQ11 is turned off so that base potential of a TRQ12 is at high level and high-level signals are taken out from an emitter of the TRQ12. On the other hand, in an interval that base potential of the TRQ10 is lower than base potential of the TRQ11, the TRQ10 is turned off and the TRQ11 is turned off, so that low-lvel signals are taken out through a base emitter of the TRQ12.

Description

[Detailed Description of the Invention] [Summary] Concerning a method for testing a semiconductor device having an internal circuit that operates in synchronization with an external clock signal, a lock signal that can be generated by a pulse generator or semiconductor test equipment that generates an external clock signal is used. The purpose of this test is to test a semiconductor device 1a that operates with a clock signal having a cycle shorter than the minimum cycle, and to test the first and second transistors of a differential circuit consisting of first and second transistors whose emitters are commonly connected. - A clock that supplies first and second external clock signals to each base of the transistor through the first and second clock signal input terminals, generates an internal clock signal from the differential circuit, and outputs the generated internal clock signal to the internal circuit. A method for testing a semiconductor device internally testing a circuit, wherein first and second external clock signals having the same period and different logic levels are tested, wherein the first external clock signal is higher than the second external clock signal. The first external clock signal of the semiconductor device has a phase relationship such that periods in which the second external clock signal is at a high level and periods in which the second external clock signal is at a higher level than the first external clock signal alternately appear twice within one cycle. The test is performed by inputting the first and second external clock signals to the clock signal input terminal and the second clock signal input terminal, respectively.

[Industrial application field]

The present invention relates to a method for testing a semiconductor device, and more particularly to a method for testing a semiconductor device having an internal circuit that operates in synchronization with an external clock signal.

In a semiconductor device that has an internal circuit that operates in synchronization with an external clock signal, the external clock signal is supplied,
Usually, a clock circuit is included in order to distribute and output this signal to a plurality of internal circuit sections, or to convert it to a logic level determined by the internal circuit.

In a semiconductor device incorporating this clock circuit, the internal circuit, ie, the semiconductor device, is tested by varying the clock signal period in order to guarantee the minimum period of the clock signal that allows the internal circuit to operate normally. Therefore, when testing this semiconductor device, it is necessary to be able to supply a clock signal with a cycle as short as possible to the internal circuit.

[Conventional technology]

A clock circuit built into a conventional semiconductor device has a sixth clock circuit.
There are single-phase clock circuits with only one clock input terminal, as shown in FIG. 7(A), and differential clock circuits with two clock input terminals, as shown in FIG. 7(A).

The single-phase clock circuit not shown in FIG. 6(A) is the semiconductor device 1.
A single clock input terminal 2 is connected to the base of the NPN transistor Q+. The emitter of the transistor Q1 is NPN, and the emitter of the transistor Q2 is connected to the constant current source 4.
A common differential current switch circuit is constructed in which the collectors of the two collectors are connected to a load resistor R1.

In addition, in FIG. 6(A), 3 is a constant voltage VR input terminal;
Q3 is an NPN transistor constituting an emitter of 740 watts, and 5 is a constant current source. The emitter output of transistor Q3 is supplied as a clock signal to an internal circuit (not shown) such as an ECL (emitter coupled logic) type logic circuit or memory.

In a test to guarantee the minimum clock cycle of the semiconductor device 1 having a single-phase clock circuit with such a configuration, as shown in FIG. 6(B), the high-level potential v1 is higher than the constant voltage VR and the low The clock signal CL whose level potential ■2 is lower than the constant voltage VR and whose period is tcYc
Input K to clock input terminal 2.

During the period when the clock signal CLK is at a high level, transistor Q1 is on and transistor Q2 is off, so a high-level voltage (ground potential) is supplied to the base of transistor Q3, and a high-level signal is supplied from the emitter of Q3. taken out.

On the other hand, during the period when the clock signal CLK is at a low level, the transistor QI is turned off and the transistor Q2 is turned on, so that the collector potential of the transistor Q2 decreases and an O-level signal is taken out from the emitter of the transistor Q3. Therefore, the emitter of transistor Q3 outputs the same signal as the external input clock signal CLK shown in FIG. 6(B).
A clock signal having a period of 1i1Jtcvc and having the same phase is taken out.

Therefore, it is possible to test whether the internal circuit operates normally by setting the period tcYc of the external input clock signal CLK to the guaranteed minimum clock cycle.

On the other hand, the differential clock circuit shown in FIG. 7(A)
It is provided within the semiconductor device 10, and two types of clock signals are input to two input terminals 11 and 12. The differential clock circuit consists of a general differential current switch circuit consisting of NPN transistors Q4 and Qs, a constant current source 13, and a collector load resistor R2 of Qs, and an emitter follower NPN transistor Q6 and a constant current source provided on the output side. Current source 1
It is composed of four output circuits.

A semiconductor device 10 having such a differential circuit
When testing to guarantee the minimum clock period of
As shown in FIG. 7(B), the high-level potential is V3 and the low-level potential is 4 with a period of tCYC in opposite phases.
Clock signals CLK and CLK are input to clock input terminals 11 and 12. In this case, the clock signal CL shown in FIG. 7(B) is transmitted from the emitter of the transistor Q6 to the internal circuit (ECL type logic circuit, memory, etc.).
A clock signal having the same phase as K and the same period tCYC is supplied.

Further, as shown in FIG. 7(C), a clock signal with a period tc''r'c in which the high level potential is v5 and the low level potential is v7 is input to the clock input terminal 11,
As shown in FIG. 6(C), a constant voltage of the intermediate potential v6 between the potentials v5 and v7 may be manually applied to the clock input terminal 12 as a clock signal. In this case, the single-phase signal shown in FIG. 6(A) The circuit operation is the same as that of the clock circuit, and a clock signal having the same phase and period tCYC as the clock signal CLK shown in FIG. 7(C) is supplied from the emitter of the transistor Q6 to the internal circuit.

Thereby, when testing the semiconductor device 10, it is possible to set the external input clock signal CLK and the cycle tCYC of CLK to the guaranteed minimum clock cycle.

(Problem to be Solved by the Invention) However, in recent years, the internal circuits of semiconductor devices have become increasingly capable of high-speed operation, and external pulse generators and semiconductor testers that generate the above-mentioned external clock signals CLK and C'LK have become increasingly capable of operating at higher speeds. There is a drawback that the conventional test method described above cannot test semiconductor devices that can operate with a clock signal with a shorter cycle (for example, 10 ns) than a clock signal with a minimum cycle (for example, 20 ns) that can be generated by the device. Ta.

The present invention has been made in view of the above points, and tests semiconductor devices that operate with a clock signal having a cycle shorter than the minimum cycle of a lock signal that can be generated by a pulse generator or semiconductor test equipment that generates an external clock signal. The purpose of the present invention is to provide a method for testing a semiconductor device that can perform the following steps.

[Means to solve the problem]

FIG. 1 shows a waveform diagram for explaining the principle of the present invention. In the method for testing a semiconductor device according to the present invention, as shown in FIG.
The external clock signal CLK2 of the first external clock signal CLK2 is set during the period 1.1 during which the first external clock signal CLK1 is at a higher level than the second external clock signal CLK2. ．． 1. and a second external clock signal C
At the first and second clock signal input terminals of the semiconductor device, the phase relationship is such that periods 12.14 in which LK2 is at a higher level than the first external clock signal CLK1 alternately appear twice in one cycle tcvc. The test is performed by inputting the first and second external clock signals, respectively.

[Effect]

A semiconductor device to be tested according to the present invention has at least two clock signal input terminals, and receives first and second external clock signals input thereto from first and second transistors whose emitters are commonly connected. The differential circuit has a built-in clock circuit that is supplied to the base of each transistor of the single-acting circuit, generates an internal clock signal from this differential circuit, and outputs it to the internal circuit.

Such a semiconductor device may include a built-in differential clock circuit 23, such as the semiconductor device 20 shown in FIG. 2A, or a normal clock circuit used during normal operation, such as the semiconductor device 25 shown in FIG. 2B. In addition to the circuit 29, some devices have a built-in test clock circuit 30 exclusively for testing.

The semiconductor device 20 shown in FIG. 2A has an external clock signal C input in parallel to clock signal input terminals 21 and 22, respectively.
LK1. CLK2 is supplied to the differential clock circuit 23, which generates an internal clock signal. As shown in FIG. 1, the external clock signal CLKI has a high level potential of Vs and a low level potential of Vu, and the external clock signal CLK2 has a high level potential of v8 and a low level potential of V+o. These potentials v8 to V11 (7
) (Ik-Va > V9 > VIQ > Vll
Naru M person is t%le.

As a result, as shown in FIG.
Within the cycle 11QjCYC of LKI and CLK2, the period tl and t3 when the external clock signal CLK1 is at a higher level than CLK2 and the external clock signal @CLK2 is C
Period j2 when the level is higher than LKl. i4 and 2 alternately
Appears once in a while.

On the other hand, the differential clock circuit 23 is a clock circuit originally used for normal operation, but is also shared during testing, and is the same as the differential clock circuit in the conventional semiconductor device 10 shown in FIG. 7(A). It is. As described above, the differential clock circuit has a high level when one clock signal CLK has a higher potential than the other clock signal CLK, CL K /J
<CLK Operates to output a low level signal when the potential is lower than K.

Therefore, from the differential clock circuit 23, the period t+
, t3, and a low level during the periods t2 to t4, a pulse as shown in FIG. 1(B) is generated and output as an internal clock signal.

Since the internal clock signal shown in FIG. 1(B) has a cycle of j c v c / 2, which is 1/2 times the cycle of the external clock signals CLKI and CLK2, the minimum clock cycle is 1/2 times that of the external clock signals CLKI and CLK2. This means that it can be expanded to twice the size.

Moreover, in the case of this semiconductor device 20, since the differential clock circuit 23 is originally used during normal operation, there is no need to change the configuration of the semiconductor device 20 for testing. Note that in FIG. 1(B), t1)d is the propagation delay time of the differential clock circuit 23.

Further, the semiconductor device 25 shown in FIG. 2B has, in addition to the clock signal input terminal 26 normally connected to the clock circuit 29,
It has clock signal input terminals 27 and 28, respectively, dedicated to testing.

The normal clock circuit 29 is a single-phase clock circuit within the semiconductor device 1 shown in FIG. 6(A). On the other hand, the test clock circuit 30 is the differential clock circuit.

Therefore, by inputting the first external clock signal CLK1 and the second external clock signal CLK2 to the clock signal input terminals 27 and 28 in parallel, the test clock circuit 30 can be An internal clock signal having the waveform shown in FIG. 1(B) is generated and output from the circuit. This internal clock signal is connected to the test clock circuit 30 by a switch 3 only during testing.
1 to the internal circuit.

As with the semiconductor device 20, the minimum clock frequency for this semiconductor device 25 is 1/2 that of the conventional one! Testing with Il+ becomes possible.

Note that the switch 31 may be a switch that selectively operates only one of the two normal clock circuits and the test clock circuit 30.

(Example) Next, each example of the present invention will be described with reference to FIGS. 3 to 6. Note that each of the following embodiments shows a circuit such as a test clock circuit in a semiconductor device equipped with a test clock signal input terminal and a test clock circuit. As shown, it is most effective when applied to a semiconductor device having an existing differential clock circuit.

FIG. 3 shows a circuit diagram of a first embodiment of the invention.

In the figure, the same components as those in FIG. 2B and FIG. 6(A) are designated by the same reference numerals, and their explanations will be omitted.

In FIG. 3, the test clock circuit 308 has a base at the connection point between NPN transistors QIG and Qll whose emitters are commonly connected to the constant current source 33, the collector load resistance R3 of Qn, and the collector of Qo and the resistance R3. Furthermore, the emitters of transistors Q3 and Q10 are commonly connected to a constant current source 34, and a clock signal input terminal of an internal circuit (not shown). It is connected to the. That is, the output of the normal clock circuit 29a and the output of the test clock circuit 30a are logically connected by a common emitter follower.

Next, the operation during the test will be explained. At this time, a low level signal is always applied to the clock signal input terminal 26, and external clock signals CLKI and CLK2 shown in FIG. 1(A) are applied to the clock signal input terminals 27 and 28.
are input respectively.

By inputting a low level signal to the clock signal input terminal 2G, the transistor Q1 is turned off and the i-transistor Q2 is turned on, so that the emitter output signal of the transistor Q3 remains at a low level during the test.

On the other hand, the period when the base potential of the transistor Q+a is higher than the base potential of the transistor Qu (1+
, 13), the transistor Q+o is on and the transistor Qn is off, so that the base potential of the transistor (hz) becomes high level (ground potential), and a high level signal is taken out from the emitter of the transistor QI2. It will be done.

On the other hand, the period in which the base potential of transistor Q+o is lower than the base potential of transistor Qu (Fig. 1 (A>
nij2. j4), the transistor Q1
6 is off and 1 transistor Qu is on, which causes a voltage effect due to the load resistor R3, and transistor Q
A low level signal is taken out through the base and emitter of 12.

Therefore, the pulse shown in FIG. 1(B) is output from the emitter of transistor Q12 to the internal circuit as an internal clock signal.

Note that when the normal clock circuit 29a is operated, the input potential of the clock signal input terminal 27 of the test clock circuit 30a is held lower than the input potential of the clock signal input terminal 28. As a result, the emitter output signal of transistor QI2 is always at a low level.

FIG. 4 shows a circuit diagram of a second embodiment of the invention.

In the figure, the same components as those in FIG. 3 are designated by the same reference numerals, and their explanations will be omitted. In this embodiment, a part of the normal clock circuit is shared with the test clock circuit, and the clock signal input terminal 36 is used exclusively for the clock signal during normal 03 operation and the test clock signal CLK1.

In FIG. 4, Q10.0I4 are NPN transistors each having an emitter follower configuration, each having a clock signal input terminal 36.28 connected to its base, and a constant current source 37°38 connected to each emitter. It is connected. Furthermore, the emitters of transistors Q13 and Q10 are separately connected to the bases of transistors Q+o and Qu.

Also, it is a Q+s1.1tNPN transistor, whose collector is connected to the common connection point of the collector of the transistor Qn, the base of Q12, and the resistor R3, and its emitter is commonly connected to the emitters of the l-transistors QIO and Qll. There is. A constant voltage VRVBE is constantly applied to the base of the transistor Q+s via a terminal 39. However, V[JE is the base-emitter voltage of each transistor such as Qδ when it is on. Furthermore, the emitter of transistor Q12 is connected to constant current source 40, while
Connected to the clock signal input terminal of the internal circuit.

Next, the operation during the test will be explained. During testing, the external clock signal @CLK1 shown in FIG. 1 (A) is input to the clock signal input terminal 36, and the external clock signal CL shown in FIG. 1 (Δ) is input to the clock signal input terminal 28.
K2 is input.

However, the low-level potential Vu of the external clock signal CLKI is set to a value greater than the reference voltage VR.

As a result, the period when CLKI is at a higher level than CLK2 (
i+, ia) in FIG. 1(A) is the transistor Q
to is turned on, and transistor Qu is turned off. Here, the base potential of the transistor QCs (VR-V
B E ) is lower than the base potential (VIO-VB E ) of the transistor Qn at this time, and the transistor Q
Cs is always off.

By turning off transistors Qu and Q+s, a high level signal is taken out from the emitter of transistor QI2.

On the other hand, during the period when ClK1 is at a lower level than ClK2 (tz, t4 in FIG. 1 (△)), 1-transistor QIO, Q
15 are respectively off and transistor Qu is on, so
A []-level signal is taken out from the emitter of transistor Q12.

Therefore, during the test, as in the above embodiment, as shown in FIG.
As shown in , the cycle is 1/2 that of CLKl and ClK2!
A clock signal of CY C/2 is taken out.

Note that during normal operation, the clock signal input terminal 36 has a high level potential that is higher than the reference voltage VR (for example, -13V) (for example, -0.9V), and a low level potential that is lower than the reference voltage Va+ (for example, -1.7V) clock signal for normal operation is input. At the same time, the clock signal input terminal 28 is fixed at a potential equal to or lower than the [1- level] of the normal operation clock signal.

In this case, the base potential of the transistor Qo is always lower than the base potential (VR-VB Bi) of the transistor QCs, and the transistor Qu is always turned off.

During the high level period of the above normal operation clock signal [when the base potential of transistor QIG is (VRVBE)J:
Since the voltage becomes high, transistor QIO is turned on, transistor QCs is turned off, and the emitter output of transistor Q12 becomes high level.

Furthermore, during the low level period of the normal operation clock signal mentioned above, the base potential of the transistor QIO is (VR-Vo E
), transistor Q+a turns off and transistor QCs turns on, so the emitter output of transistor QI2 becomes low level. Therefore, during normal operation, a differential current switch consisting of transistors Q+o and Q+s, etc., outputs a signal of the same period and phase from the emitter of transistor Q12 as an internal clock signal to the normal operation clock signal input to the clock signal input terminal 36. taken out.

Next, a third embodiment of the present invention will be described with reference to the circuit diagram of FIG. In FIG. 5, the same components as in FIGS. 2B and 3 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 5, 42 is a clock mode (CM) terminal, which is an NPN
Connected to the base of transistor Q+6.

1-The collector of transistor QI6 is transistor Q+
, Q2, and these normally constitute a clock circuit 29b.

The NPN transistor Q17 has its collector connected to the emitters of the transistors Q+o and Qn, respectively, and constitutes the test clock circuit 30b together with the transistor Q16.011 and the resistor R3. Furthermore, transistor QI6
and Q+y emitters are connected to a constant current source 44.

Collectors of transistors 02 and Qn and load resistor R3
The connection point with is connected to the base of transistor Q12,
Further, the emitter of the transistor QI2 is connected to a constant current source 46.

A constant Mt$ voltage VR is always applied to the base of the transistor Q2 via the terminal 43, and a constant voltage (VR-Ve E ) is always applied to the base of the transistor QI7 via the terminal 1'f-45. is being applied.

When testing a semiconductor device equipped with clock circuits 29b and 30b having such a configuration, the 0M terminal 42 is connected to (VR-VB
E) Fix to a lower potential than E).

As a result, the transistor QI6 turns off, and the normal clock circuit 29b becomes inactive during the test.
Transistor QI7 is turned on, and test clock circuit 30b becomes operational.

At the same time, clock signal input terminals 27 and 28
The external clock signals CLKI and ClK2 are supplied to the transistors QI and ClK2, and the transistor QI
The period i CY shown in FIG. 1(B) from the emitter of 2
A C/2 clock signal is extracted.

On the other hand, during normal operation, the CMI element 42 is connected to the potential (VR
-VBE).

As a result, the transistor Q16 is turned on, and the normal clock circuit 29b is placed in an operating state, while the transistor Q+y is turned off, and the test clock circuit 30b is placed in a non-flr operating state.

On the other hand, since the external clock signals CL and K shown in FIG. 6(B) are inputted to the clock signal input terminal 26, the same operation as the single-phase clock circuit explained in conjunction with FIG. 6(A) is performed. , an internal clock signal having the same period and the same phase as the input external D-sock signal CLK is taken out from the emitter of the transistor QI2.

In the case of this embodiment, as in the above-mentioned embodiments, it is possible to generate and output an internal clock signal with half the minimum clock cycle that can be generated by an external pulse generator or semiconductor test equipment. It has the advantage of being able to expand the test range compared to conventional methods.

〔Effect of the invention〕

As described above, according to the present invention, a test is performed by inputting two types of clock signals with the same period but different logic levels to generate an internal clock signal, so that the clock circuit in the semiconductor device is In the case of a differential clock circuit, without changing the configuration of the semiconductor device from the conventional one, and even if the clock circuit inside the semiconductor device is a single-phase clock circuit, by installing a test clock circuit, the external It is possible to expand the test range for guaranteeing the minimum clock cycle to 1/2 the limit minimum clock cycle of pulse generators and semiconductor test equipment, and improve the reliability of semiconductor device testing -F. It is a Shino that has the characteristics of being a great person.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the principle of the present invention, FIGS. 2A and 2B are configuration diagrams of a semiconductor device to which the present invention can be applied, and FIGS. 3 to 5 are diagrams of respective embodiments of the present invention. 6 and 7 are conventional explanatory circuit diagrams and waveform diagrams for each side, respectively. In the figure, 20.25 is a semiconductor device, 21.27 is a first clock signal input terminal, and 22.28 is a semiconductor device.
29 is a second clock signal input terminal, 23 is a differential clock circuit, 26 is a normal operation clock signal input terminal, 29.29a
, 29bkt normal/) lower 1) circuit, 30.30
30a and 30b indicate test clock circuits. H-sized book donation for home buyers! Fig. 28/Early secondary Kashiri of F4A. Blind) mouth fsS diagram (A) (B) Diagram O

Claims (1)

[Claims] First and second clock signal input terminals (21, 2
2: A semiconductor having a built-in clock circuit (23, 30) that supplies first and second external clock signals via the differential circuit (27, 28), generates an internal clock signal from the differential circuit, and outputs it to the internal circuit. A device testing method, comprising first and second external clock signals (CLK1, CLK2) having the same period and different logic levels, the first external clock signal (CLK1) being the second external clock signal. (
CLK2) and the second external clock signal (CLK2) is at a higher level than the first external clock signal (CLK2).
The phase relationship between the first clock signal input terminal (21, 27) and the second clock signal input terminal of the semiconductor device is such that periods at a level higher than K1) alternately appear twice in one cycle. (22, 28) the first and second
A method for testing a semiconductor device, characterized in that testing is performed by inputting external clock signals (CLK1, CLK2), respectively.