JP2932501B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to applying a signal different from a normally used state to another function of the semiconductor integrated circuit device. The present invention relates to a semiconductor integrated circuit device that operates.

[Conventional technology]

4 (a) and 4 (b), as shown in the conventional example, the logic element 1 and the inverter logic element 2 are connected to the input I _11.
It is connected to pin 4. The output of the logic element 2 leads to the next inverter logic element 3, the output, the output terminal 5 of the output O ₁₂ of the lower bits of the input pins 4, logic element 1
Output has been connected to the output terminal 6 of the output O ₁₁ of the upper bit.

Next, the operation of this circuit will be described. The logic element 2 has a logic threshold between a normal power supply voltage and ground (GND), and transmits a signal to the next stage in response to an input change. As a result, the signal input and phase appears at the output O ₁₂ of the output terminal 5.

Meanwhile logic element 1 is at logic threshold is higher than the supply voltage, the output to only the output O ₁₁ when you enter a high voltage exceeding this threshold appears. In other words, I ₁₁ is on the output O ₁₂ side.
When the semiconductor integrated circuit is operating, even if the voltage of the input terminal 4 is increased, the normal operation is not affected, and the operation of another function can be newly performed. . This can be realized, for example, by providing dedicated input pins. However, since the number of pins of a package is often limited in an IC, such an input pin capable of multi-level input is required.

[Problems to be solved by the invention]

In the above-described conventional semiconductor integrated circuit, a voltage higher than the power supply must be applied to the input pin. Some older ICs use various power supplies, such as + 5V, + 12V, and -5V, such as 16kbit DRAM.
It was easy to make a signal of the level. However, most of recent ICs have a single 5V power supply, which makes it difficult to generate signals higher than the power supply voltage.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit in which the above-mentioned drawbacks are solved and a signal can be sent to another semiconductor integrated circuit at a normal logic level.

[Means for solving the problem]

In the semiconductor integrated circuit device of the present invention, a high potential and a low potential are supplied during normal operation, and during a different function operation,
A / D converter circuit connected between the high potential side terminal, the low potential side terminal to which the low potential and the high potential are supplied, and the high potential side terminal and the low potential side terminal, respectively, In the semiconductor integrated circuit device having a built-in R string circuit for generating a comparison voltage, the high potential side terminal and the low potential side terminal which are connected to the high potential side terminal and the low potential side terminal when another function is operated. And a detection circuit for detecting that the potential relationship is opposite to that in the normal operation.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 (a) is a circuit diagram showing a first embodiment of the present invention,
FIG. 1 (b) is a diagram showing the operation of FIG. 1 (a).

In FIG. 1 (a), a semiconductor integrated circuit device according to a first embodiment of the present invention includes, for example, an input I of a high potential side terminal 9 of an R string circuit (Rs) 11 for generating a comparison voltage of an A / D converter. ₊ the input I of the low potential side terminal 10 _- each and are input to an exclusive (exclusive) OR @ 7, the logical in the logic circuit 8 comprising a NAND gate which receives the output O ₁ again, the output obtaining a signal O _2. Exclusive AND 7 is input I ₊ , I
_- each having an input terminal 9, 10 to input circuit 8 of NAND gate has an output O _1, input I _- as input and outputs an output O ₂ to the output terminal 12.

As shown the operation in Fig. 1 (b), first, usually I ⁺
> I ^- relationship is maintained. If this circuit device is not used, it is fixed to “1” or “0”, so I ⁺ = I ⁻
There is also a state. Therefore, when these combinations are used,
Output O ₂ of 12 have the same value, I ⁺ = I ^- seen that the logic is organized such that different value only when it is related.
The I ⁺ <I ^-, in normal use in combination does not occur absolutely therefore as long as the normal operation is the IC output O ₂ is "0" it is not to be.

FIG. 2 is a circuit diagram showing an example in which the circuit device of FIG. 1A is actually used. In Figure 2, the input I ₊ is applied to the input terminal 14, connection of the electrode switches S _2, the electrodes of the other switch S ₁ reference voltage input terminal 13
V ₊ leads. Also the input I _0, electrode or an input terminal 16 of the switch S ₄ is lead, the electrode of the other switches S ₃ Reference Voltage V _- that is, the input terminal 15 leads. here,
Switch S ₁ and S _3, and the switch ₂ and S ₄ is respectively in phase and group S _1, have become mutually opposite phase relation to the group of S _2. Voltage V ₊ and V _- voltage relationship is, V _+> V _-
In the input I ₁ is "0" level, the input I ₀ is assuming that is fixed to the "1" level, when a signal for switching the polarity of the switches S _{1 to 4} is input to the switching circuit, it until I ₊ = From V ₊ > I ₋ = V ₋ , I ₊ = I ₁ <I ₋ = I ₀ , whereby the output O ₂ in the IC changes and a signal can be input to this IC. Of course, at this time, the other input ports are not affected even when receiving the original signal.

In FIG. 1A, components other than the input terminals 9 and 10 are formed in the semiconductor integrated circuit chip 30.

The semiconductor integrated circuit of this embodiment the upper input I ₁ of the reference power source, such as A / D converters and comparators, lower input I _- has a circuit for comparing the potential relation, the resistor string having a polarity A signal is applied from the outside so as to have the opposite polarity, and some circuit functions in the semiconductor integrated circuit device are changed.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

In this circuit, there are no special additional elements, and the elements that make up the A / D converter are used as they are. First, the analog switch 20 receives a clock and selects an appropriate one of switches for selecting the low-potential-side input terminal 22 of the R string circuit (Rs) 11. The analog switch 21 receives a clock φ and inputs a high-potential-side input terminal. Select and use the appropriate switch from among the 23 switches. Comparator 24 inside the dotted line
Uses the one used in the A / D converter. The configuration of the comparator 24 has a sample-and-hold capacitance 25 as an input, which is connected to the input of the inverting amplifier 26. A bias transistor 27 is connected between the input and output of the inverting amplifier 26, and a clock φ is input to the gate of the transistor 27. Comparator 24
The output of the inversion is a output of the amplifier 26, and line output O ₂ via a level converter 28 for converting logic levels.

The operation of the circuit device shown in FIG. 3 first has a precharge period. At this time, the clock φ is “1”, the upper side of the R string circuit 11 is selected, and the transistor switch 21 is turned on. You have entered a level. In the comparator 24, the transistor 27 charges the on-capacitance 20 during the biasing period. Output level, through a level converter 28, the output O _2, and outputs a "1".

Next, there is a comparison period. This time, the transistor 20 for selecting the lower side of the R string circuit 11 is turned on and is input to the comparator 24. Comparator 24, since the transistor 27 is off, if I _+> I _- if the potential of the input side is going down, so the original output is "1" by the level converter 28, the output O ₂ Does not change. However, I ₊ <I _- if the output O ₂ in the reverse is "0". The I ₊ <I _- conditions, as described in the first embodiment described above, a combination that does not occur in normal use.

Semiconductor integrated circuits with built-in A / D and comparator circuits,
In particular the microprocessor, since these do not have always used a function, the period of non-use I ⁺ <I ^-
There is no problem in providing the above-described cycle for detecting the error.

〔The invention's effect〕

As described above, the invention, R string section normal I ₊ I _- in the case of utilizing the fact that is the, I ₊ <I by external signals _- By making the state of this in the IC There is an effect that an external signal can be input.

[Brief description of the drawings]

FIG. 1A is a logic circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention, FIG. 1B is a diagram showing a truth table of FIG. 1A, and FIG. 1A is a circuit diagram showing an application example of the circuit device, FIG. 3 is a logic circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 4A is a conventional semiconductor integrated circuit. FIG. 4 (b) is a diagram showing a truth table of FIG. 4 (a). 1,2,3,7,8 …… Logic elements, 4,9,10,13,14,15,16,22,23…
... input terminals, 5, 6, 12 ... output terminals, 24 ... comparators, 26 ... inverting amplifiers, 28 ... level converters, 20, 21 ...
... switch, 27 ... transistor, 25 ... sample-and-hold capacitance.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822

Claims (1)

(57) [Claims] 1. A high potential side terminal to which a high potential and a low potential are respectively supplied during a normal operation, and a low potential and a high potential which are respectively supplied in a different function operation in reverse to the normal operation.
A semiconductor integrated circuit device including a low-potential-side terminal and an R string circuit connected between the high-potential-side terminal and the low-potential-side terminal for generating a comparison voltage of an A / D converter circuit; And a detection circuit connected to the low-potential-side terminal and detecting that the potential relationship between the high-potential-side terminal and the low-potential-side terminal during another function operation is opposite to that during the normal operation. A semiconductor integrated circuit device comprising: