JPH02151185A - Frame inter-line type solid-state image pickup element and its drive method - Google Patents

Abstract

PURPOSE:To use the element for both a movie and an electronic still camera by providing two storage sections and varying the connection of electrodes of a vertical transfer section for each column. CONSTITUTION:In the case of the electronic still mode, a signal charge of picture elements 10-18 is read simultaneously to vertical transfer sections 18A, 18B via a transfer gate by each field. Then the excess electric charge is thrown away to the substrate via a longitudinal overflow drain. Then exposure and storage for a prescribed time is applied to read the signal charge of the picture elements 10-16 by the vertical transfer sections 18A, 18B via the transfer gate by each field simultaneously. In the case of the movie mode, the signal charge of a field A and that of a field B are not simultaneously read from the picture elements 10-16 but read out at a time difference of one field period (1/60sec).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor and a driving method thereof, and particularly to a frame interline transfer fFIrl type CCDtj&1.
This invention relates to a jetting element and its driving method.

[Prior Art] CCD image pickup devices, which are widely used as solid-state 12i image devices, have conventionally adopted a frame transfer method (8+ method) and an interline transfer method (1 ) method.The FT method has a light receiving section and a storage section independently.1
When using the electronic still mode, which has a live-like signal transfer section between the light receiving images and each has its own advantages and disadvantages, there is a time difference in the timing of reading out the signal charges of both fields A and 8. Therefore, in the N method, signal charges are simultaneously read out from all pixels in both fields A and 8 to the vertical transfer section, and then to each column of the two horizontal transfer sections provided at the end of the vertical transfer section. A method of obtaining two output signals by applying signal charges of the A field and B field respectively and horizontally transferring them is shown in the 1987 Journal of the Television Society of Japan (Page 85).

Recently, a frame interline transfer (FIT1) type CCD image sensor has been developed and put into practical use as a configuration that overcomes the shortcomings of the FDN type and the single type.
fi (Motoko Fura, for example, the Journal of the Society of Television Vo140
, No. 1+ (1980) No. P, 1062 As shown in Figure 6, the CCD camera 1 of the 1■ method also extended the vertical transfer section of the element and provided a storage section similar to the frame memory in the H method. It was developed primarily as a smear countermeasure.

These various types of CCO TI image elements are used not only for video cameras (Movie (registered trademark)) but also for electronic still cameras.

An electronic still camera uses a mechanical shutter to obtain one frame (two fields) of signals with one exposure. On the other hand, in the case of movies, an electronic shutter is used to capture fast-moving images.
p.

[Problem to be solved by the invention] Video cameras (movies) must have high dynamic resolution, while electronic still cameras preferably have high vertical resolution. Since it is determined by the method, t+ (no previous method could satisfy both conditions).

Furthermore, since conventional electronic still cameras required the use of mechanical cassettes, there was a risk of wear and tear on parts.
There are problems such as failure and damage, and there are also problems that the cost is high and interlocking operations are difficult. As a shutter for electronic still cameras (b) (If the electronic shutter used in conventional movies can be moved for each field, there will be a difference of 1/60th of a second between two fields, making it unsuitable for still photography of moving subjects. It is.

In addition, when simultaneously reading out image signals of both fields A and 8 in the above-mentioned IT method, \\.

Since the video signals of 8 fields are output almost simultaneously without a time difference of 1/60th of a second, in order to make a normal composite video signal, the signal of one field must be output via external memory. It was necessary to delay.

Therefore, it can be used extensively for both movies and electronic still cameras, and when using an electronic shutter, even when reading both the A and 8 field signals at the same time, there is no need for external memory, and the gap between the two signals is 1/60th of a second. There has been a demand for a solid-state negative element and a method for driving the same, which can provide a time difference of 100 kHz and which can be used as an electronic still camera without the need for a mechanical shutter.

In order to fulfill this desire and reality, prior to the present invention, this author developed an NT-based solid state r;A f? We have developed a + element and its driving method, and have filed a patent application for l1iT1↑. Among these patent applications, the embodiment shown in FIG. 9 of the patent application titled "Frame interline type solid-state photography (9, element and method for driving the same") dated October 17, 1986 has a photoelectric conversion section. One column of vertical transfer sections is provided on both sides of each vertical pixel column, and the extended portion of each vertical transfer section is used as a storage section that can store charges for one frame in total. The structure is such that charges are taken out through a horizontal transfer section.

FIG. 6 is a diagram showing the already proposed solid-state #ii light element shown in the above-mentioned prior application. In FIG. 6, 10 to 1G are some pixels of one vertical column of pixels arranged two-dimensionally, and these constitute a photoelectric conversion section. 18A and +8B are vertical transfer sections provided one column on each side of each vertical pixel column, and in response to a transfer gate pulse, signal charges from each pixel 10 to 1G are transferred via transfer gate sections (not shown). The vertical transfer section 18A of Ta during the vertical blanking period as shown by the arrow.

Transferred to 18B. 20A and 20B are storage sections provided in the extensions of each of the vertical transfer sections +8A and +8B, both of which consist of one CCO for each vertical row. In the figure, each storage section 20A, 20B has the same number of stages as the number of pixels in one vertical pixel column, so that the storage sections 20A and 20B can store signal charges for a frame in the entire sensor element. It is provided.

A first horizontal transfer section 22 receives signal charges from one end of each storage section and reads them out in the horizontal direction, and is composed of a horizontal CCD. Further, 23 is an overflow drain.

In the solid-state sensor and its driving method of the present inventor's earlier application, in the still photography mode, signal charges are simultaneously read out from the pixels 10 to 16 and transferred at high speed to the storage units 20A and 20B. During field 1, in which the signal charge of field A is read out via the horizontal transfer unit 22, the signal charge of field B in the storage unit 20B is read out via the horizontal transfer unit 22.
It is necessary to hold the L load as is. Therefore, it is not possible to apply the same driving pulse to the storage sections 20A and 20B to transfer the amount of charge, and it is necessary to apply the driving pulses at different timings. When the wiring between the electrodes has a four-layer structure in order to provide different drive pulses in this way, crosstalk between the electrodes may occur, making independent charge transfer difficult.

Therefore, the present invention provides an NT-type main body that can read out signal charges with a time difference of one field between the A-field vertical transfer section and the B-field vertical transfer section in the storage section without applying different driving pulses to the vertical transfer section and the B-field vertical transfer section. An object of the present invention is to provide an image sensor and a method for driving the same.

[Means and operations for solving the problem] In order to achieve the above object, the present invention utilizes the NT system CC shown in the above prior application [
1. The first electrode is provided on one side of each column of the vertical transfer section of the FI element and temporarily accumulates a total of 17 minutes of charge.
In addition to the storage section, a second storage section is provided on the other side of every other column of the vertical transfer section and temporarily stores charges for one field as a whole, and the odd numbered columns of the first storage section are provided. The TL electrode arrangement is different from the electrode arrangement for even-numbered columns, and the charge transfer direction is reversed between odd-numbered columns and even-numbered columns by the same driving pulse.

That is, according to the present invention, a photoelectric conversion section including a plurality of two-dimensional array pixels constituting one screen, a vertical transfer section provided one column on each side of each vertical pixel column of the photoelectric conversion section, and A transfer gate section that transfers signal charges generated in each pixel to a corresponding portion of the vertical transfer section; and a transfer gate section provided at an extension part of one end of each column of the vertical transfer section, and a transfer gate section that transfers signal charges generated in each pixel to a corresponding portion of the vertical transfer section; This device temporarily accumulates charges, and the electrode arrangement in the odd-numbered rows is different from the electrode arrangement in the even-numbered rows, so that the direction of charge transfer between the odd-numbered rows and the even-numbered rows is reversed by the same drive pulse. a first accumulating section, a second accumulating section provided at an extension of the other end of every other column of the vertical transfer section, and accumulating charges for one field as a whole; means for switching the phases of the drive pulses applied to the vertical transfer section and the drive pulses stored in the second storage section; A frame interline type solid-state imaging device is provided which has a horizontal transfer section for outputting an image (ejection signal).

According to the present invention, there is also provided a method for driving an interline solid-state image sensing device according to claim 1, which comprises <a) applying a transfer gate pulse to the transfer gate within a vertical blanking period; (b) transfer signal charges from a pixel corresponding to the field and a pixel corresponding to the B field to the vertical transfer section at the same time; A high frequency driving pulse is applied to transfer the A field signal charge in the vertical transfer section to the first storage section within the vertical blanking period in a short time, and also transfer the B field signal charge in the vertical transfer section to the first storage section. (C) After that, the data is transferred to the second storage section in a short period of time within the vertical blanking period;
The signal charge of the A field in the first storage F+'1 section is transferred to the horizontal transfer section by applying a driving pulse at a rate of 1.times.

(('') A horizontal driving pulse is applied to the horizontal transfer section, and the charge No. 73 of the A field transferred to the horizontal transfer section is transferred to the next vertical blanking JtA r:r+ as part of the video signal. (e) applying the control signal to means for respectively switching the phases of the drive pulses to reverse the direction of charge transfer in the vertical transfer section and the second storage section;

<f> A driving pulse having a frequency sufficiently higher than the horizontal synchronizing signal frequency is applied to the vertical transfer section and the first and second MFa sections to transfer the signal charge of the B field in the second storage section to the next vertical blanking period. (g) Applying a drive pulse to the first storage section at a rate of l times per horizontal synchronization signal period to transfer the first storage section to the first storage section via the vertical transfer section in a short period of time; (h) applying a horizontal driving pulse to the horizontal transfer section, and transferring the signal charge of the B field applied to the horizontal transfer section to the horizontal transfer section; (h) applying a horizontal drive pulse to the horizontal transfer section; Further, there is provided a method for driving a frame interline type solid-state imaging device, which outputs the image signal as part of the image signal before the next vertical blanking period.

Further, according to the present invention, a photoelectric conversion section including a plurality of two-dimensional array pixels constituting one screen, and a vertical transfer section provided one column on each side of each vertical pixel column of the photoelectric conversion section,
a transfer gate section that transfers the signal charge generated in each pixel to a corresponding part of the vertical transfer section; and a transfer gate section that is connected to one end of each column of the vertical transfer section and corresponds to one vertical pixel column.
a conversion circuit that combines signal charges from the vertical transfer sections of the columns into one column; and a conversion circuit that is provided on the output side of the conversion circuit and temporarily stores charges for one field from the vertical transfer sections as a whole. The first storage section has a configuration in which the electrode arrangement of the odd number columns is different from the electrode arrangement of the fA number columns, and the direction of charge transfer between the odd number columns and the even number columns is reversed by the same drive pulse, and the vertical transfer section. a second storage section that is provided at an extension of the other end of every other column and stores charges for one field as a whole; a drive pulse that is applied to the vertical transfer section in accordance with a control signal; and a horizontal transfer section connected to an end of each column of the first storage section for outputting the signal charge from the first storage section as a video signal. An interline solid-state image sensor is provided.

[Example] Hereinafter, Example 6 of the present invention will be explained with reference to the drawings.
The figure shows only a part of one vertical pixel column (500"f) of the first embodiment of the one-piece CCD sensor according to the present invention. In FIG. 1, 10 to 1G are two-dimensionally arranged. 18A and 18B are vertical transfer units provided one column on each side of each vertical pixel column. In response to the transfer gate pulse, the A field and B field signal charges from each of the pixels 10 to 1G are transferred to the vertical transfer section +8.+8. in the vertical blanking period separately as shown by the arrows via the transfer gate section (not shown). 20A and 20B are first storage units provided in extensions of the vertical transfer units 18A and +8B, respectively, and each vertical transfer unit 18A and 18B and each first storage unit are connected to each vertical column. In Figure 1, which consists of one CCD in a strawberry, the first storage section 20A, 2
0B is M, which is half the number of pixels in one vertical pixel column, so that signal charges for one frame can be accumulated in the entire image sensor.
In this embodiment, each vertical transfer section 18A, 18B has two product sections.
Consisting of 50 stages of CCD, the first storage section 20A, 2
0B etc. each consists of 250 stages of CCO. In the following description, the CCD columns connected to the two left and right vertical transfer units corresponding to the l vertical pixel column will be referred to as storage fIt units.

The area of the entire similar CCD array is sometimes referred to as the storage area or simply the storage area. 22 each first storage section 20A;
This is a horizontal transfer section that receives signal charges from one end of 20B and reads them out in the horizontal direction, and is composed of a horizontal CCD.

Every other column in the vertical transfer sections +8A and 18B, that is, in this embodiment, the first [21! Even numbered row 1 when viewed from the center left side
8811! ! is the above-mentioned first storage section 20 B Ill, 1
It also extends in the direction opposite to the end of 1, and as a whole, 1
It constitutes a second M product section 24 that temporarily stores charges for a field. The number of stages in this second storage section 24 is also half the number of pixels in one pixel column, that is, 250 stages in this column.

Now, assuming that the number of pixels in one vertical column among all the two-dimensionally arranged pixels of the 111th TA image element is <500 as described above, the vertical transfer units 18A and 18B have 250 stages (bits). Similarly, the first accumulation sections 20A and 20B and the second accumulation section 24 have 250 stages (bi-soto), that is, the first accumulation sections 2OA and 20B temporarily store signal charges for one frame as a whole. The second storage section 24 can temporarily store signal charges for one field as a whole.

In Fig. 1, φ94. φv2 and φv3 are respectively the second storage V
T? J24, vertical transfer section +8A18B first storage section 2
It shows the drive pulses applied to 0A and 20B.

As shown, these driving pulses φ,1, φV2−φV
3 is a no-phase one.

30. 31 is a phase switching circuit, which can output φ1 and φ4 or φ2 and φ3 among the four-phase pulses IV2 φ to φ4 of each drive pulse φ, φ, by swapping them according to a predetermined control signal. It is something.

FIG. 2 is a diagram schematically showing the connection status of the electrodes of vertical transfer sections +8A and 18B, and each vertical transfer section 18A and +8B
4-phase drive pulses φ , φ , φ U, every other row of...
φ4 is given in different ways. That is, for example, when looking from the left end in Figure 81, the odd-numbered rows of electrodes have φ, φ, φ2, φ, φ, φ1, . . . from the top in the figure.
φ and φ4 and φ2 and φ3 are alternately reversed so that driving pulses are applied in the order of φ, φ, φ3, φ, φ, and φ4 from the top of the figure to the even-numbered electrodes. It is wired in such a way that Therefore, as shown in No. 1121, the four-phase driving pulse φV2 is applied to the vertical transfer section 18.
If iL is applied to A and 18B, then the charge in the odd numbered column +8A will be transferred downward in the figure, while the charge in the even numbered column 18B will be transferred upward in the figure.

3rd (2I is vertical transfer section +8A shown in 2nd U!i,
This is a diagram showing the connection status of the electrodes of 18B, in which the upper and lower two layers are connected to the photodiode PD constituting each pixel in a vertically alternating manner as shown by solid lines and dotted lines. . Therefore, by applying the same driving pulse, the charge transfer direction changes every other vertical column.

Next, the movement of the first embodiment shown in FIG. 1 will be explained separately into an electronic still mode and a normal movie mode. First, in the case of the electronic still mode, when using the electronic shutter, it is necessary to sweep out excess charges in both the A and B fields at appropriate timing in order to control the exposure and accumulation time of the photoelectric conversion section. For this reason, the signal charge of each pixel 10 to 1G is transferred to the vertical transfer section 18A through a transfer gate (not shown).
This surplus charge is discarded to the substrate via a vertical overfloat input (not shown) for the 0th order, which is simultaneously read out field by field to the BIB. At this time, the upper and lower first storage sections 20A,
The charges in 20B and the second storage section 24 are also discarded. The vertical transfer section +8A, 18 is exposed to light for a predetermined time and accumulated through the signal charge 3 transfer gate of 81 pixels 10 to 1G.
B simultaneously read each field.

Next, as the drive pulses φ, φ, φ, the horizontal opening VI
V2 V3 +! Applying a vertical drive pulse with a frequency sufficiently higher than that of the Jl tz number, the A field signal goes downward, that is, from the vertical transfer section +8A to the odd column 20A of the second storage section.
On the other hand, the B field signal is transferred upward, that is, from the vertical transfer section 18B to the first Mf1ff section 24 at high speed in a short time. When this high speed transfer is completed, the A field signal charge is transferred to the odd column 18A of the first M product section. , B field signal charges are in the second storage section 24. Reading from each pixel 10 to 1G and the above-mentioned high-speed transfer are performed in a short time within the vertical blanking period.

When the vertical blanking period ends and the video signal period begins, the vertical drive pulse of the horizontal synchronizing signal period and φV3 are applied to the first storage sections 20A and 20B, and the A in the odd-numbered column 20A of the first storage section is applied via the horizontal CCD 22. The field charge is read out for each IH as part of the video signal.

During this period, the charges of the B field are held as they are in the second storage section 24. When all the charges No. 13 of the A field are read out and the next vertical blanking period begins, the charges of the B field are held as they are in the second storage section 24. The transfer units 18A, +8B, then the vertical transfer units 18A, 188 and the first storage units 20A, 2
At 0B, high frequency drive pulses φ, φ, similar to those described above are applied.
φ Give each. This and V+ V2
A control signal is sent to the four-phase switching circuits 30 and 31 for νJ, and φ1 and φ and φ2 and φ are exchanged and output. Therefore, ti of the B field is transferred downward at high speed to the second storage section 2.
4 to the gA sequence 20B of the first storage section. Thereafter, the driving pulse φV3 to the first storages M20A and 20B is set to have a horizontal synchronizing signal period, and the charge of the B field is read out as part of the video signal for each IH via the horizontal transfer CCD 22.

Figure 4 is a timing chart 1 showing the operation of the electronic still mode. transfer department.

The downward arrow also indicates downward transfer.

IH, 20H... is the elapsed time due to the horizontal synchronization signal from the first sweep of the overflow drain I＼rr:I
3 I'll show you.

Note that the timing of sweeping out the remainder and one charge can be adjusted as appropriate depending on the desired shutter speed.
A shutter speed of 100 to +/20008- can be selected. The fastest shedding speed is determined by the time required for sweeping out.

Note that φV3 is similarly applied to the odd and even columns of the first storage section, and the charges are transferred only in the direction of the horizontal transfer section 22. In order to prevent unnecessary charges from entering the horizontal transfer section 22, it is preferable to provide a gate.

Next, the normal movie mode will be explained.

In the l-bee mode, the signal charges of the A field and the signal charges of the B field are not read out simultaneously from the pixels 10 to 16, but with a time difference of l field period (1/GO seconds). During the vertical blanking period, the signals i and W of field A are read out to the vertical transfer section +8A, and a signal with a frequency sufficiently higher than the horizontal synchronization signal is applied using the drive pulse φ φ and Lv2/v3 to transfer the signal charge in the vertical transfer section +8A. and downward, that is, to the odd-numbered column 20A of the first storage section.Next, similarly to the electronic still mode described above, a driving pulse φV3 of the horizontal synchronizing signal period is applied to the first storage sections 20A and 20B to collect the charge of the A field. During the 0th vertical blanking period read out via the horizontal transfer CCD 22 as part of video No. 13, the B field signal charges are read out to the vertical transfer section 188 and the primary high speed drive pulses are applied to φV2, φ, 3. After being transferred downward at high speed like the A field, it is read out for each IH. Therefore, in the normal movie mode, the second storage section 24 is not used and its drive pulse φV1 is unnecessary.

FIG. 5 is a diagram showing a second embodiment of the solid-state wI image element of the present invention. This embodiment differs from the first embodiment in that the first storage section consists of only one column of vertical CC02G per one vertical pixel column instead of two columns.
The horizontal paths of the second storage section 24 are exactly the same as those in the first embodiment, and the charges from the ends of the two columns of vertical transfer sections 18A and 18B are collected into one column via the conversion circuit 28 and transferred to the second storage section 24. 1 storage unit vertical CCD 26. Regarding the conversion circuit 28 that combines two rows of signal charges into one row, the 1984 Television Society Conference Preliminary Lectures No. 5
pp. 7-58 "Two-line readout CCD" by Norio Koike et al.
tji image element".

In this second embodiment, the first drive pulse φ,3 is applied.
The number of vertical CCD columns in the MM section is half that of the first embodiment.

Therefore, the structure can be simplified and costs can be reduced.

In each of the above embodiments, both the first M product section 20A, 20B or 26 and the second M product section 24 are four-phase driven;
By using phase drive, the chip size can be reduced. As a method for changing the transfer direction using two-phase drive, the reversible two-phase CCD technology described on page 98 of ``Basics of RCCO'' (written by Tsukamoto, published by Ohmsha) can be used.

[Effects of the Invention] As is clear from the detailed explanation, since two storage sections are provided and the connection of the t-pole of the vertical transfer section is changed for each column, the signals of both fields can be controlled in the electronic still mode. After reading charges independently and simultaneously to two columns of vertical transfer sections, when reading them out to the outside with a time difference of one field period between them, the same drive is applied to the A-field vertical transfer section and the B-field vertical transfer section. By applying a pulse, the signal charge of the A field is transferred to the first storage section, and the signal charge of the B field is transferred to the second storage section located in the opposite direction to the first storage section.
The signal charges of the B field can be transferred to the M product section, and thus the signal charges of the B field can be read out from the 7 tables held in the second storage section for one field period. Also, 2 corresponding to 1 pixel column
By providing a conversion circuit that collects the signal charges from the vertical transfer sections of the columns into one column, the number of vertical 000 columns in the first accumulation section can be the same as the number of vertical pixel columns, and the horizontal transfer can be easily done. It is possible to reduce the cost l~.

[Brief explanation of the drawing]

FIG. 1 shows the first embodiment of the solid-state image sensor and its driving method according to the present invention.
A diagram showing an embodiment, 2I2I is T of the vertical transfer section in FIG.
3 is a diagram schematically showing the connection between Lfffi, 4I21 is a timing chart showing the operation of the electronic still mode in the first embodiment, and 5I2I is the solid-state imaging of the present invention. A diagram 612I showing a second embodiment of the device and its driving method is a diagram showing the solid-state imaging device disclosed in the applicant's previous application. 10 to 16... Pixels, +8A, +8B... Vertical transfer section. 2OA, 20B, 26...first storage section 22...
・Horizontal transfer section, 23... overflow drain,
24... Second storage unit, 28... Conversion circuit, 30
．． 31... Phase switching circuit. Inventor Shinozaki
Shun Patent Author, Representative of Victor Japan Co., Ltd.
Person Patent Attorney Bin Masataka Figure Figure 1

Claims (3)

[Claims] (1) A photoelectric conversion unit consisting of a plurality of two-dimensional array pixels constituting one screen, a vertical transfer unit provided on each side of each vertical pixel column of the photoelectric conversion unit, and A transfer gate section that transfers the generated signal charge to a corresponding portion of the vertical transfer section;
This device temporarily stores charges for a frame, and the electrode arrangement in odd-numbered columns is different from the electrode arrangement in even-numbered columns, so that the direction of charge transfer between odd-numbered columns and even-numbered columns is changed by the same driving pulse. A first storage section having an opposite configuration, a second storage section provided at the extension of the other end of every other column of the vertical transfer section and storing charge for one field as a whole, means for switching the phases of the drive pulse applied to the vertical transfer section and the drive pulse applied to the second storage section, respectively; and means connected to an end of each column of the first storage section and a signal from the first storage section; A frame interline type solid-state image sensor that has a horizontal transfer section for outputting charges as a video signal. (2) A method for driving a frame interline type solid-state imaging device according to claim 1, comprising: (a) applying a transfer gate pulse to the transfer gate within a vertical blanking period to select pixels corresponding to the A field and the B field; simultaneously transfer signal charges from pixels corresponding to the vertical transfer section to the vertical transfer section, and (b) then apply a driving pulse of a frequency sufficiently higher than the horizontal synchronization signal frequency to the vertical transfer section and the first and second storage sections. A in the vertical transfer section
Field signal charges are transferred to the first storage section in a short time within the vertical blanking period, and field B signal charges in the vertical transfer section are transferred to the second storage section in a short time during the vertical blanking period. (c) After that, the first storage section receives one signal per horizontal synchronization signal period.
(d) Applying a horizontal drive pulse to the horizontal transfer section, and transferring the signal charge of the A field in the first storage section to the horizontal transfer section by applying a drive pulse at a rate of (e) outputting the signal charge of the field A as a part of the video signal before the next vertical blanking period; and (f) applying a driving pulse of a frequency sufficiently higher than the horizontal synchronizing signal frequency to the vertical transfer section and the first and second storage sections to transfer the charge in the second storage section. (g) transfer the signal charge of the B field to the first storage section via the vertical transfer section in a short time within the next vertical blanking period; (g) transfer the signal charge to the first storage section once per horizontal synchronization signal period; (h) Applying a horizontal drive pulse to the horizontal transfer section to transfer the signal charge of the B field applied to the first storage section to the horizontal transfer section by applying a drive pulse at a rate of A method for driving a frame interline type solid-state image sensing device, wherein the signal charges of the B field transferred to the above are further output as part of the video signal before the next vertical blanking period. (3) a photoelectric conversion section consisting of a plurality of two-dimensional array pixels constituting one screen; a vertical transfer section provided on each side of each vertical pixel column of the photoelectric conversion section; a transfer gate section that transfers the generated signal charge to a corresponding portion of the vertical transfer section; and a transfer gate section that transfers the generated signal charge to a corresponding portion of the vertical transfer section; a conversion circuit that collects signal charges into one column; and a conversion circuit that is provided on the output side of the conversion circuit and temporarily stores charges for one field from the vertical transfer section as a whole, and the electrode arrangement of the odd numbered columns is an even number. a first storage section having a structure that is different from the electrode arrangement of the columns and in which the direction of charge transfer is opposite between odd and even columns by the same driving pulse; and every other column of the vertical transfer section. provided at the extension of the other end of the
a second storage section that stores charges for one field as a whole; means for switching the phases of the drive pulses applied to the vertical transfer section and the drive pulses applied to the second storage section according to a control signal; A frame interline type solid-state imaging device having a horizontal transfer section connected to an end of each column of storage sections for outputting signal charges from the first storage section as a video signal.