JPH02149121A - Negative impedance circuit - Google Patents
Negative impedance circuitInfo
- Publication number
- JPH02149121A JPH02149121A JP30295588A JP30295588A JPH02149121A JP H02149121 A JPH02149121 A JP H02149121A JP 30295588 A JP30295588 A JP 30295588A JP 30295588 A JP30295588 A JP 30295588A JP H02149121 A JPH02149121 A JP H02149121A
- Authority
- JP
- Japan
- Prior art keywords
- impedance
- negative
- circuit
- nic
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 238000001152 differential interference contrast microscopy Methods 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 5
- 230000002457 bidirectional effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 206010000060 Abdominal distension Diseases 0.000 description 1
- 208000024330 bloating Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、双方向増幅器、イコライザ回路、ジャイレー
タ回路等に用いて好適な負性インピーダンス回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a negative impedance circuit suitable for use in bidirectional amplifiers, equalizer circuits, gyrator circuits, and the like.
（従来の技術）
負性インピーダンス回路は、抵抗、容量、インダクタン
ス等の回路素子のように、正のインピーダンスを持つも
のとは反対の働きをする回路である。その負性インピー
ダンス回路は、−数的には負性インピーダンス変換器（
Ｎｅｇａｔｉｖｅ ＩｍｐｅｄａｎｃｅＣｏｎｖｅｒｔ
ｅｒ ；以下ＮＩＣと略記する）によってインピーダン
スを負性変換して得ている。(Prior Art) A negative impedance circuit is a circuit that functions in the opposite way to circuit elements such as resistors, capacitors, and inductances that have positive impedance. The negative impedance circuit is -numerically, a negative impedance converter (
Negative Impedance Convert
er; hereinafter abbreviated as NIC), the impedance is obtained by negative conversion.
（発明が解決しようとする課題）
そのようなインピーダンスの負性変換の具体的な構成と
して、第３図の如く回路の一端が接地された接地型負性
インピーダンス回路や、第４図の如くある回路素子だけ
をフローティングで負性インピーダンス化した回路（昭
和５４年特許願第８６６５２号）が従来から知られてい
る。(Problem to be Solved by the Invention) Specific configurations for such negative impedance conversion include a grounded negative impedance circuit in which one end of the circuit is grounded as shown in Figure 3, and a grounded negative impedance circuit as shown in Figure 4. A circuit (Patent Application No. 86652 of 1972) in which only circuit elements are made floating and has a negative impedance has been known.
このような従来の回路では、１つの回路素子ごとに１つ
のＮＩＣを接続して負性インピーダンス化するから、回
路網全体では多くのＮＩＣが必要となる場合がしばしば
あり、また多数のＮＩＣがあるとそれらは相互に干渉し
易いし、能動素子による雑音の増加が大きい。In such conventional circuits, one NIC is connected to each circuit element to create a negative impedance, so many NICs are often required for the entire circuit network, and there are many NICs. They tend to interfere with each other, and the noise caused by active elements increases significantly.
（課題を解決するための手段）
本発明によれば、負性変換すべきインピーダンス回路網
と、複数のＮＩＣとからなり、そのインピーダンス回路
網の各端子に前記ＮＩＣの一方の端子をそれぞれ接続す
ることにより、前記ＮＩＣの他方の端子に、前記インピ
ーダンス回路網のもつインピーダンス値を負性変換した
インピーダンスを等価的に形成する負性インピーダンス
回路を得ることができる。(Means for Solving the Problems) According to the present invention, the impedance network to be negatively converted is comprised of a plurality of NICs, and one terminal of the NIC is connected to each terminal of the impedance network. By doing this, it is possible to obtain a negative impedance circuit that equivalently forms an impedance obtained by negatively converting the impedance value of the impedance network at the other terminal of the NIC.
（作 用°）
本発明は、単に一つの回路素子を負性インピーダンス化
する方式とは異なり、ある回路網全体を負性インピーダ
ンス化する方式の回路を提供するものであり、個々に負
性インピーダンス化する為のＮＩＣ素子の数を減少せし
め、多数のＮＩＣ相互の干渉、能動素子による雑音信号
の増加を最小限にすることが可能となる。(Function°) The present invention provides a circuit in which an entire circuit network is made into a negative impedance, unlike a method in which only one circuit element is made into a negative impedance. It is possible to reduce the number of NIC elements for NICs, thereby minimizing interference between a large number of NICs and an increase in noise signals due to active elements.
（実施例） 第１図は本発明の一実施例を示す構成図である。(Example) FIG. 1 is a block diagram showing an embodiment of the present invention.
この実施例において、１００は抵抗、容量、インダクタ
ンス等の回路素子によって構成されるインピーダンス回
路網である。インピーダンス回路網１００はｎ個の端子
（１５〜ｎ５）と１個の接地端子６とを有する。そめイ
ンピーダンス回路１００の回路定数はインピーダンス行
列を用いて、式（１）の如く表わすものとする。In this embodiment, 100 is an impedance network constituted by circuit elements such as resistors, capacitors, and inductances. Impedance network 100 has n terminals (15 to n5) and one ground terminal 6. The circuit constant of the impedance circuit 100 is expressed as shown in equation (1) using an impedance matrix.
ｎ５）にそれぞれ次の特性をもっＮＩＣ（１０１〜１０
ｎ）の一端（１３〜ｎ３）を接続する。NICs (101 to 10
Connect one end (13 to n3) of n).
このとき、ＮＩＣ（１０１〜１０ｎ）の他端（１１〜ｎ
ｌ）には式（１）、（２）より、次の等価的な回路定数
が表わきれる。At this time, the other end (11-n) of the NIC (101-10n)
From equations (1) and (2), the following equivalent circuit constant can be expressed for l).
ダンス回路網１００のインピーダンスがすべて負性変換
されて表われることになる。All the impedances of the dance network 100 appear as negative transforms.
尚、負性変換する為のＮＩＣ（１０１〜１０ｎ）を構成
する方法には種々あるが、例として、第２図（ａ）、（
ｂ）に示す差動増幅器１と抵抗２．３により構成した回
路を示す。There are various methods of configuring the NIC (101 to 10n) for negative conversion, but as an example, Fig. 2 (a), (
A circuit constructed from the differential amplifier 1 and resistors 2.3 shown in b) is shown.
第２図（ａ）、（ｂ）とも端子１１と１３間の電圧、電
流の関係は、抵抗２，３の抵抗値が等しく、差動増幅器
１の利得が充分高いとすればｖ、″ｖ、 ・・・・
・・・・・（４）１ 、 ！ ＋ ｉ 。In both FIGS. 2(a) and 2(b), the relationship between the voltage and current between terminals 11 and 13 is v, "v" if the resistance values of resistors 2 and 3 are equal and the gain of differential amplifier 1 is sufficiently high. , ・・・・・・
...(4)1,! +i.
となり、式（２）の条件を満足するＮＩＣとなる。Therefore, the NIC satisfies the condition of equation (2).
第２図（ａ）、（ｂ）の違いは差動増幅器１の安定条件
による差異であり、ＮＩＣの両端に接続されるインピー
ダンス値の大小により、安定する方の回路を適宜に選択
して用いる。The difference between Fig. 2 (a) and (b) is due to the stability conditions of the differential amplifier 1, and depending on the magnitude of the impedance value connected to both ends of the NIC, select and use the circuit that is more stable as appropriate. .
（発明の効果）
以上に述べた如く、本発明によれば任意のインピーダン
ス値をもったＤ路網全体を最小のＮＩＣ素子を使用する
ことによって負性インピーダンス化することができる。(Effects of the Invention) As described above, according to the present invention, the entire D path network having an arbitrary impedance value can be made into a negative impedance by using the minimum NIC element.
負性インピーダンス回路網は、単に一つの負性インピー
ダンス素子とは異なり、例えばインピーダンスマツチン
グの可能な双方向増幅器やイコライザ回路やジャイレー
タ回路等幅広い応用が可能となる。Unlike a single negative impedance element, the negative impedance network can be used in a wide range of applications, such as bidirectional amplifiers capable of impedance matching, equalizer circuits, and gyrator circuits.
第１図は本発明の一実施例の構成図、第２図（ａ）、（
ｂ）は第１図実施例で構成要素として用いられるＮＩＣ
素子の回路図、第３図は従来の接地型負性インピーダン
ス回路の構成図、第４図は従来のブローティング型負性
インピーダンス回路の構成図である。
１・・・差動増幅器、２．３・・・抵抗器、１１〜１５
．２１〜２５．〜ｎ１〜ｎ５・・・入出力端子、１００
・・・インピーダンス回路網、１０１〜１０ｎ・・・Ｎ
ＩＣ素子。
代理人 弁理士 本 庄 伸 介Figure 1 is a configuration diagram of an embodiment of the present invention, Figures 2 (a), (
b) is the NIC used as a component in the embodiment of FIG.
The circuit diagram of the element, FIG. 3 is a block diagram of a conventional grounded negative impedance circuit, and FIG. 4 is a block diagram of a conventional bloating type negative impedance circuit. 1...Differential amplifier, 2.3...Resistor, 11-15
．． 21-25. ~n1~n5...input/output terminal, 100
... Impedance network, 101-10n...N
IC element. Agent Patent Attorney Shinsuke Honjo
Claims (1)
されるインピーダンス回路網と、このインピーダンス回
路網の各端子に一方の端子を接続された複数の負性イン
ピーダンス変換器とを含み、これらの負性インピーダン
ス変換器の他方の端子に、前記インピーダンス回路網の
もつインピーダンス値を負性変換したインピーダンスを
等価的に形成することを特徴とする負性インピーダンス
回路。The negative impedance conversion method includes an impedance network constituted by circuit elements such as resistance, capacitance, and inductance, and a plurality of negative impedance converters having one terminal connected to each terminal of this impedance network. A negative impedance circuit, characterized in that an impedance obtained by negatively converting the impedance value of the impedance network is equivalently formed at the other terminal of the impedance circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63302955A JP2666860B2 (en) | 1988-11-30 | 1988-11-30 | Negative impedance circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63302955A JP2666860B2 (en) | 1988-11-30 | 1988-11-30 | Negative impedance circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02149121A true JPH02149121A (en) | 1990-06-07 |
| JP2666860B2 JP2666860B2 (en) | 1997-10-22 |
Family
ID=17915162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63302955A Expired - Lifetime JP2666860B2 (en) | 1988-11-30 | 1988-11-30 | Negative impedance circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2666860B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007122605A (en) * | 2005-10-31 | 2007-05-17 | Fujitsu Ltd | Impedance circuit and power supply device |
| US8159767B2 (en) | 2008-12-10 | 2012-04-17 | Kabushiki Kaisha Toshiba | Repeatable runout evaluation method for a stamper |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610730A (en) * | 1979-07-09 | 1981-02-03 | Nec Corp | Negative impedance circuit |
-
1988
- 1988-11-30 JP JP63302955A patent/JP2666860B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610730A (en) * | 1979-07-09 | 1981-02-03 | Nec Corp | Negative impedance circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007122605A (en) * | 2005-10-31 | 2007-05-17 | Fujitsu Ltd | Impedance circuit and power supply device |
| US8159767B2 (en) | 2008-12-10 | 2012-04-17 | Kabushiki Kaisha Toshiba | Repeatable runout evaluation method for a stamper |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2666860B2 (en) | 1997-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Senani | Novel mixed-mode universal biquad configuration | |
| US4779056A (en) | Active filter | |
| JPH02149121A (en) | Negative impedance circuit | |
| CA1149478A (en) | Bandstop filters | |
| KR960012697A (en) | Circuit device with controllable transmission characteristics | |
| JPH0262101A (en) | Dielectric filter | |
| Chang et al. | Universal current-mode filters employing CFCCIIps | |
| JP2712923B2 (en) | SAT phase shift circuit | |
| Senani | CFOA-based state-variable biquad and its high-frequency compensation | |
| Sladok et al. | Systematic design of pseudo-differential frequency filter | |
| JP2001251164A (en) | Active inductance circuit, two-terminal element active inductance circuit and symmetric four-terminal active inductance circuit | |
| JPH10327036A (en) | Output circuit for d/a converter | |
| RU2019023C1 (en) | Active rc filter | |
| US20050138436A1 (en) | AC coupling network with variable attenuation | |
| US4464637A (en) | Semi-active notch filter | |
| SU1343547A1 (en) | Active resistance-capacitance-phase circuit | |
| KR20020003724A (en) | Active Lowpass Filter for Higher frequency wave | |
| JPH01321716A (en) | Active filter | |
| JPS59183521A (en) | Active rc filter | |
| JPS6052107A (en) | Two-way active filter circuit | |
| SU995277A1 (en) | Active phase stage of the third order | |
| Higashimura | Brief communication. Active-R realization of current-mode low-pass filters | |
| JPH0467367B2 (en) | ||
| SU815868A2 (en) | Broad-band active rc-filter | |
| Paul et al. | Transadmittance mode universal filter based on MOCCCII |