JPH02146964A - Output controller for inverter - Google Patents

Abstract

PURPOSE:To improve the accuracy of the waveform of a PWM signal by using the clear signal of a counter generating a carrier signal as the latch signal of a phase voltage data. CONSTITUTION:An output controller for an inverter is composed of a micro-computer 1 as a control means having a ROM 1a and determining phase voltage and a gate circuit 2 outputting PWM signals to each switching element of the inverter. The gate circuit 2 consists of an updown counter 22 generating a carrier signal, an F/F 23, latch circuits 24a-24d, comparators 25a-25c generating PWM signals, and a data selector 26 varying the output destinations of the PWM signals. Accordingly, the timing of the selective changeover of the carrier signal, a phase voltage data and the PWM signals coincides, thus improving the accuracy of a waveform.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an output control device for an inverter that drives, for example, a compressor motor, and in particular,
The present invention relates to an output control device that is controlled by a WM (pulse width modulation) signal.

(Prior Art) FIG. 3 is a functional block diagram showing the configuration of an output control device for an inverter of this type, which is disclosed in, for example, Japanese Patent Laid-Open No. 1375/1983. In the figure, 1 is memory (ROM) l
It is a microcomputer (hereinafter referred to as a microcomputer) that has a microcomputer a, a multiplier circuit, a register, etc., and a memory la stores frequency data (frequency data of the carrier signal) and basic voltage data input to the microcomputer 1. Designation of the output destination of the data by the microcomputer 1 (designation of the rotation direction, that is, designation of the switching element of the inverter)
A control means is configured to perform the following. 2 is a switching element for each phase of the inverter (
(not shown) is controlled by a PWM signal.
The structure is as follows. That is, 22 is an up/down counter that generates a carrier signal, 23 is a flip-flop (F/F), and 24a, 24b.

24c is a latch circuit that latches each data; 25a, 2
5b and 25c are comparators that compare the carrier signal and phase voltage data and output a PWM signal, 12 and 13 are flip-flops, and 26 is a data selector that changes the cutting edge of the PWM signal.

FIG. 4 is an explanatory diagram showing the principle of generating a PWM signal to the inverter. In this example, a symmetrical three-phase AC inverter is shown, and therefore the memory 1a has data only for the 60° section, and the other sections are made compatible by changing the cutting edge. That is, the microcomputer 1 generates a carrier signal that determines the output frequency, compares this carrier signal with the voltage data of each phase (U, V), and outputs a PWM signal according to the comparison result.
The switching elements of each phase provided in the inverter are controlled by the WM signal, and AC power of a desired frequency and voltage is output to a motor or the like. In the figure, PO, P3. P4+
Each point of Pt is a point where the U phase is inverted, PI, P2. P
5. Each point of Pa is a point where the V phase is reversed, and T+ (i = 1.2, 3. . . . ”J is P l−
It shows the time from point 1 to point PI. Then, in the memory 1a of the microcomputer 1, the switching state and time data ("r+) of each phase at the above 23 points,
is stored.

FIG. 5 is a flowchart showing the operation of the conventional circuit shown in FIG. 3. First, as the initialization of microcontroller 1,
Carrier cycle data (frequency data) is sent to latch circuit 2
4a, the voltage data of X is sent to the latch circuit 24b, and the voltage data of Y is sent to the latch circuit 24b.
The pressure data are respectively written to the latch circuits 24c. Then, at the point CI in FIG. Value and counter 22
An interrupt request (INTI) is sent to the microcomputer 1 at the point where the carrier value outputted from the microcomputer 1 matches the carrier value outputted from the microcomputer 1, and the counter 22 starts counting down and enters the interrupt processing of the flowchart in FIG. 5 (step 500).

When the interrupt process is entered, the pointer of the basic voltage data in the memory la is calculated depending on the number of the 60' interval at which the time point is (step 501). Next, phase voltage data X is calculated from the contents of the memory 1a indicated by the pointer and the voltage parameter Vp (step 502). Similarly, phase voltage data Y is calculated from the contents of the memory 1a indicated by adding a fixed value to the above pointer and the voltage parameter Vp (step 503).

Next, at point C2 in FIG. 4, that is, at the point where the up/down counter 22 in FIG. start. Then, when there is the interrupt request INT2 (step 504),
(7) Output the data to the boat (step 50)
5), output the data of Y to the boat (step 506)
, writes those data to the latch circuits 24b and 24c. Next, it is determined whether the 60° interval has ended (step 507), and if it has not ended, an interrupt is permitted (step 508), and the interrupt processing is exited (step 509). If the 60'' interval has ended in step 507, the number of carriers is calculated from the input frequency and voltage commands (step 510), the carrier period (step 511), and the voltage parameter Vp (step 5).
12). At this point, the interrupt request (IN
TI) is set, so the interrupt request (INTI)
clear step 513), interrupt request (INT2
), and then outputs the data of X to the boat (step 515) and outputs the data of Y to the boat (step 516).

0, X, Y, I (O) is assigned to which phase of U, V, W (7) is selected (step 5).
17) The carrier period calculated above is transferred to the latch circuit 24a.
(step 518), then step 508
Move to.

Here, the interrupt request (INT2) is sent in step 504 above.
After checking , it takes a time of 1.5 seconds to output the phase voltage data Y in step 506, that is, from the lowest point of the triangular wave carrier signal to the end of outputting the phase voltage data. Similarly, after checking the interrupt request (INT2) in step 514, a time t2 is required until the carrier cycle is output in step 518. Also, interrupt requests (TNTI
) until the interrupt request (INT2) is input, that is, from point C1 to point 02 in Figure 4, the interrupt processing cannot be exited, and by the end of the 60° interval,
From the time of inputting an interrupt request (INTI) in step 500, through calculation of the number of carriers in step 510, etc., to step 509.
Until the interrupt processing ends at
．． Five times as much time is occupied by interrupt processing.

(Problem to be Solved by the Invention) Since the conventional inverter output control device is configured as described above, it is possible to output the lowest point of the carrier signal (switching point from down-count to up-count) and phase voltage data. There is a timing discrepancy, which makes it difficult to output short pulse signals, reducing the waveform accuracy of the PWM signal, and increasing the carrier frequency requires the use of an expensive microcontroller with fast processing speed. There was a problem. Also, after the interrupt request from lNTl to INT2, the interrupt processing cannot be exited until each data is output to the microcontroller's port, so the microcontroller's function is limited to only PWM signal output regardless of the carrier frequency.
There is a problem that the microcomputer is occupied by more than 0%, and the load of arithmetic processing on the microcomputer is heavy, and the microcomputer cannot perform other processing during that time.

This invention was made to solve the above problems, and can improve the waveform precision of the PWM signal, reduce the computational processing load on the microcomputer, be inexpensive, and increase the processing capacity of the microcomputer. The first objective is to obtain an inverter output control device that can perform the following steps.

(Means for Solving the Problems) An inverter output control device according to the present invention controls the switching elements of each phase provided in an inverter using a pulse width modulation signal, and outputs alternating current at a desired frequency and voltage. In an output control device for an inverter, the control means determines a phase voltage from frequency data, basic voltage data, and output voltage parameters and specifies an output destination of the data, and a control means for determining a frequency of the pulse width modulation signal. a counter that generates a carrier signal, a comparator that compares the carrier signal and phase voltage data to generate a navigation pulse width modulation signal, and a gate circuit that has a data selector that changes the output destination of the pulse width modulation signal. ,
The phase voltage data is latched by the clear signal of the counter and inputted to the comparator.

(Function) In the inverter output control device of the present invention, the clear signal of the counter that generates the carrier signal is used as the latch signal of the phase voltage data, so the timing of selection switching of the carrier signal, phase voltage data, and PWM signal is matched. , the waveform accuracy of the PWM signal is improved. Further, the control means can exit from the interrupt processing immediately after processing the phase voltage data, etc., and can perform other processing (processing other than PWM signal generation).

〔Example〕

FIG. 1 is a functional block diagram showing the configuration of an inverter output control device according to an embodiment of the present invention, and the same reference numerals as in FIG. 3 indicate the same components. In the figure, 1 is a microcomputer that constitutes a control means that determines the phase voltage from frequency data, basic voltage data, and output voltage parameters, and specifies the output destination of the data. It has a memory (ROM) la for storing data. 2 is a gate circuit that outputs a PWM signal to each switching element of an inverter (not shown), and includes an up/down counter 22, a flip-flop 23. Latch circuit 2
4a to 24d, comparators 25a to 24C1 that generate PWM signals by comparing the carrier signal and phase voltage data in the memory la, and a data selector 26 that changes the output destination of the PWM signals. Data from the corresponding microcomputer 1 is input to one input terminal of each of the comparators 25a to 25c, and the value from the counter 22 is input to the other input terminal.
Each phase voltage data is latched by the clear signal and inputted to the comparators 25a to 25c.

Next, the operation will be explained according to the flowchart shown in FIG.

The principle of PWM signal generation is explained in the fourth section mentioned above.
The explanation will be based on the explanatory diagram of the figure.

First, to initialize the microcomputer 1, carrier cycle data is output to the latch circuit 24a, X data to the latch circuit 24b, Y data to the latch circuit 24c, and a select signal to the latch circuit 24d. Further, the counter 22 is cleared after the up or down operation and outputs a latch signal. Thereafter, the counter 22 goes up and down according to the latched carrier cycle data and generates a carrier signal. Then, the microcomputer 1 receives an interrupt request (
INT2) is entered, the 9 o'clock counter 22 starts counting up, and enters the interrupt processing operation shown in the flowchart of FIG. 2 (step 200).

When microcontroller 1 enters the above interrupt processing, the time is 60.
"Determine whether the section has ended (step 201),
If it has not ended, the point of the basic voltage data in the memory 1a is calculated depending on the number of the 60° interval (step 202). Next, phase voltage data X is calculated from the contents of the memory 1a indicated by the pointer and the voltage parameter Vp (step 203). Similarly, phase voltage data Y is calculated from the contents of the memory 1a indicated by adding a fixed value to the pointer and the voltage parameter Vp (step 204).

Next, phase voltage data X is output to the boat (step 205), phase voltage data Y is output to the boat (step 206), and interrupts are enabled (step 207).
, exits from the interrupt routine (step 208).

If the 60° interval ends in step 201, the frequency and voltage commands input to the microcomputer 1 are used to calculate the number of carriers (step 209), carrier period (step 210), and voltage parameters (step 201). 211). And X, Y, O, X, Y.

1 (0) is assigned to which phase of U, V, and W to the latch circuit 24d (Step 212), and the carrier cycle data is output to the latch circuit 24a.
(step 213). Then step 20
Move to 5.

Here, irrespective of the operation of the microcomputer 1 mentioned above, the value of the carrier cycle data (actually data of 1/2 of the carrier cycle) latched by the latch circuit 24a and the value of the carrier cycle data latched by the latch circuit 24a are output from the counter 22. At the point when the carrier value matches the carrier value, the flip-flop 23 is inverted and the counter 22 starts counting down. Thereafter, after the interrupt processing shown in FIG. 2 is completed, the value of the counter 22 becomes 0, and the latch circuit 24a for carrier cycle data, the latch circuit 24b for phase voltage data X, and the latch circuit 24c for phase voltage data Y
The latch signal from the counter 22 is input to the select data latch circuit 24d, and each data is held.

After that, the above operation is repeated and the PW as shown in Fig. 4 is obtained.
M signal is obtained.

In this way, the X output from the microcomputer 1.

The Y phase voltage data, carrier cycle data, and select switching data are latched by the clear signal of the up/down counter 22 output at the lowest point of the carrier (No. 3), and each phase voltage data and carrier signal are compared. Since the PWM signal is output using the PWM signal, even if the carrier frequency increases, the waveform accuracy of the PWM signal is improved, and the arithmetic processing load on the microcomputer 1 can be reduced, increasing the processing capacity of the microcomputer 1. In addition, it can be constructed using an inexpensive microcomputer 1.

[Effects of the Invention] As described above, according to the present invention, since the clear signal of the counter that generates the carrier signal is used as the latch signal of the phase voltage data, the waveform accuracy of the PWM signal is improved, and the microcomputer used as the control means is improved. This has the effect of reducing the computational processing load, making it cheaper, and increasing the processing capacity of the microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing the configuration of an inverter output control device according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the circuit in FIG. 1, and FIG. 3 is a functional block diagram showing a conventional example. , FIG. 4 is an explanatory diagram showing the principle of generating the PWM signal of the inverter, and FIG. 5 is a flowchart showing the operation of the circuit of FIG. 3. ! ...Microcomputer (control means) 1
a---・-=Memory 2...Gate circuit 22---Up/down counter 23...
・Flip-flops 24 a to 24 d =---- latch circuit 25 a to
2.5 c ------- Comparator 26 -------
Data selector Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] In an inverter output control device that controls the switching elements of each phase provided in the inverter using a pulse width modulation signal and outputs alternating current of a desired frequency and voltage,
a control means that determines a phase voltage from frequency data, basic voltage data, and output voltage parameters and specifies an output destination of the data; a counter that generates a carrier signal for determining the frequency of the pulse width modulation signal; A gate circuit includes a comparator that compares the carrier signal and phase voltage data to generate the pulse width modulation signal, and a data selector that changes the output destination of the pulse width modulation signal. An inverter output control device characterized by latching data and inputting it to a comparator.