JPH02146879A - Liquid crystal television receiver - Google Patents

Abstract

PURPOSE:To distinguish a channel marker clearly from a picture by providing a segment driver for picture and a segment driver for indicator and driving both drivers by a signal of a different voltage waveform respectively. CONSTITUTION:A liquid crystal television set consists of a television receiver 1, a tuning voltage controller 2 and a liquid crystal display device 3. The device 3 is provided with a common driver 35 driving a common electrode of a liquid crystal panel 34, a picture segment driver 36 driving a picture segment electrode and an indicator circuit 38 generating a signal to drive a channel indicator segment electrode based on a data from an A/D conversion circuit 28 and an indicator segment driver 39. The circuit 38 drives a segment electrode ME of the indicator part of the panel 34 via the driver 29. Then the indicator part is driven with a different high voltage waveform from that of the picture display section to always display a clear channel marker in the display screen.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal television, and more particularly to a marker type channel indicator for displaying the selected channel of a liquid crystal television.

[Conventional technology]

Channel indicators on LCD televisions have changed from mechanical to panel display, and their formats are not uniform. An example of a panel display type channel indicator is one that uses a vertically long monochrome bar-shaped pattern extending from the top to the bottom of the screen as a channel marker, and moves this horizontally across the screen. There is one in which either the left or right end of the channel is used as an indicator, and a short horizontal channel marker is moved up or down. Character display indicators using microcomputers have almost never been put into practical use.

There are two ways to select channels: an auto-tuning method, which uses two push-button switches to select channels, and a manual method, which has a mechanical feel and selects channels by turning a rotary volume.

[Problem to be solved by the invention]

Among the conventional examples above, those that use microcontrollers are expensive (
, it will not be viable as a product unless there is another element that specifically enhances its marketability. Even if the configuration is relatively simple, in the case of a format that uses vertically elongated channel markers, the channel marker overlaps the image, so it is necessary to turn off the channel marker (unless you are operating the channel). An indicator display switch (commonly known as a channel call) is necessary when you want to know which channel is being received without having to watch the channel.The short horizontal channel marker is moved up and down at the edge of the screen, so that it is always displayed outside the image area. Since it can be displayed, there is no problem like the above.

However, in the conventional channel display method, channel markers are displayed using the same segment driver as the image display, so the contrast and brightness are the same as the image, making it difficult to distinguish them from the image. There is a problem that the marker may be mistaken for a part of the image, which can be a hindrance to viewing the video.Therefore, the marker should be displayed brightly and the background dark (even if the marker is displayed darkly, the marker may be displayed darkly). Even if the background is made brighter, it is difficult to clearly express that the indicator area is a separate area from the image area, and the contrast is also unclear. A mechanical indicator with moving brightly colored markers inside (for those who are used to it, it is extremely difficult to get used to).

The present invention aims to solve the above-mentioned problems, and its first object is to provide a liquid crystal television in which channel markers can be clearly distinguished from images.

A second object of the present invention is to provide a liquid crystal television in which channel markers are made to stand out from the background.

A third object of the present invention is to provide a liquid crystal television in which image segment electrodes and channel display segment electrodes are manufactured in the same process and in the same shape.

[Means to solve the problem]

The gist of the present invention for achieving the above object is as follows.

1. A television receiver that receives a television broadcast signal and outputs a video signal, a tuning voltage control device that outputs a tuning voltage for the television receiver, and a common electrode and segment for displaying the video signal as an image. A liquid crystal display device comprising a liquid crystal panel in which electrodes are arranged in a matrix, the liquid crystal television displaying a broadcast image and a channel indicator simultaneously on the liquid crystal panel, wherein the segment electrodes of the liquid crystal panel are used for images. In addition to segment electrodes and indicator segment electrodes, the liquid crystal display device includes an image segment driver for inputting a video signal from the television receiver to drive the image segment electrodes, and the tuning voltage control device. An indicator segment driver is provided for driving the indicator segment electrode by inputting a tuning voltage from the device, and the image segment driver and the indicator segment driver are driven by signals with different voltage waveforms. Features.

2. A plurality of indicator segment electrodes corresponding to the length of the channel marker are arranged at either the left or right side end of the liquid crystal panel, and the indicator display section is formed as a whole.

3. The indicator segment driver is driven by a signal with a higher voltage waveform than the image segment driver.

4. The indicator segment driver outputs a signal with a voltage waveform that fixes the potential of the indicator segment electrode to approximately a common potential during a period other than the timing of displaying the channel marker.

5. Color filters of three colors, RGB, are formed in stripes on the image segment electrodes and indicator segment electrodes provided on the liquid crystal panel.

6. The indicator segment electrode is divided into a first color selection electrode corresponding to a filter of one color among RGB and a second color selection electrode commonly connected to filters of the other two colors. Features.

7. All the first color selection electrodes in the indicator display section are connected in common to lead out as a first common electrode, and the second color selection electrodes are connected in common to form a second common electrode. It is characterized by being derived as a common electrode.

8. The first common electrode is supplied with either the VHF channel marker lighting signal or the UHF channel marker lighting signal selectively output from the indicator segment driver, and the second common electrode is supplied with the other one. It is characterized by being supplied.

〔Example〕

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a liquid crystal television according to the present invention. Reference numeral 1 denotes a television receiver that converts the signal into an RF double signal video signal, 2 a tuning voltage control device that controls the reception frequency band and reception channel of the television receiver 1, and 6 converts the signal from the television receiver 1 into an image. This is a liquid crystal display device, and the audio circuit, power supply circuit, etc. are omitted from illustration.

The television receiver 1 includes a chainer 11 that converts the RF multiplied signal into an intermediate frequency signal (referred to as an IF multiplied signal), and a chainer 11 that detects the 1F signal and outputs a video signal VIDEO and an audio signal AUDEO.
It consists of a detection circuit 12 that extracts the .

The tuning voltage control circuit 2 is connected to an external operation block 27.
, an A/D conversion circuit 28 , a D/A conversion circuit 29 , and a high voltage conversion transistor circuit 25 that DC amplifies the output signal of the D/A conversion circuit 29 .

The liquid crystal display device 6 includes a chroma circuit 31 that divides the video signal VIDEO into a synchronization signal 5YNC and an RGB signal;
A control circuit 32 has a built-in reference oscillator, generates various clock signals and timing signals, performs A/D conversion of the RGB signals, and controls the liquid crystal panel driver.
In addition to the liquid crystal panel 64, the common driver 65 for driving the common electrodes of the liquid crystal panel 64, and the image segment driver 36 for driving the image segment electrodes, An indicator circuit 68 that generates a signal for driving channel indicator segment electrodes based on data and an indicator segment driver 69 are provided. The indicator circuit 68 has an output terminal for UHF reception and an output terminal for Vl (F reception), and is connected to the liquid crystal panel 64 via an indicator segment driver 69.
The segment electrode ME of the indicator portion of is driven.

FIG. 11 is an external view showing the external appearance of the liquid crystal television of the present invention, and the numbers on the right side represent channel numbers, 1
The numbers up to ~12 are VHF band channel numbers, 13~
The number 62 means the channel number of the UHF band. 501 is an indicator part of the liquid crystal panel, 502 is an image display part, 506 is a channel marker displayed on the liquid crystal panel, and a tuning variable resistor 27a
By rotating a disk-shaped knob 505 for turning with a finger 504, the channel marker 506 moves up and down, and when it is brought to the end and continues turning the knob,
The resistance value of the variable resistor 27a changes rapidly from the maximum to the minimum or from the minimum to the maximum after passing through a high impedance state, but the channel marker 503 is not displayed, and when the variable resistor 27a is turned further, the channel marker 506 appears again from the opposite side and tuning is possible. It looks like this. In this case, the movement of the channel marker 503 to the opposite side is not displayed, and it appears as if it has moved through the back side. Slide knob 506 provided on the side of the LCD TV case
is the knob for UHF/VHF band switching, and knob 5
Slide 06 upward to select the UHF band, and slide downward to select the VHF band.

FIG. 12 is a partial plan view that attempts to clearly show a part of the electrode structure of the liquid crystal panel 64, and the color-coded stripes 601, 602, and 606 are R, G, and B of the color filter, respectively. , 604 is common driver 6
5 is a common electrode driven by 605, and 605 is an image segment electrode driven by an image segment driver 66. Further, 606 is an indicator segment electrode constituting the indicator portion of the present invention. The length l occupied by these twelve indicator segment electrodes 606 becomes the length of the channel marker 503.

Stripe color filters 601 to 603 similar to the image portion are formed on the indicator segment electrode 606.
It also has a stripe shape similar to the image segment electrode 605. However, at one end, the same color (R)
are connected together and put together into a first common electrode terminal 6.
06a and the remaining two colors (G, B) at the other end.
) are connected together into a second common electrode terminal 606.
b. In this embodiment, both the common electrode terminals 6
06a and 606b are provided in the same direction, the common electrode terminal 606b passes through the endmost segment electrode. The two common electrode terminals 606a, 606
b are respectively connected to two output terminals of the indicator segment driver 69.

FIG. 2 is a block diagram showing in detail the configuration of the external operation block 27, high voltage conversion transistor circuit 25, and indicator segment driver 69 of the present invention.

The external operation block 27 is a tuning variable resistor 27
a and UHF/VHF switching slide switch 27
b, and semi-fixed resistors VRI to VR6. The high voltage conversion transistor circuit 25 is a D/A conversion circuit 29
The signal PWM2 is smoothed by a resistor 25a and a capacitor 25b and amplified by an operational amplifier 25C to create a tuning voltage Vc, and the amplification factor is a resistor 25d.
It is sufficient to fix the division ratio to an appropriate value of 256.

The indicator segment driver 39 amplifies the signal M1 output from the indicator circuit 68 and sends the marker signal Ml to the indicator segment electrode 60.
6a, resistors 39a and 39b for determining the amplification factor, and an operational amplifier 39C.
The marker is composed of a capacitor 39d for DC cut and a resistor 39e for clamping to the common voltage level VM of the liquid crystal panel drive voltage, and is created by amplifying the signal M2 output from the indicator circuit 68 in exactly the same way. The signal M2 is connected to the indicator segment electrode 606.
The circuit for applying voltage to b is resistors 39f, 39g, and 39h.
, operational amplifier 691. Another capacitor 39j is configured.

FIG. 3 is a block diagram showing the circuit configuration of the A/D conversion circuit 28, and FIG. 4 is a timing chart showing its operation.

K2O1 is a signal 5G2 obtained by dividing the clock signal CLKt.
0 and the signal 5G2 which is a thin pulse of the signal 5G20.
A timer K2O2 that outputs 1 is a binary counter with a reset that outputs a count-up signal ENDI, which outputs the clock signal C through an AND gate A203.
While counting LK1, when the count is up, the count-up signal END1 passes through the inverter 1204 and closes the AND gate A2[]3 to stop counting.

K2O3 is the click input terminal UP and DO for UP count.
This is a 12-pin up/down counter having a clock input terminal DN for WN counting and a built-in decoder for outputting a negative logic signal MAXB indicating that the count has reached the maximum and a negative logic signal ZERB indicating zero count.

K2O6 is the lower 4 of 205 in the up/down counter.
This is a well-known multiplexer that switches bits at the timing of the signal 5G21 and outputs the output with a difference in the number of outputs depending on the bit weight to produce a 1-bit signal.

K2O7 has the top 8 of 205 in the up/down counter.
This is a digital comparator that compares the contents of 9 bits including 1 pit from 206 to the multiplexer and the contents of 9 pits to the binary counter 202, and outputs a match signal EQ1.

Here, the output signal of the D-type flip-flop F2O3, which is set at the rising edge of the signal 5G21 and reset by the inverted signal of the coincidence signal EQI, and the count-up signal END1 are connected to the -CP channel through the inverter I209 and the NOR gate R210. Field effect transistor M211 and N-channel field effect transistor M
212, a three-state signal PWM1 is obtained from the drains of both transistors. This three-state signal PWM1 is the signal 5G21
The signal becomes high during the time from then to the coincidence signal EQ1, becomes low from there until the signal END1, and becomes high impedance from then until the next 5G21. A voltage V28 obtained by smoothing this signal with a resistor R1 and a capacitor C1 is a substantially DC voltage whose level changes depending on the pulse width of the three-state signal PWM1. and change. K214 is a voltage comparator that compares the voltage V28 with the voltage VREF from the tuning variable resistor 27a and outputs a high signal when the voltage V28 is lower, and outputs a low signal when the voltage V28 is higher. The output of 214 to the voltage comparator is a D-type flip-flop F215.
The signal is sampled at the timing of the signal 5G20. AND gates A216 and A217 each have the outputs Q and Q of the flip-flop F215 as one input, and the signal 5G20 as the other input, and their output signals are an up signal UP and a down signal DN, respectively. The up signal UP is input to the AND gate A218 together with the signal MAXB of 205 to the up/down counter, the down signal DN is input to the AND gate A219 together with the signal ZERB, and the output signals are input to the up/down counter 205, respectively. It is input to terminal UP and terminal DN of. As a result, the up/down counter 205 is configured not to count up above the maximum value or down count below zero, and when the voltage V28 is lower than the VREF, it counts up and increases the voltage V28. Conversely, when the voltage V28 is higher than the VREF, it counts down to lower the voltage V28.

With the above configuration, 205
+i, a counting operation is performed in the direction in which the voltage V28 and VREF become equal, and as a result, the voltage of VREF becomes A/
The D-converted result is obtained in the up/down counter 205.

A marker erasing circuit 28a is added to the A/D conversion circuit 28 of the present invention to make it appear as if the marker has moved through the back side. The following marker erasing circuit 28a
Explain the configuration and operation of.

N220 is an intermediate value decoder that outputs the 205 intermediate bits to the up/down counter as is, or more carefully, always outputs high when the intermediate value is a certain distance from the maximum value and zero. F225 and F2
22 is an SR flip-flop set by the zero count signal ZERB; N221 is a NAND gate that resets the SR clip 70 knob F222 with an AND signal of the output signal of 220 and the up signal UP in the intermediate value decoder; N224 is a NAND gate that resets the SR flip-flop F225 with an AND signal of the inverted signal of the output of the SR flip-flop F222 by the inverter I226 and the down signal DN.

That is, the SR flip-flop F225 is set at zero count, and then when only the up signal UP continues, it will not be reset to the maximum count even if it passes through the intermediate value. Similarly, F227 and F260 are SR flip-flops set by the maximum count signal MAXB, and N226 is an AND signal of the output signal of 220 and the down signal DN, which is set by the maximum count signal MAXB.
(NAND game that resets the flip-flop F227), N229 is an AND signal of the inverted signal of the output of the SR flip-flop F227 by the inverter I229 and the up signal UP;
This is a NAND gate that resets 230. In this case, the SR flip-flop F230 is set at the maximum count and is not reset to zero count when only the down signal DN continues thereafter. Therefore, when the V RE F suddenly changes from zero to the maximum or from the maximum to zero, the tuning variable resistor 27
When the resistance value of a suddenly changes, the SR flip-flop F225 or F260 remains set.

In this way, SR flip-flops F225 and F260
is set in the up/down counter at zero and maximum value of 205, and is configured to be reset when it starts to repeat up and down within a predetermined value range, and the output signals of both flip-flops By performing the logical sum with OR game 0231 and outputting it as the indicator inhibit signal INH, the display of the marker can be erased at an appropriate timing, making it appear as if the marker is passing through the back side.

Furthermore, the contents of 9 bits including the upper 8 bits of 205 in the up/down counter and 1 bit from 206 in the multiplexer are transferred to the pass line BUS1.
/A conversion circuit 29 and indicator circuit 68.

FIG. 5 is a block diagram showing an example of the configuration of the D/A conversion circuit 29, and FIG. 6 is a timing chart showing its operation. The basic configuration includes a timer 256 that frequency-divides CLK1 and outputs a pulse signal 5G31, similar to the A/D conversion circuit 28, and a timer 256 that outputs a pulse signal 5G31.
a first delay circuit 29a for offset adjustment which inputs the clock signal P269 and outputs the delayed signal P269, and the clock signal CLK1.
251, which is started by the delay signal P269 and stopped by the count-up signal; 252 to a digital comparator for comparing the contents of the pass line BUS 1 which is the D conversion result and outputting a coincidence signal EQ2; and 252 to the digital comparator set by the output signal of 256 to the timer.
a flip-flop F254 that is reset by a decoder 29b that decodes the output signal of the counter 251, and an output signal END of the decoder 29b that is set at the falling edge of the output Q of the flip-flop F254.
2, the flip-flop F is reset by the signal P270 generated by the second delay circuit 29C for gain adjustment.
255, and both the flip-flops F254 and F255.
By inputting the output signal of
CMO8) transistors M256 and M25 that output M2
It consists of 7. This 3-state signal PWM2 is
Assuming that the time constants of the first and second delay circuits 29a and 29C are zero, the signal 5G31 to the coincidence signal E
The signal becomes high during the time up to Q2, becomes low during the time from there to the decoder output signal END2, and becomes high impedance (indicated by a broken line) thereafter until the next 5G31. This 3-state signal PWM2 is connected to the resistor 25.
Integrating circuit consisting of a and capacitor 25b (see Figure 2)
The tuning voltage VC can be obtained by smoothing the voltage and amplifying the direct current using an operational amplifier or the like. This voltage VC is a substantially direct current voltage whose level changes depending on the pulse width of the three-state signal PWM2, and the tuner 11 is tuned according to the level of this voltage VC.

25j (maximum count number 51) in the binary counter
The decoder 29b that decodes 1) is a NAND game (N258 to N26) that decodes the upper 3 bits into 3 types.
0, and a NAND gate N261 that outputs the logical sum of the three decoding results as END2,
One of the types is selected depending on the receiving frequency band. As a result, the output timing of END2 is obtained from the NOR gate R265 which inputs the color signal UV in the UHF band.

The D/A conversion circuit 29 of the present invention includes the path line BUS.
A subtraction circuit is provided between 1 and 252 of the digital comparator, and a signal U indicating the pass line receiving frequency band is provided.
Signal UV from external operation block among V, VH, and vL
is a U/V switching signal that is high when it is UHF and low when it is VHF. Regarding the determination of HIGH/LOW of VHF, in this embodiment, in order to simplify the circuit, HIGH is determined when either of the upper two bits of the pass line BUS 1 becomes high, and VHF - HI
The signal VH indicative of this is obtained by taking the logical sum of the upper two bits of the pass line BUS1 by an OR gate 0262, and then inverting this by an inverter I263.
It is obtained by passing the signal UV along with the NOR gate R264. Furthermore, a signal vL indicating VHF-LOW
is the output signal of the OR game) 0262 and the signal VHF
- LOW to VHF-HIK off') At the same time as changing the value, the value sent to the comparator 252 is changed to n-128. In this embodiment, inverter I
A simple gate circuit consisting of an exclusive sweep-or gate E266 and an exclusive sweep-or gate E267 performs an operation equivalent to subtraction on only the upper two bits. The above subtraction result is VH
Transmission game when F-HI) TG2.
9, is output through TG30, and at other times, the signal before subtraction is output as is through transmission gates TG27 and TG28.

In addition, a first delay circuit 29a for delaying the time from the timer output signal 5G31 to the start of counting 251 in the binary counter;
The counter is provided with a circuit for forming a second delay circuit 29C for delaying the time from the decoding result output END2 of the counter 251 to the reset of the flip-flop F255. The SR flip-flop F268 is provided to generate a signal whose rising edge indicates the output timing of the timer signal 5G31 and whose falling edge indicates the output timing of the decoding result signal END2 of 251 to the binary counter.
32 is sent to both the delay circuits 29a and 29G.

The first delay circuit 29a converts the output signal 5G32 of the SR flip-flop F268 into the signals VL, VH,
Transmission gates TG24, TG25, TG26 each switched by UV and semi-fixed resistor VR4
It is composed of a first RC time constant circuit composed of ~VR6 and a capacitor C20, and a one-shot circuit 269.

After the signal 5G32 is delayed by the first delay circuit 29a, its rising edge is converted into a narrow pulse signal P269 by the one-shot circuit 269 and applied to the reset terminal of the binary counter 251.

The second delay circuit 29C includes transmission gates TG21, TG22, and TG23 that switch the signal 5G32 with the signals VL%VH and UV, respectively;
A second RC time constant circuit consisting of semi-fixed resistors VR1 to VR3 and a capacitor C21, and a one-shot circuit with 27
0.

After the signal 5G32 is delayed by the second delay circuit 29C, its falling edge is applied to the one-shot circuit 270 as a thin negative direction pulse signal to the reset terminal of the flip-flop F255.

By configuring in this way, the first delay circuit 29a
Therefore, the offset of the tuning voltage VC can be adjusted by adding a certain time to the high period of the three-state signal PWM2 without affecting the low period, and the second delay circuit 29G allows the low period to be adjusted. The gain can be adjusted by extending the period by a certain amount of time and reducing the high impedance period.

FIG. 7A is a circuit block diagram showing a configuration example of the indicator circuit 38, and FIG. 7B is a time chart of signals of each part. K2O2 is the A/D conversion circuit 28
A/ sent by path line BUS 1 from
When the vertical synchronizing signal vS from the control circuit 62 is supplied to the latch enable terminal LE in a latch circuit that latches D-converted data, a latch operation is performed at that timing to latch the upper 8 bits out of 9 bits.

The pass line BUS2 carries an 8-bit data signal sent from the control circuit 62, and this data is a count value obtained by counting the horizontal synchronizing signal H3 starting from zero at the start of scanning of the common driver.

K2O2 is a match circuit that compares the data on the pass line BUS2 with the contents of 601 in the latch circuit and outputs a match signal EQ3. F2O3 is the vertical synchronization signal V
S is set and the output signal EQ3 of 602 is sent to the matching circuit.
The SR flip-flop K2O2 is a shift register that shifts the output signal 5G56 of the SR flip-flop F604 at the timing of the horizontal synchronizing signal HS. This is a three-stage shift register that outputs a delayed signal 5G34.An inverter 1605 that outputs an inverted signal of the output signal of the SR flip-flop F604, and an AND that inputs the inverted signal and the output signal 5G34 of 606 to the shift register. Game) A
306, a signal MRK with a pulse width of 6H that rises in response to the coincidence signal EQ3 is obtained. By driving the indicator segment electrode 606 at the timing of this signal, a channel indicator marker can be displayed. A60
7. A 308 c. UHF/VHF off': 1 change It constitutes a selector together with an inverter 1609 that inverts the signal Uv, and when receiving UHF, A607 outputs the signal MRK, and when selecting VHF, A308 outputs the signal MRK. .

The signal DR from the control circuit 62 indicates the polarity of the selection scanning signal of the common driver 35, and includes inverters l611, l612 and AND gates A614, A
618, and the inverter ■611,
The output of 2 is input to NAND gates N613 and N317. The output of the AND gate A307 is connected to the other input terminals of the AND gate A314 and the NAND gate N313, and the AND gate A31
8 and the other input terminal of the NAND gate N317 are connected to the output of the AND gate N308. M621 is a P-channel field effect transistor driven by the NAND gate N313, M322 is an N-channel field effect transistor driven by the AND gate A614, and the drains of both transistors are connected to each other and connected to the UHF channel marker lighting terminal. It has become.

M626 is a P-channel field effect transistor driven by the NAND gate N317, and M624 is an N-channel field effect transistor driven by the AND gate A318.The drains of both transistors are connected to each other and serve as a VHF channel marker lighting terminal. ing.

Next, the marker signal output operation of the indicator circuit 68 will be explained.

Now, if the band selection is in the UHF selection state, the AND game) A307 is in the operating state, so the signal MRK is NAN.
The signal is supplied to D gate N616 and AND gate A614, and as a result, marker signal M1 is outputted from signal MRK and signal DR as shown in FIG. 7B.

Next, when the band selection is switched to VHF, the AND gate A308 is activated and the marker signal M2 is switched and output. Both channel marker signals M1 and M2 are supplied to inverters l615 and l316 as shown in FIG. 7B.
And, by transmission gates T619 and T620, the signal M RK is fixed at an intermediate potential during a low period, that is, a period other than the marker lighting timing.

As a result, the marker signal M1. M2 becomes a 3-level signal. The intermediate potential is created by resistance division using resistors R31 and R32.

Here, driving of the image section and indicator section of the liquid crystal television according to the present invention will be explained with reference to FIGS. 8 and 9.

FIG. 8 is a diagram similar to FIG. 12, and shows a part of the electrode structure of the liquid crystal panel. , B, and is shown as one electrode.

In the illustrated example, the indicator segment electrode ME is 5
It's a book. The length l of the channel display marker lit in the indicator section is determined by the number of indicator segment electrodes ME, and is five in the illustrated example. Further, the width W of the marker is determined by the number of common electrodes, and in the illustrated example, there are three.

FIG. 9 shows the waveforms of the signals applied to the common electrode CE and the segment voltages SE and ME, and the waveform of the voltage applied between both electrodes, and (a) shows the scanning voltage applied to the common electrode CE. Signal waveforms, (b) is the waveform of the marker signal applied to the indicator segment electrode ME, (c) is the waveform of the image signal applied to the image segment electrode SE, and (b) is the common electrode CE and the indicator segment The waveform of the voltage applied between the electrode ME and (e) is the waveform of the voltage applied between the common electrode CE and the image segment electrode SE. In addition, Figure 9 (a) and (b)
, (/-+, ni), and (e), the horizontal axes are time expressed on the same scale.

However, the vertical axes of (E) and (E) are exaggerated because the actual values would be too small.

Now, as shown in FIG. 8, the common electrodes CE are CE ICE z ...CE tan 240 in order from the top.
Consisting of a book electrode, each common electrode CE.

Selection pulses, which are scanning signals as shown in FIG. 9(a), are sequentially applied to CF2...CE z 4° (.

The polarity of the selection pulse is reversed for each line, and the peak value is, for example, +18 leap, and the potential of the common electrode at the time of non-selection is at the common potential.

At this time, when all five indicator segment electrodes ME have peak values as shown in FIG. 9(b), each of the common electrodes CE, CE, .
A voltage as shown in FIG. 9) is applied between the indicator segment electrode ME and the indicator segment electrode ME.

Examining the inter-electrode voltage at this time for each common electrode, we find that common electrodes CE, -CE, and CE8 to CE are used for scanning signals and indicators with a peak value of ±18 (V) applied to the common electrodes. Since the marker signal M with a peak value of ±9 (V) applied to the segment electrode ME is shifted in timing, the maximum value of the voltage applied between both electrodes is +18 (to) which is equal to the peak value of the scanning signal. Therefore, the liquid crystal between the two electrodes will not light up.

However, the common electrodes CE s CE a , CE−
Regarding r, since the timings of the scanning signal and the marker signal M overlap, the voltage applied between the common electrode and the indicator segment electrode ME is ±9 (v )+18(V)=±2
7 (V). Therefore, common electrode CE s ,
The liquid crystal at the portion where CE a and CE y overlap with the indicator segment electrode ME is lit and displayed as a marker with width W and length j. That is, the length l of the marker
is equal to the lateral distance of the indicator segment electrode ME consisting of five segment electrodes, and the marker width W
are three common electrodes CE s , CE a , CE
Equal to the vertical distance of y.

The scanning signal shown in FIG. 9(a) is the control driver 6.
The marker signal M indicated by VC in FIG. 1) to the indicator segment electrode ME, the intersection of the picture electrodes continues to light up as a marker.

The position of the waveform of the marker signal M in FIG. 8 (b) changes in accordance with the channel selected by the tuning voltage VC from the high voltage conversion transistor circuit 25 by the external operation block 270 channel selection operation (because of this, A common electrode corresponding to that position is selected and the lighting position of the marker changes, thereby making it possible to display a channel selection.

Currently, with NTSC video signals, one field is 26
Assuming that the video signal on 240H of 2.5H is to be displayed on the liquid crystal, the effective value voltage applied to the liquid crystal of the indicator section is when the marker is lit (■Y.N
) and when the marker is turned off (VM,,,), it becomes as follows Vvos ” (2X9” + (18+9)”)/
262.5 = 1.842 (V) VMo,, = (
3X9”+18”)/262.5 = 1.470(V
)VMON/Vmorr=1.254
(1) On the other hand, the image segment electrode SE is composed of a plurality of segment electrodes (for example, 640 segment electrodes), one of which is the segment electrode SE.

When examining the voltages applied between each common electrode CE when an image signal as shown in FIG. 9(C) is applied, the results are as shown in FIG. 9(E).

That is, regarding the common electrodes CE and ~CEa, the scanning signal applied to the common electrodes and the image segment electrode S
Since the image signal with the peak value ±1.2v applied to E overlaps with the same polarity, the maximum value of the voltage applied between both electrodes is ±1s (V) + 1.2(V) = ±16 .8 (G), and the liquid crystal between the two electrodes does not light up.

However, CE after common electrode CE7, CB9...
Regarding ・, since the scanning signal and image signal overlap with opposite polarity, the maximum value of the voltage applied between both electrodes is +18 (■±
1.2(V)=±19.2(Vl), and the liquid crystal between the two electrodes lights up.

At this time, the effective value voltage applied to the liquid crystal of the image area is as follows when the light is on (Vo.N) and when the light is off (■...2.).

vGO, l=〆(239X1.2”+(18+1.2)
2) / 262.5 = 1.648 (V) 1.545 (V) V (1ON / V aorr = 1.067
・==・(2) As is clear from comparing the above equations (1) and (2), V in the indicator section. * /
V 6 y y value is V aos/V in the image area
Although it is considerably larger than the aorr value, this means that the contrast between the indicator area when the marker is lit and its background is much larger than the contrast in the image area.

FIG. 10 is a voltage-transmittance characteristic diagram (T-V
curve). As shown in this figure (the contrast of the image area is 5=1, it can be seen that the contrast of the indicator area is significantly improved to 48:1).This difference in contrast is as shown in Figure 8 (the contrast of the marker signal is This is achieved by a voltage difference between the image signal and the image signal, and a drive voltage waveform in which the period of the marker signal other than the marker display timing is fixed to approximately a common potential.

In FIG. 8, the interval between the diagonal lines is changed so that the difference in contrast between the image area and the indicator area can be easily seen, and the finer the interval between the diagonal lines, the closer to black it is. Even from this gradation, it can be seen that the indicator portion can be distinguished from the image portion, and the marker of the indicator portion can also be distinguished from the image portion.

In this embodiment, the binary counter 202 of the A/D conversion circuit 28 and the binary counter 251 of the D/A conversion circuit 29 are separated for the sake of explanation, but in reality, they have a common configuration. 201 on the timer.
The same applies to the lower 7 bits of the digital comparators 207 and 252.

〔Effect of the invention〕

(According to the present invention, an indicator section for displaying a channel marker is provided at one end of the liquid crystal panel, and this indicator section is driven with a high voltage waveform using a driver different from that of the image display section. , it is now possible to display clear channel markers on the display screen at all times.

Furthermore, when changing bands, the color filters are changed to display the channels, so it is possible to display channel markers of different colors for each band, making identification extremely easy.

Furthermore, by making the shapes of the electrodes and color filters of the indicator part the same as those of the image display part, it is possible to achieve many effects, such as making it possible to avoid complicating the manufacturing process of the liquid crystal panel. .

[Brief explanation of the drawing]

FIG. 1 is an overall circuit configuration diagram of a liquid crystal television according to the present invention;
Figure 2 is a detailed circuit diagram of a part of the overall circuit configuration shown in Figure 1, Figure 3 is a detailed circuit diagram of the A/D conversion circuit shown in Figure 1, and Figure 4 is a detailed circuit diagram of the A/D conversion circuit shown in Figure 1. FIG. 5 is a detailed circuit diagram of the D/A conversion circuit shown in FIG. 1, FIG. 6 is a timing chart showing the operation of the D/A conversion circuit, and FIG. 7A is a timing chart showing the operation of the D/A conversion circuit. 7B is a detailed circuit diagram of the indicator circuit shown in FIG. 1, FIG. 7B is a timing chart showing the operation of the indicator circuit, FIG. 8 is a partial plan view showing the electrode structure of the indicator section of the liquid crystal television according to the present invention, and FIG. Figures 9 (a) to (1) are timing charts showing the waveforms of signals applied to each electrode of the liquid crystal panel;
Figure 0 is a voltage-transmittance characteristic diagram for comparing and explaining the contrast between the image area and the indicator area of the liquid crystal panel of the liquid crystal television according to the present invention, and Figure 11 is a perspective view showing the appearance of the liquid crystal television according to the present invention. FIG. 12 is a partial plan view showing the electrode shape of the liquid crystal panel of the liquid crystal television according to the present invention. 1...Television receiving device, 2...Tuning voltage control device, 6...
...Liquid crystal display device, 27...External operation block, 28...A/D conversion circuit, 29...D/A conversion circuit, 34... LCD panel, 36... Image segment driver 38...
... Indicator circuit, 69 ... Segment driver for indicator ... Indicator section, 3 ... Channel marker VC Fig. Fig. (b) (d) VCEI+ 111112 ``- (c) (book) and cheek seventh figure

Claims (8)

[Claims] (1) A television receiver that receives a television broadcast signal and outputs a video signal, a tuning voltage control device that outputs a tuning voltage for the television receiver, and a common electrode that displays the video signal as an image. A liquid crystal display device comprising a liquid crystal panel having segment electrodes arranged in a matrix, and displaying broadcast images and channel indicators simultaneously on the liquid crystal panel, wherein the segment electrodes of the liquid crystal panel are arranged in a matrix. In addition, the liquid crystal display device includes an image segment driver for inputting a video signal from the television receiver to drive the image segment electrode, and the tuning voltage. An indicator segment driver is provided for inputting a tuning voltage from a control device to drive the indicator segment electrode, and the image segment driver and the indicator segment driver are driven by signals with different voltage waveforms. An LCD TV featuring (2) A plurality of indicator segment electrodes corresponding to the length of the channel marker are arranged on either the left or right side edge of the liquid crystal panel, and the indicator display section is configured as a whole. The liquid crystal television according to claim 1. (3) The liquid crystal television set according to claim 1, wherein the indicator segment driver is driven by a signal with a higher voltage waveform than the image segment driver. (4) The indicator segment driver outputs a signal having a voltage waveform that fixes the potential of the indicator segment electrode to approximately a common potential during a period other than the timing of displaying the channel marker. liquid crystal television. (5) The liquid crystal television set according to claim 1, wherein color filters of three colors, RGB, are formed in stripes on the image segment electrodes and the indicator segment electrodes provided on the liquid crystal panel. (6) The indicator segment electrode is divided into a first color selection electrode corresponding to a filter of one color among RGB and a second color selection electrode commonly connected to filters of the other two colors. The liquid crystal television set according to claim 5. (7) All the first color selection electrodes in the indicator display section are connected in common to lead out as a first common electrode, and the second color selection electrodes are connected in common to form a second common electrode. 7. The liquid crystal television set according to claim 6, wherein the liquid crystal television is derived as a common electrode. (8) Either the VHF channel marker lighting signal or the UHF channel marker lighting signal selectively output from the indicator segment driver is supplied to the first common electrode, and the other is supplied to the second common electrode. 8. The liquid crystal television set according to claim 7, wherein: