JPH02146659A - Bus control system - Google Patents

Abstract

PURPOSE:To enable the devices except a memory to use a shared bus with no occupation of the bus even though the memory is kept in a refresh mode by adding a refresh busy signal generating device to the memory and a memory access inhibiting means to each information processor respectively. CONSTITUTION:A refresh busy signal generating device 5 is added to a memory 2 to control the memory 2 so that it is refreshed synchronously with a bus clock and a main clock and also to show that the memory 2 is kept in a refresh mode. A transmission line 6 is added to a common bus 4 for transmission of the refresh busy signal. Furthermore the memory access inhibiting means 7-1 - 7-n are added to the information processors 1-1 - 1-n respectively to inhibit the accesses to the memory 2 during the reception of the refresh busy signal. In such a constitution, such a case where the bus becomes unavailable during the refresh of the memory 2 can be avoided. Then the operating efficiency is improved for each information processor.

Description

[Detailed Description of the Invention] (Summary) A synchronization method is adopted, and a plurality of information processing devices are assigned bus usage priorities by a bus priority determining means, and a plurality of information processing devices are commonly accessed and Regarding a bus control method that controls a common bus that connects a memory device that requires refreshing at regular intervals and other input/output devices, the memory device is refreshed in synchronization with the bus cycle, and the memory device is being refreshed. The purpose of this is to allow devices other than the memory device to use the bus without the shared bus being occupied, even if the shared bus is A refresh busy signal generator is provided which controls the refresh operation in synchronization with the main clock and generates a refresh busy signal to indicate that the memory is being refreshed, and transmits the refresh busy signal to the common bus. In addition, each information processing device is provided with memory access prohibition means for prohibiting access to the memory device when receiving the refresh busy signal.

[Industrial application field]

The present invention relates to a bus control method, and particularly to a bus control system that employs a synchronous method, and that uses a plurality of information processing devices whose bus usage priorities are assigned by a bus priority determining means, and which is accessed in common by these information processing devices. The present invention relates to a bus control method for controlling a common bus that connects memory devices that require refreshing at regular intervals and other input/output devices.

[Conventional technology]

By adopting the synchronization method as described above, as shown in Fig. 7,
A common bus 11 connects multiple terminal devices 12 which are information processing devices.
-r, 12-2. ..., 12-, and the plurality of terminal devices 11. ．． 12-2. In an information processing system in which a memory device 13, an input/output device 14, etc. that are commonly used by terminal devices 12-n are combined, a plurality of terminal devices 12-1
, 12-2. ..., 12-n simultaneously issue a request to use the common bus 11, to which terminal device is the common bus 11 used?
For example, a bus priority determining means 15 is provided which predetermines whether to give exclusive right to the terminal device 12. ．． 1,112.・・・
, 12-n accesses the memory device 13, it first issues a bus occupancy request to the bus priority determining means 15, and when there is no conflict with other terminal devices, the terminal device that issued the request is granted bus occupancy permission. is given. However, if multiple terminal devices issue requests to occupy the common bus 11 at the same time, the right to use the common bus will be given to the terminal device with the highest priority according to the predetermined priority order of the terminal devices. The bus is controlled so that lower terminal devices are not allowed to use the bus.

[Problem to be solved by the invention]

By the way, the memory device 1 of such an information processing system
3, in order to continue to retain its internal information, it must be refreshed. This memory device is refreshed once every 16 ps, for example. During refresh of the memory device 13, if there is an access from a terminal device, the refresh will be hindered, so the memory device 13 is set in advance as the bus master with the highest priority in the bus priority setting means, and refresh from the memory device 13 is performed. When a request is received, this request is given top priority and the common bus is occupied, prohibiting other information processing devices from using the common bus and preventing access to the memory device.

However, in this method of preventing access from other devices while the memory device is being refreshed, the common bus is occupied during refresh, and the terminal device cannot access the memory from other devices. For example, if you try to exchange data with an input/output device, it will not work.
It becomes inefficient.

Furthermore, if refresh of the memory device is executed independently of bus cycles in order to avoid such problems, there is a problem that synchronization with other devices cannot be achieved, resulting in inefficiency.

Therefore, the present invention provides a system in which a memory device is refreshed in synchronization with a bus cycle, and the shared bus is not occupied even when the memory device is being refreshed, and devices other than the memory device can use the bus. The purpose is to provide a bus control method that allows

[Means to solve the problem]

In the present invention, means for solving the above problems are as follows:
As shown in FIG. 1, a plurality of information processing devices 11, 12, . In a bus control method that controls a common bus 4 that connects a memory device 2 that is commonly accessed by a processing unit and requires refreshment at regular intervals, and other input/output devices 3, the memory device includes a memory device. A refresh busy signal generator 5 is provided for controlling the operation so that the memory is refreshed in synchronization with the bus clock and the main clock, and also for displaying that the memory is being refreshed and for generating a refresh busy signal. A transmission path 6 for transmitting a refresh busy signal is provided, and each information processing device 1-t, 1-2..., 1
-n includes memory access inhibiting means 7-1+'7-2 for inhibiting access to the memory device when receiving the refresh busy signal. . . , 7-n was provided.

(Function) According to the present invention, the fresh busy signal generating device 5 provided in the memory device 2 controls the operation so that the memory device 2 is refreshed in synchronization with the pass clock and the main clock, so that the memory is refreshed. Generates a refresh busy signal to display. And memory access prohibition means provided in each information processing device '7-1.7-2+
....

7-n prohibits access to the memory devices of the information processing devices 1-1+, 1-2+, . The information processing device can use the shared bus normally. Furthermore, since the refresh timing of the memory device is synchronized with the main clock, the information processing device can access the memory device efficiently.

〔Example〕

Embodiments of the bus control system according to the present invention will be described below with reference to the drawings.

2 to 6 show embodiments of the bus control system according to the present invention. FIG. 2 shows the connection status of each line of the common bus control system used in the bus control system according to this embodiment. In the same figure, 11-1 to 11-n
are n terminal devices that operate as bus masters that can occupy the bus, and 12 are these terminal devices 11-1 to 11-1.
11-o is a memory device commonly accessed; 13 is an input/output device used by the above-mentioned n terminal devices 11-1 to 11-n; and 14 is a control device for controlling the bus use order of the above-mentioned terminal devices. 3 shows a means for determining bus priority.

In this embodiment, a common bus 1 connecting each device
5 is connected to the control line shown in FIG. 2 as a control line. In FIG. 2, 16 is a clock line through which a main clock (MCLK) and a reference path clock (BCLK) are transmitted, and 17 is each terminal device 111.11-2. -,
A line 11-n transmits a bus use request signal (BRQ) to the bus priority determining means, and 18 is a line through which a bus use request signal (BRQ) is transmitted from the bus priority determining means 14 to the bus priority determining means 14 to indicate permission to use the bus. Terminal devices 11-, . 11-2. −
. . , a line 19 for transmitting a bus acquisition signal (BG) transmitted to 11-n indicates that each terminal device 11-0 to 11-o is using the bus in response to this bus acquisition signal (BG). A line that transmits a busy signal (BUSY) that indicates that
Reference numeral 20 denotes a line added in this embodiment, which transmits a refresh busy signal indicating that the memory device is being refreshed.

In this embodiment, as shown in FIG. 3, the bus priority determining means 14 receives bus requests from each terminal device, and sets a priority level to permit only the request from the - terminal device according to a predetermined priority order. Encoder 21 and
A decoder 22 generates a bus permission signal (BG) to the terminal device selected by the priority encoder 21.

Further, in this embodiment, the memory device 12 is provided with a refresh control device.

As shown in FIG. 4, this refresh busy signal generator and memory control device 33 receives a clock signal and generates a refresh request timing signal, a refresh counter section 31, and the actual refresh operation timing for the memory array. It consists of a memory control section 32. Two flip-flops 34 and 35 hold the refresh request timing signal from the refresh counter section 31 and generate a refresh busy signal via the gate 38 in synchronization with the bus timing, and this refresh busy signal (RFBSY) A third flip-flop retains the signal from the gate 36, which turns on when the on-state signal (BUSY) is off, and outputs a signal (RFGO) for actually refreshing the memory array. 37.

Furthermore, in this embodiment, each terminal device 11-1 to 11
-n has a part of the bus master which also serves as memory access prohibition means. As shown in FIG. 5, this part of the bus master includes a master control section 41 and a first gate that takes the logical sum of these in response to access requests from the master control section 41 to input/output devices and memory devices. A first flip-flop 4 holds a signal of 42 and outputs it as a bus request signal (BRQ) via a second gate 43.
4, and a determination case 45 that determines the conditions for acquiring a bus.
and a second flip-flop which holds the output of the decision gate 45 and generates a busy signal and an execution signal (CYGO) which is input to the master control unit and causes it to output addresses, data, etc. onto the bus. 46. Then, the above-mentioned judgment gate turns on the second flip-flop under the following conditions.

Condition 1 (When the memory device is not being refreshed and the bus is open) ■The bus request signal (BRQ) is on. ■The refresh busy signal (RFBSY) is off. ■The bus permission signal (BG) is on. ■Bus use signal (BUSY) or off state condition 2 (when the memory device is being refreshed, but the bus is open and an access request is made to the input/output device) ■Bus use request signal (BRQ) is on. ■ Refresh busy signal (RFBSY) is on. Bus use permission signal (BG) is on. Bus use signal (BUSY) is off. Master control circuit memory request signal (MEM) is off. The configuration allows the bus to be used even while the memory device is being refreshed.

Next, the operation of the bus control system according to this embodiment will be explained.

FIG. 6 shows a timing chart showing an example of the operation of the bus control method according to this embodiment. In this timing chart, two cases where bus requests conflict are shown below the display of the control clock signal. These control clock signals are the bus clock signal (BCLK), main clock signal (MCLK), and clock signal 1 (CLKI).
, clock signal 2 (CLK2), clock signal 3 (
CLK3) and clock signal 4 (CLK4). Among these clock signals, the pass clock signal and the main clock signal are clock signals for synchronization and are supplied to all devices, and clock signals 1 to 4 are provided to the terminal. This is an internal control clock signal generated by the device and the memory device from the above synchronization clock signal.

As for the bus usage order of each terminal device, T terminal device 1 has the highest priority, followed by terminal device 2, . . . , terminal device n in that order.

The first example of operation will be explained below.

Falling timing T of clock signal 1 (CLKI). Assume that terminal device 1 and terminal device 2 simultaneously issue bus use requests (BRQ#1.BRQ#2). This signal is input to the above-mentioned bus priority determining means,
The priority encoder determines the priority, and the decoder outputs a bus acquisition signal (BG#1) to the terminal device 1 with the higher priority. In the state where the bus acquisition signal is generated, the refresh busy signal (RF BSY ) from the memory device is in an off state, and the timing T of clock signal 2 (CLK2).

Terminal device 1 acquires the bus and sends a busy signal (BUSY).
) is turned on to notify other terminal devices that the bus is in use, and the bus use request (BRQ#1) is dropped. This causes the terminal device 1 to access the memory device.

At this time, the bus use request (BRQ well 1) is sent as a busy signal (B
At the same time that the bus acquisition signal (BCl2) from the bus priority determining means to the terminal device 2 turns on, the bus cannot be used because the busy signal (BUSY) is on. At this time, when the memory device attempts to perform refresh, it sends a refresh request signal (RFRQ) and a refresh busy signal (RFBS).
Y) is turned on, but since the terminal device R1 is being accessed, no refresh is performed during the first cycle, and the busy signal (BUSY) is turned off, and at the bus acquisition timing T1 of the next second cycle. Execute refresh in the current state (RFGO). In this $2 cycle, the bus use request (BRQ#2) of terminal device 2 is also in the on state, but the refresh busy signal (RFBSY
) is on, so the memory device cannot be accessed. And this terminal device 2 is the next third terminal device.
In the cycle, it is assumed that the memory device can be accessed while the refresh busy signal is in the off state.

Next, another example of the operation of the bus management system according to the tree embodiment will be described. In the 1'th cycle, as in the first cycle described above, a bus use request (BR
Q#L, BRQ#2) compete, causing the terminal device l to access the memory device while the memory device generates a refresh request (RFRQ).

At this time, if the terminal device 2's bus use request is not for accessing memory but for accessing an input/output device, the terminal device 2
access to the input/output device.

As explained above, according to this implementation directive, refresh of the memory device is executed in synchronization with the pasta lock and main clock of the information processing system, so there is no wasted processing, and also when the memory device is refreshing However, since the terminal device can access devices other than the memory device, such as input/output devices, it is possible to prevent situations where the bus becomes unavailable while the memory device is being refreshed, allowing the information processing device to operate more efficiently. can do.

(Effects of the Invention) As explained above, according to the present invention, the bus management method is controlled so that the memory device is refreshed in synchronization with the bus clock and the main clock, and the memory is refreshed. A refresh busy signal generating device is provided that generates a refresh busy signal to indicate that the refresh busy signal is in progress, a transmission path for transmitting the refresh busy signal is provided on the common bus, and each information processing device is configured to receive the refresh busy signal. A memory access prohibition means is provided to prohibit access to the memory device when the memory device is in use. For this reason, refresh of the memory device is executed in synchronization with the bus clock and main clock of the information processing system, so if the refresh is already in progress when accessing the memory device (as in the case of asynchronous access), access will be delayed compared to synchronous access. Since the terminal device can access devices other than the memory device, such as input/output devices, even when the memory device is refreshing, the bus This has the effect that it is possible to prevent a situation where the information processing device becomes unusable, and the information processing device can be operated efficiently.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the bus control method according to the present invention, and FIG. 3 is a diagram showing the structure of the bus priority determining means of the bus control method shown in FIG. 4 is a block diagram showing the structure of the memory device using the bus control method shown in FIG. 2, FIG. 5 is a block diagram showing the structure of each terminal using the bus control method shown in FIG. FIG. 6 is a timing chart showing the operation of the bus control method shown in FIG. 2, and FIG. 7 is a block diagram showing an information processing system to which the conventional bus control method is applied. 1-1 to 1-n... Information processing device 2... Memory device 3... Input/output device 4... Shared bus 5... Refresh busy signal generation means 6... Transmission line 7-1 ~7-n...Memory access prohibition means 8...
Bus priority determining means Yumika Kyoko Figure 7

Claims (1)

[Claims] A plurality of information processing devices (1
_-_1, 1_-_2, ..., 1_-_n) and these information processing devices (1_-_1, 1_-_2, ...,
In a bus control method for controlling a common bus (4) that connects a memory device (2) that is commonly accessed (1_-_n) and requires refreshing at regular intervals and other input/output devices (3). The memory device (2) has a refresh busy signal that controls the operation of the memory device (2) to refresh it in synchronization with the bus clock and the main clock, and generates a refresh busy signal that indicates that the memory is being refreshed. A generating device (5) is provided, a transmission line (6) for transmitting the refresh busy signal is provided on the common bus (4), and each information processing device (1
_-_1, 1_-_2, . . . , 1_-_n) includes memory access prohibition means (7) for prohibiting access to the memory device when receiving the refresh busy signal.
_-_1, 7_-_2, ..., 7_-_n).