JPH10269167A - Memory access system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of data transfer delay time due to the competition of access requests and to avoid the reduction of a transfer rate of a data bus. SOLUTION: Continuous logic addresses are allocated to different memory of a memory part 2, and also a switching part 3, which separately connects each memory to plural bus masters in accordance with each memory and consists of plural switches is provided. An access controlling part 1, in accordance with an access request from an optional bus master to an optional logic address, connects the memory that has the logic address to the bus master at a switch corresponding to the memory. Also, an intervention is performed and an access right is given to any of bus masters only in the case of the competition of access requests from plural bus masters to the same memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system, and more particularly to a memory access system for accessing a shared memory to which a predetermined logical address is assigned by a plurality of bus masters at high speed. .

[0002]

2. Description of the Related Art With the recent increase in the speed of networks, there is a demand for improved performance of network connection devices. For this reason, it is necessary for the network connection device to try to reduce the internal delay during data transfer and to improve the data processing capability inside the device, and high-speed access to the data buffer memory is also important inside the network connection device. Come.

In order to realize high-speed access to a data buffer memory formed in a network connection device, it is necessary to reduce access wait time due to contention for access to a memory, and to transfer a data bus for accessing a memory. It is necessary to perform memory access control that can improve capacity. In a conventional memory access method, as shown in FIG. 5, a plurality of bus masters access an arbitrary memory via one common data bus.

In FIG. 5, reference numeral 52 denotes a plurality of memories # 1 to # 2.
A memory unit for realizing an arbitrary logical address area from #m;
54 is a memory section 52 via one shared data bus 59.
Is a bus master unit composed of a plurality of bus masters # 1 to #n that share and access each memory. The access control unit 51 responds to a memory access signal 57 from any of the bus masters # 1 to #n to convert the logical address notified by the memory access signal 57 into a corresponding physical address on the memory unit 52. And the memory corresponding to the physical address is selected by the memory control signal 55.

At the same time, the access control unit 51 outputs an arbitration response signal 58 to the bus master.
In response, the bus master has a common data bus 5
9 is occupied, and predetermined data is read from the memory selected by the memory control signal 55. When the memory access signal 57 is received from a plurality of bus masters at the same time, the access control unit 51 selects one of the bus masters for which an access request has been made by predetermined arbitration control.

[0006] Then, the same memory selection control as described above, that is, the logical address notified by the memory access signal 57 from the bus master is converted into a physical address on the memory unit 52, and the logical address corresponding to the physical address is converted. The memory to be used is selected by the memory control signal 55. At the same time, the access control unit 51 outputs an arbitration response signal 58 to the bus master.

[0007] In response, the bus master occupies the common data bus 59 and reads predetermined data from the memory selected by the memory control signal 55. In response to the end of a series of memory accesses by the bus master, the access control unit 51 performs the same arbitration control and memory selection control as described above on the bus master that has requested access first. Had become something.

[0008]

However, in such a conventional memory access system, a plurality of bus masters access a shared memory via one shared data bus, and a plurality of bus masters access the shared memory. -When access requests from the masters conflict, only the bus master that has acquired the access right through arbitration accesses the memory, so other buses that could not acquire the access right through arbitration The master cannot access the memory until at least the series of memory access by the bus master that has acquired the access right ends and the next arbitration starts, and the data transfer delay time as a whole However, there is a problem that the number increases.

Further, since each bus master is connected by one shared data bus, the bus masters share the transfer rate of one data bus, and from the viewpoint of each bus master, the transfer of the data bus is performed. There was a problem that the rate was reduced. An object of the present invention is to provide a memory access method capable of suppressing an increase in data transfer delay time due to contention of an access request and avoiding a reduction in a data bus transfer rate. The purpose is.

[0010]

To achieve the above object, a memory access method according to the first aspect of the present invention provides a plurality of buses for each memory of a memory unit.
A switch unit for connecting any one of the masters individually and in parallel, and a memory to which a logical address is assigned in response to an access request for an arbitrary logical address from each bus master. With respect to a plurality of bus masters whose access requests conflict, one of the plurality of bus masters is selected, and the selected bus master is individually connected to the memory via the switch unit. Thus, the access from the bus master to the memory is permitted, and for one bus master that does not conflict with the access request to the memory to which the logical address is assigned, the memory is transferred to the memory via the switch unit. By connecting masters individually, an access control unit that permits access from bus master to memory It is obtain things.

Therefore, with respect to a plurality of bus masters whose access requests compete for the same memory, one of the plurality of bus masters is selected, and the bus master is selected from the plurality of bus masters via the switch unit. The selected bus masters are individually connected and access to the memory is permitted. Further, for one bus master whose access request does not conflict with the same memory, the bus master is individually connected to the memory via the switch unit, and access to the memory is permitted.

According to a second aspect of the present invention, in the memory access method according to the first aspect, consecutive logical addresses are assigned to different memories. Therefore, when successive logical addresses are sequentially accessed, different memories are sequentially accessed. According to a third aspect of the present invention, in the memory access method of the second aspect, consecutive logical addresses are cyclically allocated to each memory in a predetermined order. Therefore, when successive logical addresses are sequentially accessed, each memory is accessed in a predetermined order.
According to a fourth aspect of the present invention, in the memory access method according to the first aspect, a plurality of switches provided for each memory of the memory unit and selectively connecting any one bus master to each memory. , To constitute a memory section. Therefore, each memory and an arbitrary bus master are individually connected in parallel via a switch provided for each memory.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a memory access method according to an embodiment of the present invention.
Reference numeral 2 denotes a memory unit for realizing an arbitrary logical address area from the plurality of memories # 1 to #m. -It is a bus master section composed of a master.

Reference numeral 3 denotes a plurality of switches provided for each of the memories # 1 to #m of the memory unit 2 and connecting the corresponding memory to one of the bus masters # 1 to #n. Switch section. Reference numeral 1 denotes arbitration control for selecting any one of the bus masters in response to an access request from any of the bus masters # 1 to #n, memory selection control for selecting a memory corresponding to a predetermined logical address, and selection. And an access control unit that performs switch control for connecting the bus master and the memory by a switch.

In this case, as shown in FIG. 4, in the memory section 2, the logical addresses 2A are sequentially and horizontally allocated to the respective memories arranged in parallel. In FIG. 4, the memory unit 2 is composed of three memories.
Is configured as an example, and the logical address “A00” is assigned to the physical address “B00” of the memory 21.

The next logical address "A01" is stored in the memory 22.
Is assigned to the physical address “B00” of the memory 23, and the logical address “A02” is further assigned to the physical address “B0” of the memory 23.
0 ”. In addition, the logical address “A0
3 returns to the beginning and the physical address “B0
1 ", and thereafter, in the same manner,
Each of the 23 same physical addresses 2B is allocated in the horizontal order.

As described above, consecutive logical addresses are assigned to different memories 21 to 23, for example,
By circulating and allocating to each of the memories 21 to 23, such as 1, a memory 22, a memory 23, a memory 21,..., A continuous logical address is accessed as in most memory accesses. In such a case, the memory corresponding to each logical address is switched for each access. This prevents continuous access to the same memory even when accessing continuous logical addresses.

Next, the operation of the present invention will be described with reference to FIG. First, an example in which only the bus master # 1 of the bus master unit 4 issues an access request will be described.
In response to the memory access signal 7 from the bus master # 1, the access control unit 1 detects an access request to a predetermined logical address. Next, it is determined whether or not another bus master has requested access to the same memory having the predetermined logical address, that is, whether or not a conflict has occurred.

In this case, since no conflict occurs, the access control unit 1 converts the logical address into a physical address on the memory unit 2. Subsequently, by outputting the memory control signal 5 corresponding to the physical address,
A corresponding memory in the memory unit 2, for example, a predetermined address area of the memory # 1 is selected. At the same time, the access control unit 1 outputs a switch control signal 6 to the switch # 1 in the switch unit 3 provided corresponding to the memory # 1.

Thus, via this switch # 1,
The memory data bus 9 of the memory # 1 is connected to the master data bus 10 of the bus master # 1 that has requested access. Therefore, the bus master # 1 that has issued the access request starts accessing the memory # 1 having the predetermined logical address via the switch # 1 in response to the arbitration response signal 8 from the access control unit 1.

Subsequently, when the bus master # 1 accesses a logical address that follows the logical address accessed immediately before, the bus master # 1 outputs a memory access signal 7 indicating the logical address. In response, the access control unit 1
In the same manner as described above, it is determined whether or not there is a conflict, and after confirming that there is no conflict, the memory control signal 5 corresponding to the logical address is output.

In this case, since the previous logical address and the next logical address are continuous, according to the above-described logical address assignment, the memory unit 2 is not a memory # 1 corresponding to the previous logical address, but a memory # 1. Memory # 2 next to it
Will be selected. In parallel with this, similarly to the above, the switch control signal 6 is output from the access control unit 1 and the arbitration response signal 8 is output, and the switch #
2, access from the bus master # 1 to a logical address on the memory # 2 that is subsequent to the previous logical address is started.

On the other hand, the bus master # of the bus master unit 4
A case will be described as an example where 1 and # 2 simultaneously make access requests to logical addresses on the same memory. In this case, the memory access signals 7 indicating the logical addresses on the same memory are simultaneously output from the bus masters # 1 and # 2 to the access control unit 1, respectively. In response to this, the access control unit 1 determines that a conflict has occurred, and performs one of the arbitration controls to select any one, for example, the bus master # 1 having a smaller number.

Thereafter, in the same manner as described above, for example, the bus master # 1 and the memory # 1 are connected via the switch # 1 to enable access. Further, the arbitration response signal 8 is not output to the other bus master whose access right has not been obtained due to the arbitration, here, the bus master # 2. As a result, the bus master # 2 enters a standby state.

After the access to the memory # 1 is completed, the bus master # 1 outputs a new memory access signal 7 in order to access consecutive logical addresses. In response to this, after confirming that there is no conflict, the access control unit 1 communicates with the memory # 2 and the bus
It is connected to Master # 1 to enable access.

Further, at this time, after confirming that there is no contention with respect to the bus master # 2 from which the access right has not been obtained by the previous arbitration, the memory # 1 and the bus master # 2 is connected to enable access. Thus, access from the bus master # 1 to the memory # 2 via the switch # 2 and access from the bus master # 2 to the memory # 1 via the switch # 1 are simultaneously performed in parallel. Thus, a plurality of bus masters can access the memory unit 2 in parallel.

As described above, continuous logical addresses are allocated to different memories of the memory section 2, and switches for connecting each memory and a plurality of bus masters are provided corresponding to each memory, so that an arbitrary bus is provided. In response to an access request for an arbitrary logical address from the master, a memory having the logical address and the bus master are individually connected in parallel by a switch. Also, arbitration control is performed only when access requests for the same memory from a plurality of bus masters conflict, and an access right is given to any one of the bus masters.

Therefore, at the time when the access to the same memory by the bus master that has previously acquired the access right ends, the other bus masters that could not acquire the access right can access the memory. As a result, as compared with the conventional case where a plurality of bus masters access the shared memory via one shared data bus, even if the access right cannot be obtained due to arbitration, the access right is first obtained. There is no need to wait for memory access until all memory accesses by the bus master that has acquired the data have been completed, suppressing an increase in data transfer delay time due to contention of access requests and avoiding a reduction in the data bus transfer rate. You.

[0029]

2 and 3, an embodiment of the present invention will be described in which three bus masters make simultaneous access requests to four consecutive logical addresses. FIG. 2 is a memory diagram illustrating one embodiment of the present invention.
FIG. 3 is a block diagram of the access method, and FIG. 3 is a timing chart showing signals of respective parts in FIG. 2, and the same or similar parts as those described above (see FIG. 1) are denoted by the same reference numerals.

In FIG. 2, reference numerals 71 to 73 are signals constituting the aforementioned memory access signal 7, 71 is an address signal indicating a logical address to be accessed, 72 is an address enable signal indicating the validity of the address signal 71, 7
Reference numeral 3 denotes a continuous access enable signal indicating that an access request is made to a logical address following the logical address currently requested in the next access request. The access control unit 1 uses the address enable signal 72 as a memory access request signal for arbitration control.

In this case, it is assumed that the access control section 1 synchronizes and executes each process for each of the phases T0 to T9 having a predetermined time length. Further, each of the bus masters # 1 to # 3 has data "D00" to "D0", respectively.
3 are stored in the logical addresses “A00” to “A0”.
It is assumed that access up to "3" is continuously performed.

The logical addresses "A00" to "A0"
It is assumed that “3” is sequentially assigned to the memories arranged in parallel in the memory unit 2 in the horizontal order as shown in FIG. Each of the bus masters # 1 to # 3 is connected to all the switches # 1 to # 3.
, But may be connected individually as shown in FIG.

In phase T1, bus master # 1
To # 3, the address signals 71 # 1 to 71 # 3 indicating the logical address "A00" and the address enable signal 7
2 # 1 to 72 # 3 and a continuous access enable signal 7
3 # 1 to 73 # 3 are output simultaneously. In response to this, the access control unit 1 determines that access requests to the same memory # 1 are in conflict and performs a predetermined arbitration control, and performs any one of these bus masters # 1 to # 3,
For example, assume that the bus master # 1 with the smallest number is selected.

In the subsequent phase T2, the access control unit 1 performs a memory selection control by selecting a physical address corresponding to the requested logical address “A00”, in this case, a physical address “B00” of the memory # 1. Outputs control signal 5 # 1. In parallel with this, the access control unit 1 performs switch control as “M # 1” switch control signal 6 # 1 for instructing the switch # 1 corresponding to the memory # 1 to select the bus master # 1. Is output.

Thus, the memory data bus 9 # 1 of the memory # 1 and the bus master # 1 are connected via the switch # 1.
Master data bus 10 # 1. Therefore, the bus master # 1 starts accessing the memory # 1 in response to the arbitration response signal 8 # 1 output from the access control unit 1 in the phase T2. “D00” read from the logical address “A00” is input to the bus master # 1 via the switch # 1.

In the subsequent phase T3, the next logical address "A01" is output from the bus master # 1 by the address signal 71 # 1. At this time, the previous phase T
2, the address enable signal 72 # 1 is not output because the access right has already been acquired.

In the phase T2, the other bus masters # 2 and # 3, for which the access right has not been obtained, thereafter transmit the address signals 71, 71 until the access right is obtained.
An address enable signal 72 and a continuous access enable signal 73 are held and output. Therefore, in phase T3, the access control unit 1
Since no conflict has occurred with the logical address “A01” requested by No. 1, the memory control signal 5 # 2 for selecting the corresponding physical address “B00” of the memory # 2 is output in the same manner as described above. I do.

In parallel with this, a switch control signal 6 # 2 of "M # 1" for selecting and instructing the bus master # 1 is output to the switch # 2 corresponding to the memory # 2. As a result, the memory # 2 is connected to the bus master # 1 via the switch # 2, and in response to the arbitration response signal 8 # 1 from the access control unit 1, the memory # 2 is controlled by the bus master # 1.
Access is started.

On the other hand, the access control unit 1 determines that a conflict has occurred since the access requests of the bus masters # 2 and # 3 indicate the logical addresses of the same memory, and performs arbitration control in the same manner as described above. In this case, the access control unit 1
The bus master # 2 is selected, and the physical address “B00” is output as the memory control signal 5 # 1 for the memory # 1. In parallel with this, "M # 2" for selecting and instructing the bus master # 2 is output as the switch control signal 6 # 1 for the switch # 1.

As a result, the memory # 1 is connected to the bus master # 2 via the switch # 2, and the bus master # 2 is responded to the arbitration response signal 8 # 2 from the access control unit 1.
2 starts memory access. Therefore,
In phase T3, memory # 2 by bus master # 1
And the access by the bus master # 2 to the memory # 1 are performed simultaneously and in parallel. The waiting time for the bus master # 2 is a period of the phases T1 and T2.

In the subsequent phase T4, each bus master # 1 to # 3 requests access to a separate memory, so that no conflict occurs. Therefore, the access control unit 1 outputs the physical address “B00” as the memory control signal 5 # 3 for the memory # 3, and outputs the switch control signal 6
"M # 1" for selecting and instructing bus master # 1 as # 3
Is output.

Further, the access control unit 1 sends the physical address “B0” as the memory control signal 5 # 2 for the memory # 2.
In addition to outputting "0", "M # 2" for selecting and instructing the bus master # 2 is output as the switch control signal 6 # 2 for the switch # 2. Further, the physical address “B00” is output as the memory control signal 5 # 1 for the memory # 1, and the bus master # 3 is selected and instructed as the switch control signal 6 # 1 for the switch # 1.
# 3 "is output.

Thus, in phase T4, bus master # 1 accesses memory # 3, bus master # 2 accesses memory # 2, and bus master # 3 accesses memory # 1. Are simultaneously performed in parallel. The waiting time for the bus master # 3 is a period of the phases T1 to T3.

In the subsequent phase T5, each of the bus masters # 1 to # 3 requests access to a separate memory, so that no conflict occurs here. Therefore, the access control unit 1 sends the physical address “B0” as the memory control signal 5 # 1 for the memory # 1.
1 ", and outputs" M # 1 "as a switch control signal 6 # 1 for the switch # 1 to select and instruct the bus master # 1.

The access control unit 1 sends the physical address “B0” as the memory control signal 5 # 3 for the memory # 3.
0 ", and outputs" M # 2 "as a switch control signal 6 # 3 for switch # 3 to select and instruct bus master # 2. Further, the physical address "B00" is output as the memory control signal 5 # 2 for the memory # 2, and the bus master # 3 is selected and instructed as the switch control signal 6 # 2 for the switch # 2.
# 3 "is output.

Thus, also in phase T5, access to memory # 1 by bus master # 1, access to memory # 3 by bus master # 2, and access to memory # 2 by bus master # 3. Are simultaneously performed in parallel. Further, in the subsequent phases, similarly, each bus master # 1 to # 3
Then, different memories # 1 to # 3 are individually accessed in parallel via switches # 1 to # 3.

[0047]

As described above, according to the first aspect of the present invention, each switch for individually connecting one of a plurality of bus masters to each memory of the memory unit in parallel. For a plurality of bus masters whose access requests compete for the same memory, any one of the plurality of bus masters is selected, and the bus master is selected via the switch unit. The selected bus masters are individually connected to permit access to the memory, and for one bus master whose access request does not conflict with the same memory, the access to the memory is performed via the switch unit. The bus masters are individually connected to permit access to the memory.

Therefore, at the time when the access to the same memory by the bus master that has previously acquired the access right ends, the other bus masters that have not been able to acquire the access right can access the memory. And 1
Compared to the case where multiple bus masters access the shared memory via one shared data bus, even if the access right cannot be obtained due to arbitration, all the memory by the bus master that has obtained the access right first There is no need to wait for memory access until the access is completed, and an increase in data transfer delay time due to contention of access requests is suppressed, and a reduction in the data bus transfer rate is avoided.

According to the second aspect of the present invention, in the memory section, consecutive logical addresses are assigned to different memories. Therefore, when consecutive logical addresses are sequentially accessed, different memories are sequentially accessed. When the bus master sequentially accesses consecutive logical addresses, an increase in data transfer delay time due to contention of access requests is more effectively suppressed, and a decrease in the transfer rate of the data bus is avoided. Claim 3
According to the invention, consecutive logical addresses are cyclically allocated to each memory in a predetermined order. Therefore, when consecutive logical addresses are sequentially accessed, each memory is circularly accessed in a predetermined order. And the processing load on the access control unit can be reduced. Further, the invention according to claim 4 is provided for each memory of the memory unit, and the switch unit is constituted by a plurality of switches for selectively connecting any one bus master to each memory. With a relatively simple configuration and control, each memory and any bus master can be individually connected in parallel.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory access method according to an embodiment of the present invention.

FIG. 2 is a block diagram of a memory access method according to an embodiment of the present invention.

FIG. 3 is a timing chart of signals of respective parts of the embodiment shown in FIG. 2;

FIG. 4 is an explanatory diagram showing assignment of logical addresses.

FIG. 5 is a block diagram of a conventional memory access method.

[Description of Signs] 1 ... access control unit, 2 ... memory unit, 3 ... switch unit,
4 Bus master section, 5 Memory control signal, 6 Switch control signal, 7 Memory access signal, 8 Arbitration response signal, 9 Memory data bus, 10 Master data bus.

Claims (4)

[Claims] 1. A memory access method in which a plurality of bus masters share and access a memory unit composed of a plurality of separate memories to which a predetermined logical address is assigned. Switch units for individually connecting any one of the bus masters in parallel with each other, and the logical address is assigned in response to an access request for an arbitrary logical address from each bus master. For a plurality of bus masters competing for an access request to the memory, any one of the plurality of bus masters is selected, and the selected bus master for the memory is selected via a switch unit. By connecting them individually,
For one bus master that permits access from the bus master to the memory and does not conflict with an access request to a memory to which the logical address is assigned, the bus master is connected to the memory via a switch unit. A memory access method comprising: an access control unit that permits access from the bus master to the memory by individually connecting masters. 2. The memory access method according to claim 1, wherein consecutive logical addresses are assigned to different memories in the memory unit. 3. The memory access method according to claim 2, wherein the memory unit is configured so that consecutive logical addresses are cyclically allocated to each memory in a predetermined order. 4. The memory access method according to claim 1, wherein the switch unit is provided for each memory of the memory unit, and a plurality of switches for selectively connecting any one bus master to each memory. A memory access method comprising: