JPH02146436U - - Google Patents
Info
- Publication number
- JPH02146436U JPH02146436U JP5675489U JP5675489U JPH02146436U JP H02146436 U JPH02146436 U JP H02146436U JP 5675489 U JP5675489 U JP 5675489U JP 5675489 U JP5675489 U JP 5675489U JP H02146436 U JPH02146436 U JP H02146436U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- hybrid
- chips
- wire bonding
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5675489U JPH02146436U (enExample) | 1989-05-17 | 1989-05-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5675489U JPH02146436U (enExample) | 1989-05-17 | 1989-05-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146436U true JPH02146436U (enExample) | 1990-12-12 |
Family
ID=31580862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5675489U Pending JPH02146436U (enExample) | 1989-05-17 | 1989-05-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146436U (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51102566A (en) * | 1975-03-07 | 1976-09-10 | Suwa Seikosha Kk | Shusekikairo |
-
1989
- 1989-05-17 JP JP5675489U patent/JPH02146436U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51102566A (en) * | 1975-03-07 | 1976-09-10 | Suwa Seikosha Kk | Shusekikairo |