JPH02146175A - Memory cell counter electrode voltage supplying circuit - Google Patents

Abstract

PURPOSE:To improve dielectric strength and to freely impress a high voltage at the time of screening by switching the outputs between a low voltage generating circuit and a high voltage generating circuit by means of a switching circuit. CONSTITUTION:At the time of a normal operation, a transistor (TR) Q1 is turned on, a TR Q2 is turned off, and the 1/2 VCC voltage output of a 1/2 VCC generating circuit 1 is generated to an output VCL. At the time of screening, the TR Q1 is turned off, the TR Q2 is turned on, and the high voltage output of a high voltage generating circuit 2 is generated to the output VCL. In such a constitution, the dielectric strength can be improved at the time of the normal operation, and the screening is attained by the high voltage impression which is not less than a supply voltage at the time of screening.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory circuit, and more particularly to a voltage supply circuit for applying a voltage to a counter electrode of a dynamic memory using a one-transistor type memory cell.

[Prior Art] Conventionally, the method of applying voltage to the opposite electrode of a memory cell is as follows:
There was a method of directly connecting the cell counter electrode to the power supply. However, in recent years, due to the dramatic increase in memory cell capacity and the high density of memory cells, the insulating film for forming memory cell capacitance has become thinner and thinner in order to secure the capacitance value. Therefore, as shown in FIG. 3, the cell counter electrode is generally connected to a 1/2 VCC generating circuit 300 that outputs half the voltage of the external power supply (1/2 power supply system). In this way, the electric field strength of the insulating film is reduced by half, improving the breakdown voltage of the product.

[Problems to be solved by the invention] In order to eliminate initial defects in semiconductor integrated circuits and improve their reliability, a test (burn-in) in which semiconductor integrated circuits are operated at high temperatures and high voltages for a certain period of time is carried out. It has been implemented.

This is to remove (screen) initially defective semiconductor integrated circuits by temperature and voltage acceleration.

While the above-mentioned conventional 1/2 power source has the advantage of reducing the electric field strength to half and improving the withstand voltage, it has the disadvantage that the voltage must be increased more than necessary for screening.

[Differences between the invention and the prior art
Whereas only the power supply voltage is involved, the present invention has the difference that two types of voltages, low voltage and high voltage, can be freely applied to the cell counter electrode by switching between 1/2 power supply voltage and high voltage. .

Means for Solving Problem E] The gist of the present invention is to provide a memory cell counter-electrode voltage supply circuit that supplies voltage to memory cells formed on a semiconductor substrate, so that the low voltage used during normal operation of the memory cell can be used. A high voltage generation circuit generates a high voltage used during testing of memory cells, and a switch circuit selectively supplies the low voltage and high voltage to the memory cells. be.

[Operations and Effects of the Invention] As explained above, the present invention uses a switch circuit to switch between the output of the low voltage generation circuit and the output of the high voltage generation circuit, thereby improving the withstand voltage during normal operation, and increasing the power supply voltage during screening. Application of the above high voltage has the effect of further screening.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

1 is a 1/2VCC generation circuit, 2 is a high voltage generation circuit using a charge pump, and 3 is a switch circuit for switching the high voltage 1/2VCC. The signal S is an rC internal signal set by an external input, and during normal operation, it turns on transistor Q1, turns off transistor Q2, and outputs VC.
1/2V-CC voltage of the 1/2VCC generation circuit output is generated at L. Conversely, during screening, transistor Q1 is turned off, transistor Q2 is turned on, and a high voltage output from the high voltage generation circuit is generated at the output VCL. Clock φ is Q2
This is a signal that boosts the gate potential of the capacitor C2 by the bootstrap effect of the capacitor C2, and the output P of the oscillation circuit may be used.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

In the high voltage generation circuit 2, transistors Q7...Q
It is characterized by the provision of a voltage clamp circuit consisting of N.
This has the advantage of preventing excessive voltage from being applied to the cell counter electrode.

FIG.

1 ・ ・ ・ ・ ・ ・ ２　・◆　・　・　Φ　・　・ ３　・　・・　・・ Q1~Q? , QN C1, C2・

Claims (1)

[Claims] A memory cell counter electrode voltage supply circuit that supplies voltage to memory cells formed on a semiconductor substrate, and a low voltage generation circuit that generates the low voltage used during normal operation of the memory cell, and a low voltage generation circuit that is used during memory cell testing. 1. A memory cell counter electrode voltage supply circuit comprising: a high voltage generation circuit that generates a high voltage; and a switch circuit that selectively supplies the low voltage and the high voltage to memory cells.