JPH02145077A - Information encoder - Google Patents

Abstract

PURPOSE:To average processing information of each processor and to reduce the entire required processing time by providing plural processors fetching and processing the information of its own role based on an address control signal outputted from a task controller. CONSTITUTION:A task controller 7 discriminates an effective picture element number from the content of an input memory 1 and decides the share of code processing for each of digital signal processors DSP1, DSP2, DSP3 and outputs a control signal to them as an address control signal 8. That is, the area A with comparatively small effective picture element number is expanded to an area A' and similarly, the area C with comparatively small effective picture element number is expanded to an area C' and conversely, the area B with comparatively large effective picture element number is reduced to an area B' through the sharing of the task controller 7. Then the address control signal 8 is response to it is given to the DSP1, DSP2, DSP3 respectively. Thus, the processing of each DSP is averaged and useless waiting time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information encoding device, particularly to improving encoding processing capability using a digital signal processor.

[Prior Art] FIG. 5 shows the fourth part of IEEE, GLOBCOM'87
“Real-time Video Signal Processor Suitable for Pixel Encoding Devices” on page 53 [“A Real TlmeVi
deo Signal Processor 5u1t
able f'or MotionPicture C
oding Applications''] is a multiprocessor configuration diagram.

In FIG. 5, human data (1) is input to a data transfer controller (3), and then required data (4) is transferred to required digital signal processing processors 1 to N (hereinafter referred to as DSP) (2). and each DSP of block 1
After being processed within, the processed data (5) will be processed by each DSP (2) of block 2 in the next processing step.

The assigned areas of each DSP (2) at this time are shown in Figure 6(a).
Shown below. FIG. 6(a) shows 3
In this example, each DSP (2) has equal processing target areas A and B.
, C are distributed.

However, in inter-frame image encoding methods, only a portion of a certain size where there is a difference between the input frame and the previous frame is to be encoded, and for the rest, conditional pixel replenishment processing using the previous frame data is used. is common.

Therefore, even if the number of pixels in the processing target area is the same, if the effective pixel rate is different, the amount of calculation required for processing will be different, and the required amount of calculation or required calculation time will be proportional to the effective pixel rate.

Therefore, each DSP in the interframe image coding method, etc.
Assuming that the number of effective pixels distributed in (2) is distributed as EA and EB%EC, respectively, as shown in Figure 6(b), the required calculation time per block in the DSP parallel configuration is the maximum required processing time. DS sharing area B with ff1M
P processing time, and each DS that shares other ASC areas
After the arithmetic processing, P enters a waiting state and does not perform any processing.

[Problems to be Solved by the Invention] Conventional information encoding devices have been configured as described above, so that there is a bias in information density such as the effective pixel rate within an image, and furthermore, the distribution or density is biased. etc. fluctuate over time, the processing time for the entire multiprocessor is
Since the processing time is that of the DSP that requires the longest processing time among P, there is a problem in that the processing efficiency per DSP1 is low.

The present invention was made to solve such problems, and an object of the present invention is to obtain an information encoding device that can make maximum use of the processing power of a parallel configuration of multiprocessors.

[Means for Solving the Problems] An information encoding device according to the present invention includes a task controller that outputs an address control signal that instructs a plurality of processors to allocate roles so that the number of effective information is equalized, and a task controller as described above. It has a plurality of processors that retrieve and process information about their own roles from memory based on address control signals.

[Operation] According to the information encoding device according to the present invention, since the number of information processed by each processor is equalized, the processing time required for the entire processor block is shortened to nearly the maximum limit.

[Embodiments] Next, the present invention will be explained in more detail based on embodiments shown in the drawings.

FIG. 1 shows an example of an image encoding device as an embodiment of an information encoding device according to the present invention.

In Fig. 1, input data (1) is input memory 1 to 3.
(6) is input. On the other hand, the task controller (7) determines the number of effective pixels from the contents of the input memory (1), and
Each of SPI, DSP2, and DSP3 performs the encoding processing and sends the DSPI, D as an address control signal (8).
@! for each of SP2 and DSP3. Outputs IgD signal.

DSPL and DS that input this address control signal (8)
P2 and DSP3 each issue an address (9) to input memory 1, input memory 2, and input memory 3, read the data (10) to be processed by themselves, and then encode it based on a preset program. Perform processing. D
When SPI, DSP2 and DSP3 complete processing,
Each piece of processed data is output to the output memory (11), and when the output memory (11) reads all data of the DSP block, it outputs the processed data (5) and transmits it to the next DSP block, etc. do.

At this time, each DSP (2) is controlled by the task controller (7) so that the number of effective pixels to be processed by each DSP (2) is equal, so the image encoding processing time is , the processing time difference is controlled to be minimized.

In other words, when encoding an image with an effective number of pixels as shown in FIG. 6(b), area A, which has a relatively small number of effective pixels, is enlarged to A' as shown in FIG. 2(a). Similarly, the L)C region with a relatively small number of effective pixels is enlarged to C′,
Conversely, the task controller (7) allocates calculations so as to reduce the area with a large number of effective pixels to B-, and sends the corresponding address control signal (8) to each DSPI, DSP2
and to DSP3. For example, when the DSPI is given an address control signal (8) for reading and encoding image data of area A', the DSPI issues an address (9) corresponding to area A' to the input memory 1, The corresponding data is input and image encoding processing is performed using a predetermined program.

Similarly, the DSP2 is instructed to perform C' area image encoding processing on the B' area DSP3.

Then, as shown in FIG. 2(b), DSPI, DSP
The effective numbers of pixels EA-1EB- and EC- to be encoded by each of DSP 2 and DSP 3 are approximately equalized, and the total amount of image data processing becomes the same. As a result, the maximum required processing amount M by the apparatus of the present invention is is sufficiently smaller than the conventional maximum required processing iM, and the required processing time per DSP block is reduced.

FIG. 3 shows an interframe encoding device constructed by continuously connecting three stages of DSP blocks, and the processing performed by each DSP block is shown in FIG. 4.

The DSP block 1 (12) inputs the input data (1), calculates a difference signal, performs valid/invalid determination processing, calculates the distribution of the number of video pixels existing in the image data, and sends this information to the task controller (7). send to

Based on the information, the task controller (7) sends out an address control signal (8) instructing address adjustment so that each DSP in the DSP block 2 (13) is equally assigned.

Each DSP in the DSP block 2 (13) performs processing by adjusting the read address as described above.

The same applies to DSP block 3 (14).

In addition, in the above embodiment, an example was shown in which the DSP processing assigned area is controlled based on the effective pixel distribution by area in the image data, but the present invention is not limited to this.
For example, DSP sharing control can be performed by feedback based on the quantity distribution of general transmission information.

[Effects of the Invention] As explained above, the present invention has a plurality of processors CD5
Since the structure adaptively controls the processing allocation of P), the processing of each DSP is equalized, unnecessary waiting time is reduced, and the processing capacity of the apparatus as a whole is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image encoding device using a plurality of processors according to an embodiment of the present invention, and FIG. 2 is an example of processing area adaptive control of an image encoding device according to an embodiment of the present invention. FIG. 3 is a configuration block diagram of a multiprocessor block interframe encoding device according to another embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the device shown in FIG. The figure is a block diagram of the configuration of a conventional encoding device, and FIG. 6 is an explanatory diagram of a method for allocating a plurality of processors in the conventional device. In the figure, (1) is input data, (2) is a digital signal processing processor, (3) is a data transfer controller, and (5)
is processed data, (6) is input memory, (7) is task controller, (8) is address control signal, (9) is address, (10) is data, (11) is output memory, (12)
) is DSP block 1, (13) is DSP block 2,
(14) is the DSP block 3, and (15) is a frame memory. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Masuo Oiwa (2 others) Block diagram of image encoding device according to the embodiment (a) Memory area division (b) Effective pixel number distribution by area Conventional processor allocation explanatory diagram - Part 4 Nffi J L /'1 To \eII'V- To 'peoI'N

Claims (1)

[Claims] A memory that stores and sends input information, and an address that calculates the number of valid information among the information to be processed and adaptively divides the information to be processed into multiple pieces so that the number of valid pieces of information for multiple processing divisions is equal. a task controller that outputs a control signal;
Multiple digital signal processing that inputs the address control signal of this task controller, adjusts the address of the assigned area to be processed, reads information from the memory, executes encoding processing, and outputs the processing result. An information encoding device comprising a processor.