JPH02143615A - Echo elimination type transmitter - Google Patents

Abstract

PURPOSE:To reduce the error of echo elimination due to a phase deviation between the transmission reception timings by correcting a pseudo echo signal with a 1st and a 2nd correction signal generated based on the deviation of the time interval of the transmission and the reception timing signal respectively. CONSTITUTION:A transmission digital signal 3 is converted into a transmission analog signal 4 by a D/A converter 1 and sent to a two-wire subscriber line 6 by a hybrid circuit 5. On the other hand, the reception signal sent from the line 6 is converted into a reception digital signal 9 by an A/D converter 8. Then after the echo of the transmission signal is eliminated by subtractors 20 - 22, the result is sent as a reception digital signal 22. In this case, a control circuit 18 generates control signals 14A - 15C based on the phase deviation of the clock 2 and inputs them to filters 12,13, a prescribed coefficient is multiplied with the signal 3, the 1st and 2nd correction signals 16,17 are outputted as the result and the subtractors 22,20,21 subtract a pseudo echo signal 11 and correction signals 16,17 respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an echo cancellation type transmission device that performs bidirectional transmission between digital transmission and analog transmission using a full-duplex communication system, and particularly relates to an echo cancellation type transmission device that performs bidirectional transmission between digital transmission and analog transmission using a full-duplex communication system, and particularly relates to Regarding what corresponds to the phase shift of.

[Conventional technology]

Generally, an echo cancellation type transmission device is used to perform bidirectional transmission of digital signals and analog signals using a full-duplex communication method.

A conventional echo cancellation type transmission device converts transmitted digital data from a digital switch network side into an analog signal using a D/A converter, and transmits the analog signal to a two-wire subscriber line side via a hybrid circuit. Furthermore, the analog signal transmitted from the 2-wire subscriber line side is passed through a hybrid circuit to an A/D converter, which converts it into received digital data, and a subtracter converts it into a pseudo echo signal. After subtracting the value, it is sent to the digital switch network side. The pseudo echo signal is generated by passing the transmitted digital data through a filter.

[Problem to be solved by the invention]

In the echo cancellation type transmission device described above, a D/A converter and an A/
If there is a phase shift in the operating clock of the D converter, there is a drawback that the error between the echo and the pseudo echo signal increases and the echo removal ability decreases.

For this reason, conventionally, it has been necessary to take measures to minimize deviations in the operating clocks of D/A converters and A/D converters.

SUMMARY OF THE INVENTION In view of these problems, it is an object of the present invention to provide an echo cancellation type transmission device that can cope with phase shifts in transmission timing and reception timing.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides an echo cancellation type transmission device having the following means.

(1) Transmission means that synchronizes with the transmission timing signal, converts the transmission digital signal transmitted from the full-duplex communication digital transmission line into a transmission analog signal, and transmits it to the analog transmission line.

(2) A receiving means for converting the received analog signal received from the analog transmission line into a received digital signal and transmitting it to the full-duplex communication digital transmission line in synchronization with the reception timing signal.

(3) A pseudo-echo signal generating means for generating a pseudo-echo signal based on the transmission digital signal, which indicates the amount of echo when the time intervals of the transmission timing signal and the reception timing signal are both constant.

(4) Detecting the time interval deviation of the transmission timing signal,
A first correction signal generation means for generating a first correction signal for the pseudo echo signal based on the detection result and the transmitted digital signal.

(5) Detecting the time interval deviation of the reception timing signal,
A second correction signal generation means for generating a second correction signal for the pseudo echo signal based on the detection result and the transmitted digital signal.

(6) Echo removal means for subtracting the received digital signal based on the pseudo echo signal and the first and second correction signals.

[Effect]

The echo cancellation type transmission device according to the present invention uses the transmitting means and the receiving means to transmit signals between the full-duplex digital transmission line and the analog transmission line in synchronization with the transmitting timing signal and the receiving timing signal.

At this time, the echo canceling means subtracts the pseudo echo signal from the received digital signal to remove the echo of the transmitted digital signal included in the received digital signal. If a shift occurs in the time interval of the transmission timing or reception timing signal, the error between the pseudo echo signal and the actual echo increases. The above-mentioned error can be dealt with by correction.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows an echo cancellation type transmission device according to an embodiment of the present invention.

In the figure, a D/A converter 1 converts a transmitted digital signal 3 into a transmitted analog signal 4 in synchronization with a clock 2. The transmitted digital signal 3 is a transmitted signal in a full-duplex communication system. The hybrid circuit 5 is
It transmits the transmission analog signal 4 to the two-line subscriber line 6, and receives the reception analog signal 7 received from the two-line subscriber line 6, and transmits it to the A/D converter 8. A/D
The converter 8 converts the received analog signal 7 into a received digital signal 9 in synchronization with the clock 2.

The filter 10 generates a pseudo echo signal 11 from the transmitted digital signal 3. Filters 12.13 transmit digital signals 3 and control signals 14A, 14B.
, 15A, 15B, and 15C to generate first and second correction signals 16.17. The control circuit 18 is
Detect the phase shift of the clock 2, and based on this detect the control signals 14A, 14B, 15A for the filter 12.13.
115B and 15C. Subtractor 19~
21 is for subtracting the pseudo echo signal 11 and the first and second correction signals 16 and 17.

The received digital signal 22 after the subtraction is transmitted as a received signal in the full-duplex communication system.

A transmission digital signal 3 transmitted to this device is converted into a transmission analog signal 4 by a D/A converter and transmitted to a two-line subscriber line 6 by a hybrid circuit 5. On the other hand, the received signal transmitted from the two-line subscriber line 6 is outputted by the hybrid circuit 5 as a received analog signal 7 to an A/D converter 8 and converted into a received digital signal 9.

After the echoes of the transmission signal are removed by subtracters 19 to 21, the signal is transmitted as a reception digital signal 22.

Through the above-described operations, this device performs bidirectional transmission of digital signals and analog signals using a full-duplex communication method.

Before explaining the details of each filter 0.12.13, the influence of the phase shift of clock 2 on echo removal will be explained first.

2 to 4 show the relationship between the echo due to the transmitted analog signal and the clock 2 during one time interval. In these figures, (a) is the clock 2, (b) is the waveform of the transmitted analog signal 4 at an arbitrary time interval, and (C) is the waveform of the transmitted analog signal 4 at an arbitrary time interval.
shows the waveform of an echo caused by the transmitted analog signal 4 in (b).

The transmission analog signal 4 transmitted between timing tks k+1 will be explained. As shown in FIG. 2, when there is no shift in clock 2, the sampling values of the echo of the transmitted analog signal are R, R1R3. As shown in FIG. 3, clock 2 has timing jk+l, j
If a lag of time ΔT occurs between tk+2 and tk, the sampling timing of subsequent echoes will be shifted. 2.j. Errors ΔR2 and ΔR occur in the sampling values at 3. Similarly, clock 2 has timing tk. When a time difference of ΔT occurs between 2 and tks−3, an error ΔR3 occurs in the sampling value at timing t2.3. Also, as shown in FIG. 4, the time Δ between clock 2 and timing t8, k +,
If a shift in T occurs, the sampling timing of subsequent echoes will be shifted, and the waveform of the echo will change as the waveform of the transmitted analog signal 4 changes.
Errors ΔW1, ΔW, and ΔW3 occur in the sampling values at timings tk+6, tk+2, and t5.3.

When a shift occurs at a certain time interval, the three types of errors described above occur in a superimposed manner. FIG. 5 shows this situation. In the figure, (a) shows the clock 2, and (b) to h) show the echoes of each transmitted analog signal transmitted at each time interval.

In the following description, to identify the timing for each part of the echo and its error, the symbol is followed by (n).
Attach. Here, n is tn-1 whose value is time 7,
This indicates that the value is related to the echo generated by the transmitted analog signal 4 transmitted during tII.

Timing tk Sk. Assume that a shift of time ΔT occurs in a time interval of 9. In this case, the echo sampling value R(n) at each timing th is expressed by the following equations. That is, R(k+1), R(k+2), R
(An error occurs for k+2>.

R(k> =R+ (k-1) 10R2(k-2)+
R3 (k 3) ...... (1) R
(k+1) =R+ (k) +R2(k 1)+
R3(k2) +ΔW, (k)+ΔR2(
k-1) +ΔR3(k-2)... (2) R(k+2) =R+(k+1)+R2(
k) + R3 (k-1) +ΔW2 (k) +ΔR3 (k 1) ...... (3
)R(k+3) −R+ (k+2>+R2(k+1
)+R, (k) +ΔW3 (k) ...... (4) R(k+4)=R+ (k+3)+R2(k+2)
+R3(k+1) (5) Next, details of each filter 10, 12, and 13 will be explained.

FIG. 6 shows the configuration of the filter 10. Delay circuit 23A
, 23B, and 23C delay the transmitted digital signal 3 by one clock of the clock 2, respectively.

Coefficient registers 24A, 24B, and 24C output predetermined coefficients to multipliers 25A, 25B, and 25C.

Multipliers 25A, 125B, 25C are delay circuits 23A, 2
The outputs of 3B and 23C are multiplied by a predetermined coefficient.

The adder 26 adds the outputs of the multipliers 25A, 25B, and 25C.

In this device, the amount of pseudo echo is calculated by multiplying the transmitted digital signal 3 by a predetermined coefficient. That is, when the timing of clock 2 is t, multipliers 25A and 258125C multiply transmission digital signal 3 by the coefficients output from coefficient registers 24A, 24B and 24C, and obtain R1(n 1>, R2(n
2), output the value corresponding to R3(n-3). Then, the adder 26 calculates R+ (n 1) +R2(n
2) Output the value corresponding to +R3(n-3). This output becomes the pseudo echo signal 11.

FIG. 7 shows the configuration of the filter 12. Delay circuit 27A
, 27B, and 27C delay the transmitted digital signal 3 by one clock of the clock 2, similarly to the configuration of the filter 10. The coefficient registers 28A and 28B are
It outputs predetermined coefficients to multipliers 29B and 29C. Multipliers 29A and 29B are delay circuits 27B and 27C.
The output is multiplied by a predetermined coefficient. The gate circuits 30A and 30B open and close according to control signals 14A and 14B. The adder 31 is the gate circuit 3
This is to add the outputs of 0A and 30B.

In this device, the echo error is calculated by multiplying the transmitted digital signal 3 by a predetermined coefficient, similar to the above-described calculation of the amount of pseudo echo. That is, multipliers 29B and 29C are coefficient registers 28A and 28B.
By multiplying the transmitted digital signal 3 by the coefficient output from ΔRz (n 2), ΔRs (n
Output the value corresponding to 3). and control signal 14
A and 14B open and close gate circuits 30A and 30B, and adder 31 generates a required first correction signal 16. Table 1 shows the timing of the control signals 14A, 14B and the tenth correction signal 16. In the table, let t be the clock timing at which a shift occurs in clock 2.

Table 1 FIG. 8 shows the configuration of the filter 13. Delay circuit 32A
, 32B, and 32C are clock 2 as in the above configuration.
The transmitted digital signal 3 is delayed by one clock. The coefficient registers 33A, 33B, 33C are
It outputs predetermined coefficients to multipliers 34A, 34B, and 34C.

Multipliers 34A, 34B, 34C are delay circuits 32Δ, 3
The outputs of 2B and 32C are multiplied by a predetermined coefficient. The gate circuits 35A, 35B, 35C receive the control signal 15
The opening and closing operations are performed according to A, 15B, and 15C. The adder 36 adds the outputs of the gate circuits 35A, 35B, and 35C.

Similarly to the above, the multipliers 34A, 34B, and 34C multiply the transmission digital signal 3 by the coefficients output from the coefficient registers 33A, 33B, and 33C to obtain ΔWl(
k), ΔW2 (k), and ΔW(k), the gate circuits 35A and 358135C open and close according to the control signals 15A, 115B, and 15C, and the required second correction signal 17 is generated by the adder 36. be done. Control signal 1
Table 2 shows the timings of 5A, 15B, 15C and the second correction signal 17.

(Leaving space below) Table 2 In the embodiment described above, the configuration is shown in which the transmission and reception timings are the same, that is, the D/A converter 1 and the A/D converter 8 operate in synchronization with the same clock. , the present invention can be applied even when the transmission and reception timings are different.

Further, although the filters 10, 12, and 13 are illustrated as having a three-tap configuration, it is of course possible to adopt a configuration with a different number of taps. Furthermore, although we have illustrated a configuration in which the amount of pseudo echo and its correction amount are calculated by multiplying the transmitted digital signal 3 by a fixed coefficient, it is possible to calculate the coefficient as appropriate based on other configurations, such as the amount of clock deviation. hand,
It is also possible to adopt a configuration in which the transmitted digital signal 3 is multiplied.

〔Effect of the invention〕

As described above, according to the present invention, the first correction signal is generated based on the time interval difference between the transmission timing signals, and the second correction signal is generated based on the time interval difference between the reception timing signals. By correcting the pseudo echo signal using the signal, it is possible to reduce errors in echo cancellation due to phase shifts in transmission timing and reception timing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an echo cancellation type transmission device according to an embodiment of the present invention, FIGS. 2 to 4 are relationship diagrams of echoes and clocks due to transmitted analog signals in one time interval, and FIGS. are relationship diagrams between echoes and clocks due to transmitted analog signals at each time interval, Figures 6 to 8.
The figure is a block diagram showing the configuration of filters 10.12.13. 1...D/A converter, 2...Clock, 3...Transmission digital signal, 4...Transmission analog signal, 5......・Hybrid circuit, 6... 2-line subscriber line, 7... Received analog signal, 8... A/D converter, 9... Before subtraction Received digital signal of 10...
...Filter that generates a pseudo echo signal, 11...
...Pseudo echo signal, 12...Filter that generates the first correction signal,
13...A filter that generates a second correction signal,
16...First correction signal, 17...Second correction signal, 18...Control circuit, 19-21...Subtractor, 22. ...Received digital signal after subtraction.

Claims (1)

[Claims] Transmitting means for converting a transmitting digital signal transmitted from a full-duplex communication digital transmission line into a transmitting analog signal and transmitting it to the analog transmission line in synchronization with a transmitting timing signal; A receiving means that synchronizes and converts a received analog signal received from an analog transmission line into a received digital signal and transmits it to a full-duplex communication digital transmission line, and a time interval of both the sending timing signal and the receiving timing signal is constant. A pseudo-echo signal generation means that generates a pseudo-echo signal indicating the amount of echo at a certain time based on a transmitted digital signal; a first correction signal generation means for generating a first correction signal for the echo signal; and a first correction signal generation means for detecting a time interval deviation of the reception timing signal, and based on the detection result and the transmission digital signal, a first correction signal generation means for generating a first correction signal for the pseudo echo signal; A second correction signal generation means for generating a correction signal; and an echo removal means for subtracting the received digital signal based on the pseudo echo signal and the first and second correction signals. Echo cancellation type transmission device.