JPS5961232A - Circuit for detecting lead-in timing of bridged tap equalizer - Google Patents

Abstract

PURPOSE:To generate timing clocks for compensating a factor precisely even if an echo is high, by turning off a gate for a fixed period after detecting an isolated wave. CONSTITUTION:When an echo is high, an isolated wave detecting circuit 2 generates output pulse to a training pulse and the echo. At the time of the first output pulse, an AND circuit 13 is opened and the output pulse is applied to an equalizer 1 as a timing clock. The output pulse is also applied to a shift register 11 and transmitted through the shift register 11 for a fixed period. Since any one of outputs is ''1'' and all the other outputs are ''0'' in said period, the output of an NOR circuit 12 is ''0'' during the period, the AND circuit 13 is closed and an output due to the echo is not outputted from the isolated wave detecting circuit as a timing clock.

Description

Detailed Description of the Invention (Technical IF of the Invention) The present invention provides a bridged tap equalizer having an automatic pull-in function that can correctly extract tap coefficient correction timing. This relates to a pull-in timing detection circuit.

(Prior art and problems) When performing two-way digital communication using a subscriber telephone line, the subscriber line is equipped with branch sections (bridged taps) at key points to connect branch lines in preparation for future demand. is provided, the reflection of the digital signal by the bridged tap causes an echo, which is mixed into the digital signal and causes an error in the transmitted signal. Therefore, in order to cancel such echo components, a bridged tap equalization layer is inserted at the end of the subscriber line.

A vase such as a bridged tap generally has a structure of a feedback filter, and tap coefficients are converged using a training signal like a solitary wave. Therefore, a solitary wave detector is provided to detect the arrival of a solitary wave, and the timing for tap coefficient correction is created based on the output of this detector.

FIG. 1 shows the configuration of a conventional pull-in timing detection circuit in a bridged tap equalizer. In the same figure, ■ is an isometric vase, 2 is a solitary wave detection circuit, and in the isovasa 1, 3 is an adder (Σ), and 4-1.4-2.4-
．． 3 is a delay circuit (D) 5 is a tap coefficient correction circuit, 6-1
．． 6-2 is a multiplier. FIG. 2 is a time chart showing the operation of the solitary wave detection circuit 2 in FIG. The input signal (2) is a timing clock signal output.

During the training period, when the training signal is applied to the adder 3, the output signal of the adder 3 is applied to the delay circuit 4.
-1.4-2.4-3, is added to the tap coefficient correction circuit 5, and is also added to the solitary wave detection circuit 2, where solitary waves are detected at a constant detection slice level. Generates a timing clock in response to the input. The tap coefficient correction circuit 1i115 corrects the coefficient values corresponding to the respective delay circuit inputs in accordance with the timing clock. During the signal transmission period, the input signal passes through delay circuits 4-1 and 4-2, and then goes to multipliers 6 to 1 and 6-2, respectively.
Enter. Multiplier 6-1, 6-2 TE, delay circuit 4-
1. Multiply the signal of 4-2 by the corresponding coefficient value in the tap coefficient correction circuit, and input the multiplication result to the adder 3. Adder 3 generates an echo-compensated output by adding the input signal and the output signal of each multiplier.

In this case, when the echo is small, as shown in FIG. 2(a'), the training pulse A is applied to the detection slice level L, and the echo B is not applied to the slice level L, so the timing clock is set to the training pulse A.
It corresponds only to ゛ζ and occurs. On the other hand, when the echo is large, as shown in FIG. 2(b), both the training pulse A and the echo B reach the detection slice level L, and a timing clock is generated corresponding to both.

Among these, the one for echo is an erroneous timing clock, and in order to avoid malfunction of the tap coefficient correction circuit, it is necessary to prevent such timing clock from occurring, but the conventional pull-in timing detection circuit However, no countermeasures were taken at all.

□ (Objective of the invention) The present invention aims to solve the problems of the prior art, and its purpose is to correct tap coefficients even when the echo is large in a bridged tap equalizer. An object of the present invention is to provide a pull-in timing detection circuit that can correctly generate a timing clock for the purpose of the present invention.

(Embodiment of the invention) FIG. 3 shows the configuration of an embodiment of the invention. In the same figure, the same parts as in FIG. 1 are indicated by the same numbers, 11 is a shift register, 12 is a NOR circuit, 1
3 is an AND circuit. Moreover, FIG. 4 shows signals of each part in the circuit of FIG. 3, where (1) is the input signal of the solitary wave detection circuit 2, (2) is the output signal of the solitary wave detection circuit 2, and (3) is the input signal of the solitary wave detection circuit 2.
(4) is the inhibit signal output of the NOR circuit 12, and (4) is the timing clock, which are also indicated by the same numbers in FIG.

If the echo is large, the solitary wave detection circuit 2 generates an output pulse for both the training pulse and the echo (
Figure 4 (1) (2)). For the first output pulse, the AND circuit 11!813 is open, and the output pulse is given to the flower vase 1 as a timing clock (Fig.
)). This pulse is also given to the shift register 11,
It propagates through the shift register 1 for a certain period of time. During this period, one of the outputs of the shift register 11 is “1”.
, all other outputs are “0”, and NOR circuit 1
The output of 2 becomes "0" during this period (Figure 4 (3))
. Therefore, the AND circuit 13 is closed and the echo-based solitary wave detection circuit output is not output as a timing clock.

In the embodiment shown in FIG. 3, a shift register is used as a means for determining a fixed period from the generation of a timing clock based on a training pulse, but it is limited to this, and it is not possible to use an analog circuit such as a CR circuit. Needless to say, a typical time constant circuit may also be used.

FIG. 5 shows another embodiment of the invention.

In this figure, the same parts as in FIG. 3 are indicated by the same numbers, 14 is a flip-flop, and 15 is an exclusive OR circuit. Further, FIG. 6 shows the signals of each part in the circuit of FIG. Q output, (4) is the inhibition signal output of the exclusive OR circuit 15, and (5) is the timing clock, which are also indicated by the same numbers in FIG.

When the echo is large, the solitary wave detection circuit 2 generates output pulses for both the training pulse and the echo (Fig. 6 (1) and (2)), but the AND circuit 13 generates output pulses for the first output pulse. the output pulse is given to equalization layer 1 as a timing clock (Fig. 6 (5)
). The flip-flop 14 receives an input signal at its data input terminal, and outputs the output from the AND circuit 13 at its clock terminal G.
Therefore, the Q output becomes "1" by the first output pulse of the solitary wave detection circuit 2 (FIG. 6 (3)). The exclusive OR circuit 15 detects a mismatch between the input signal and the Q output of the flip-flop 14 and generates an inhibition signal output. The inhibition signal output is "0" for a part of the pulse corresponding to the training pulse and the pulse corresponding to the echo in the output of the solitary wave detection circuit 2 (Fig. 6 (4)), and therefore The solitary wave detection circuit output based on this is not output as a timing clock.

The circuit shown in FIG. 5 operates to block the second and subsequent solitary wave detection circuit output pulses when pulses of the same polarity are successively applied from the equalization layer 1.

For example, the commonly used AMI signal is "1" and then "
0” or “-1” and so on, 1” or “
-1'' is guaranteed not to occur consecutively, so the circuit in Figure 5 correctly generates the timing clock for coefficient correction in response to the AMI signal input, but since the echoes have the same polarity, It is possible to operate so as not to generate a timing clock for echoes.

(Effects of the Invention) As explained above, according to the present invention, when detecting the pull-in timing of the bridged tap equalization layer, it is possible to correctly generate a timing clock for coefficient correction even when the echo is large. Therefore, it is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional pull-in timing detection circuit in a bridged tap equalizer, FIG. 2 is a time chart showing various signals in the circuit of FIG. 1, and FIG. 3 is an embodiment of the present invention. A block diagram showing an example configuration,
FIG. 4 is a time chart showing the signals of each part in FIG. 3, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG.
The figure is a time chart showing signals of various parts in FIG. - Equalizer, 2 - Solitary wave detection circuit, 3 - Adder (Σ
), 4-1.4-2.4-3-delay circuit (D), 5-
Tap coefficient correction circuit, 6-1゜6-2- multiplier, 11-
Shift register, 12-NOR circuit, 13-AND circuit,
14-Flip-flop, 15-- Exclusive OR circuit Patent applicant Fuji 1 Co., Ltd. Company agent Patent attorney Gobe Tamamushi (3 others) Figure 1 Figure 2 (a) (2) 3 Figure 4 2T (4)

Claims (3)

[Claims] (1) In a bridged tap equalizer that includes a solitary wave detection circuit that detects the arrival of a solitary wave and generates a pulse, and uses the pulse to correct a tap coefficient, a gate that turns on and off the output of the solitary wave generation circuit is used. , when another pulse is generated in succession to the detection pulse of a solitary wave in the solitary wave generation circuit, the pull-in timing detection circuit of the second and subsequent lump equalizers. (2) Retraction of the bridged tap equalizer according to claim 1, wherein the gate control means turns off the gate for a certain period of time after detecting a solitary wave at the output of the solitary wave detection circuit. Timing detection circuit. (3) The bridged tap according to claim 1, wherein the gate control means detects the arrival of a pulse of the same polarity following a solitary wave in a solitary wave detection circuit and turns off the gate. Equalizer pull-in timing detection circuit.