JPH0223097B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform distortion equalization circuit, and more particularly to an equalization circuit that equalizes signal waveform distortion that occurs when performing digital transmission of bipolar signals using telephone subscriber lines.

Telephone subscriber lines often have several branch lines (hereinafter referred to as bridged taps) as shown in FIG. When pulse transmission is performed using such a transmission path, a portion of the pulse signal is reflected by the bridged tap, so it is received later than the signal that reaches the receiving end directly, causing echoes as shown in Figure 2. This is the received signal. Conventionally, as an equalization circuit for such a signal, a decision feedback type equalizer with a small number of taps (2 in FIG. 3) as shown in FIG. 3 has been used. The decision feedback type equalizer in FIG. 3 includes a signal addition circuit 1, a positive pulse level determination circuit 2, a negative pulse level determination circuit 3, sampling circuits 4 and 5, an error detection circuit 6, and a It is composed of circuits 7, 8, 11 and 12, integrating circuits 9 and 10 for modifying and holding tap coefficients, and a shift register 13 for holding judgment results. terminal 3
The bipolar signal input from 0 has intersymbol interference canceled by an adder circuit 1, and is input to level determination circuits 2 and 3, where positive and negative signal levels are discriminated. The identification results of the level determination circuits 2 and 3 are input to sampling circuits 4 and 5, and it is determined whether positive pulses, negative pulses, or no input pulses of data are received at predetermined phases. The determination result is input to the shift register 13. The output signal of the adder circuit is also input to the error signal detection circuit 6, compared with a reference level corresponding to the determination result, and output as an error signal. The output error signal of the detection circuit 6 is multiplied by the determination result, and further integrated by the integration circuits 9 and 10 to correct the tap coefficient. Further, the determination result held in the shift register 13 is multiplied by a tap coefficient and added to the input signal in the adding circuit 1, thereby canceling intersymbol interference of the input signal.

In the above circuit, in order to correct tap coefficients and cancel intersymbol interference, it is necessary that judgment results 4 and 5 are correct, but if a signal like the one shown in Figure 2 is input. , in the early stage of the equalizer convergence process, if the echo b at the rear of the main pulse a is higher than the threshold level of the judgment circuit, an erroneous judgment will be made at the echo position, so the tap coefficient must be corrected. The drawback is that it cannot be done correctly. Furthermore, since it is erroneously determined that a pulse is present at the echo position, an intersymbol interference cancel signal is erroneously output, and the cancel signal itself is again erroneously determined to be an input pulse.

An object of the present invention is to eliminate the above-mentioned drawbacks, and when the judgment result of the judgment circuit is that a positive polarity pulse has been received, a negative threshold level is used for subsequent judgment, and when the judgment result is that a negative polarity pulse has been received, The object of the present invention is to provide a decision feedback equalizer that stably converges even for input signals with large amplitude echoes by making decisions using positive threshold pulses.

Next, the present invention will be explained in detail using the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention. The equalization circuit of the present invention includes an addition circuit 14, a positive pulse discrimination circuit 15, a negative pulse discrimination circuit 16, sampling circuits 17 and 18 that sample determination results of positive and negative pulse levels, and a negative pulse discrimination circuit 15. Pulse level judgment error signal detection circuit 19 and multiplication circuits 20, 21, 24 and 2
5, integration circuits 22 and 23, shift register 26, and reset flip-flop 27.
and AND gates 28 and 29. Intersymbol interference of the bipolar input signal applied to the terminal 30 is canceled by the addition circuit 14, and the presence or absence of pulses and polarity are determined by positive/negative level discrimination circuits 15 and 16. The outputs of these identification circuits 15 and 16 are output from sampling circuits 17 and 18.
The received signal is sampled and the received signal judgment result is obtained. If the determination result is that a positive pulse has been received, the output of the sampling circuit 17 will be at a high level, the output of the sampling circuit 18 will be at a low level, and the reset flip-flop 27 will be in the set state.
As a result, the AND gate 28 between the positive polarity level identification circuit 15 and the sampling circuit 17 is closed.
Negative polarity level identification circuit 16 and sampling circuit 1
The AND gate 29 between 8 and 8 is in an open state. The output of the positive pulse discrimination circuit 15 is always at a low level regardless of the input signal, and only the negative pulse determination result is output. In other words, negative pulse reception is determined for negative signals with amplitudes larger than the negative threshold level, but for negative signals with amplitudes smaller than the threshold level and signals of positive polarity, Determine whether there is a received pulse. When a negative polarity pulse is received in this state, the output of the sampling circuit 17 is at a low level, and the sampling circuit 1
The output of 8 goes high, the reset flip-flop 27 goes into the reset state, the AND gate 29 closes, and the AND gate 28 opens, resulting in a signal with an amplitude greater than the positive threshold level. In this case, it is determined whether a positive pulse has been received. Since positive polarity pulses and negative polarity pulses are input alternately in a bipolar signal, this circuit can make a determination without error for an input signal with little distortion. Furthermore, even for an input signal with a large amplitude echo of positive polarity as shown in Fig. 2, the presence or absence of a pulse is determined using a threshold of opposite polarity at the time when the main pulse is determined. At the echo position, it is determined that there is no pulse, and the echo is not detected as a received pulse, and unlike the conventional method, a correct determination is made even at the echo position. Furthermore, input signals that do not conform to the bipolar code code conversion rules are ignored, so even if a judgment error occurs and an intersymbol interference cancellation signal is erroneously output, resulting in a temporary increase in distortion, the bipolar code is not followed. Even if the distortion that occurs at the misaligned position exceeds the threshold level, it will not lead to a judgment error, which alleviates the problem of spread of errors.

As described above, according to the present invention, it is possible for a decision feedback equalizer to converge even for an input signal with large distortion that exceeds a threshold level of the same polarity as the main pulse, and , the spread of errors, which is a problem unique to decision feedback equalizers, can also be alleviated.

[Brief explanation of drawings]

Figure 1 is a diagram showing a subscriber line with a bridged tap, Figure 2 is a waveform diagram showing received pulses when pulse transmission is performed using a subscriber line with a bridged tap, and Figure 3 is a conventional decision feedback type etc. The circuit diagram of the converter and FIG. 4 are circuit diagrams showing one embodiment of the present invention. In the figure, 14... Addition circuit, 15... Positive polarity pulse identification circuit, 16... Negative polarity pulse identification circuit, 17... Positive polarity pulse level judgment result sampling circuit, 18... Negative polarity pulse level judgment result sampling circuit. , 19...Error signal detection circuit, 20, 21...Multiplication circuit, 22, 23...Integrator circuit, 24, 25...Multiplication circuit, 26...Shift register, 27...Set reset flip-flop, 28 , 29...and gate.

Claims (1)

[Scope of Claims] 1. A first identification circuit that identifies the level of a positive pulse of a bipolar signal and outputs a positive identification result, and a first identification circuit that identifies a negative pulse of the bipolar pulse signal and outputs a negative identification result. a first gate circuit that blocks a positive pulse identification result at the next time by a first control signal when the positive identification result indicates that a positive polarity pulse is present; a second gate circuit that blocks a negative pulse identification result at the next time when indicating the presence of a pulse; and a second gate circuit that is set by the output of the first gate circuit and reset by the output of the second gate circuit. The first
and a flip-flop that generates a second control signal.