JPS6343012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides a method for effectively canceling echo signals (sidetone) in the hybrid circuit of a telephone connected to a line by performing 4-wire to 2-wire conversion via a hybrid circuit. This invention relates to an echo canceller device that can perform

Technical Background of the Invention Generally, a telephone set and a line are connected via a hybrid circuit through 4-wire to 2-wire conversion. Ideally, the hybrid circuit described above can achieve impedance matching between the telephone set and the line, but in reality, impedance mismatching often occurs due to line connection conditions or other reasons. Due to this, the transmitted signal goes around to the receiving side via the hybrid circuit, resulting in an echo signal (sidetone). This echo signal not only deteriorates the quality of the speech signal, but also causes howling in the case of loudspeaker telephones in conjunction with the echo coupling of the handset.

Conventionally, the echo path characteristics in a hybrid circuit are estimated, a pseudo echo signal is generated according to the estimated echo path characteristics, and this is subtracted from the receiving end output signal of the hybrid circuit. is being canceled. An echo canceller device executes this process, and is basically configured as shown in FIG. That is, the transmitted signal Xi is input to the echo canceller calculation unit 2 via the A/D converter 1, and the echo signal Yi of the transmitted signal Xi, which has been routed through the hybrid circuit 3, is input to the A/D converter 4. The signal is input to the echo canceller calculation section 2 via the echo canceller calculation section 2. In the echo canceller calculation unit 2, these signals
The echo path characteristic Hi of the hybrid circuit 3 is estimated in the form of an impulse response from Xi and Yi, and a pseudo echo signal Yi is generated according to the estimated echo path characteristic H. This pseudo echo signal Yi is converted into the echo signal
By subtracting the residual signal Ei from Yi and outputting this residual signal Ei via the D/A converter 5, the above-mentioned echo signal
It becomes possible to cancel Yi.

However, if the cancellation process of the echo signal Yi is to be performed entirely digitally within the echo canceller calculation section 2, the conversion speed must be high in order to maintain the quality of the received signal and keep the quantization noise low. Furthermore, a highly accurate A/D converter 4 is required. However, since it is extremely difficult to construct an A/D converter 4 that satisfies these requirements, it has conventionally been common practice to perform subtraction processing of the pseudo echo signal Yi using an analog system as shown in FIG. is being carried out. That is, the pseudo echo signal Yi obtained by the echo canceller calculation unit main body 2a is applied to the subtracter 7 via the D/A converter 6, and the echo signal Yi is canceled by the subtracter 7. I have to. Then, the residual signal which is the output of the subtracter 7 is given to the echo canceller calculation unit main body 2a via the A/D converter 8, and is used for estimating and correcting the echo path characteristics. . In addition, when configuring such a system, the timing is actually adjusted by delay-controlling the signal using sample-and-hold (SH) circuits 9a and 9b, as shown in FIG. In addition, measures are taken to remove sampling noise through a low-pass filter (LPF) 10 for the residual output.

Problems with the Background Art However, in the case of the device configured as shown in FIGS. 2 and 3, it is very difficult to adjust the operation timing, as shown in FIGS. 4a to l. There are certain problems. In particular, when the tap length for estimating the echo path characteristics in the echo canceller calculation unit body 2a is large, it is difficult to set the operation timing appropriately.

Briefly explaining the operation timing shown in FIG. 4 a to l, transmission data Xi is A/D converted as shown in FIG. 4 b for the sample period shown in FIG. will be held.
Based on this held data and the estimated symphonic path characteristics, a pseudo echo signal is generated as shown in FIG. 4d.
Y^i is generated. And this pseudo echo signal Y^i
is D/A converted and applied to the subtracter 7 at the timing shown in FIG. 4e. This pseudo echo signal Yi _(A)
A subtraction process is performed between this and the held echo signal Y^i at the timing shown in FIG. 4f, and this residual signal Ei is obtained as shown in FIG. 4g. This residual signal Ei is A/D converted at the timing shown in FIG. 4h, held as shown in FIG. Then, according to this held residual signal Ei _(D), the echo path characteristic is corrected as shown in FIG. 4j, and the echo path estimation characteristic Hi+1 for the next sample period is
will be required. Incidentally, the sampling timing of the echo signal Yi is as shown in FIG. 4k, and the sampling timing of the residual signal Ei is as shown in FIG. 4l.

As is clear from the operation timings shown in FIG. It is necessary to perform each of the steps once, and if sufficient time is secured for this, it becomes extremely difficult to secure the arithmetic processing time necessary for convolution integration and correction of tap coefficients. Therefore, if the number of taps is increased to estimate the echo path characteristics with high accuracy, thereby increasing the effect of canceling the echo signal, it will be extremely difficult to realize the apparatus. In particular, A/D conversion,
There is a need to increase the processing speed of D/A conversion, convolution and integration, etc. higher than the current speed, and there are problems such as the need for many high-speed operating elements.

Purpose of the Invention The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to be able to secure sufficiently stable data acquisition timing necessary for correcting tap coefficients, and to improve the echo path. It is an object of the present invention to provide a simple and highly practical echo canceller device that can improve the echo signal cancellation effect by increasing the tap length of characteristic estimation to generate a highly accurate pseudo echo signal.

Summary of the Invention The present invention converts a pseudo echo signal given as digital data generated according to estimated echo path characteristics and a receiving end output signal of a hybrid circuit into an A/D converter.
A residual signal with the converted received data is obtained, and tap coefficients at multiple points indicating echo path characteristics are corrected using this residual signal, and the pseudo echo signal is obtained by D/A conversion. The analog pseudo-echo signal is subtracted from the receiving end output signal to obtain a residual received signal. That is, the residual signal used for modifying the tap coefficient is digitally obtained separately from the system for canceling the echo signal in the received signal. In particular, the pseudo echo signal is generated in the first half of one sample period, and the tap coefficient used for generating the pseudo echo signal is modified in the second half of the one sample period in which the pseudo echo signal is generated. This is characterized in that it is used to generate a pseudo echo signal in the next sampling period.

Effects of the Invention Therefore, according to the device of the present invention, it is possible to independently determine the timing of the echo signal cancellation process and the acquisition of data necessary for modifying the tap coefficient. After acquiring the necessary data with sufficient margin, it becomes possible to carry out correction processing within one sample period with sufficient margin. Moreover, even if the tap length is made longer, problems like the conventional ones do not occur, and as a result, it is possible to estimate the echo path characteristics with high accuracy and to generate a pseudo echo signal. In addition, since the operation timing can be determined with a certain margin, it is possible to simplify the device configuration, which has great practical effects.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 5 is a diagram showing a schematic configuration of the embodiment device, and FIG. 6 is a diagram showing a specific example of the configuration. As shown in FIG. 5, this device basically sends the transmission signal and the receiving end output signal of the hybrid circuit 3 to the echo canceller calculation unit main body 2a via A/D converters 1 and 11, respectively. The echo canceller calculation unit body 2a digitally estimates the echo path characteristics of the hybrid circuit 3 according to these input data, and generates a pseudo echo signal according to the estimated echo path characteristics given in the form of an impulse response. is generated, this pseudo echo signal is D/A converted by the D/A converter 6, and the subtracter 7
The purpose is to cancel the echo signal by subtracting it from the receiving end output signal from the hybrid circuit 3 which is input to the receiver.

The details of this apparatus configured in this manner will be explained with reference to FIG. 6.

Specifically, the transmission signal sampled and inputted by the A/D converter 1 is passed through a low pass filter (LPF).
After the signal is band-limited via 12, that is, unnecessary signal components higher than the highest frequency component c of the transmitted signal are removed, it is sampled at a sample/hold circuit (SH) 13 at a sampling period of, for example, 1/2c. . This sampled transmission signal is sequentially A/D converted by the A/D converter 1 and sequentially stored in the n-stage registers 14. Therefore, at a certain timing (j-1), the sampled transmission data X _j-1 , X _j-2 to X _jo of n sampling points are stored in the register 14, respectively. On the other hand, in the tap coefficient register 15, the estimated echo path characteristics of the hybrid circuit 3 are aggregated into n taps in the form of an impulse response, and the tap coefficients h ₁ , h ₂ to _ho
It is stored as . These tap coefficients h ₁ , h ₂ to _ho and the transmission data X _j-1 , X _j-2 to X _jo stored in the register 14 are then transmitted to multipliers 16 ₁ and
After being guided by 6 ₂ and 16 _o and multiplied by each other,
An adder 17 calculates the sum. That is, multipliers 16 ₁ , 16 ₂ to 16 _o and adder 1
In step 7, the transmission data X _j-1 , X _j-2 ~ _{X jo} and the tap coefficients h ₁ , h ₂ ~ _ho are convolved, and the convolution result is obtained as the pseudo echo signal Y. It is being

The generation of the pseudo echo signal Y by this convolution is performed in the first half of one sample period.

On the other hand, the receiving end output signal of hybrid circuit 3 is
After components having frequencies higher than c are removed via the LPF 18, the signal is sampled and held at the SH19.
This sampled and held signal is digitally converted and extracted via the A/D converter 11, and the timing is adjusted via the shift register (SR) 20 and sent to the subtracter 21 at the timing of the latter half of one sample period. Supplied. The receiving end output signal (digital signal) input in this subtracter 21
A pseudo echo signal Y given as a digital signal previously determined by convolution is subtracted from . Then, the residual signal obtained by this subtracter 21 is multiplied by a predetermined coefficient α via a coefficient unit 22, and then multipliers 23 ₁ and 23 ₂
~23 _o and are multiplied by the transmission data X _j-1 , X _j-2 , and X _jo stored in the register 14, respectively. As a result, correction values of the tap coefficients h ₁ , h ₂ to _ho based on the residual signal are obtained, and the tap coefficient register 15 is stored as a new tap coefficient.
and is used to generate a pseudo-reverberation signal in the next sample period. Thereafter, such generation of the pseudo echo signal and modification of the tap coefficients based on the residual signal are repeated for each sample period.

On the other hand, the pseudo echo signal Y obtained for each sample period as described above is converted into an analog signal via the D/A converter 6 and is provided to the subtracter 7. This subtracter 7 receives the receiving end output signal, which was previously sampled and held in SH19.
The signal is sampled and held again, the timing is adjusted, and the signal is supplied. Then, the D/A converted pseudo echo signal Y is subtracted from the timing-adjusted receiving end output signal by a subtracter 7. The residual received signal obtained by the subtracter 7 is sampled and held by the SH 25, and then passed through the LPF 26 to remove sampling noise and the like associated with the digital generation of the pseudo echo signal. Later, it will be output.

Note that the correction of the tap coefficient is as follows: When the echo signal at timing i is Yi, the pseudo echo signal is Yi, and the tap coefficient is Hi, Ei=Yi−Y^i Y^i=ΣHi・Xi Hi+1= It is found as Hi+α・Ei・Xi. It goes without saying that estimation of the echo path characteristics, including modification of the tap coefficients, can be performed using various algorithms such as the steepest descent method and the learning identification method.

As described above, the operation timing of the present apparatus configured as shown in FIG. 6 is shown, for example, as shown in FIGS. 7a to 7p. That is, the sampling period of the device is as shown in Fig. 7a.
, the A/D converter 1 is started as shown in b of the same figure, A/D conversion processing is performed at the timing shown in c of the same figure, and the digital transmission data obtained thereby is transmitted. The data is sampled and set in the register 14 as shown in FIG. Therefore, the data stored in the first area of the register 14 is delayed by one cycle from the sampling time, as shown in FIG. 7e.

On the other hand, as shown in Fig. 7f, the convolution integral processing uses the transmission data X _i-1 of one sample period before, and in the first half of the sample period, the pseudo echo signal Y^i
generate. Then, using this pseudo echo signal Y^i, the tap coefficient is corrected in the latter half of the sampling period as shown in Figure 7g, and the above pseudo echo signal Y^i is as shown in Figure 7h. It is held like this. And this held pseudo echo signal
Y^i is D/A converted at the timing shown in FIG. 7i and is supplied to the subtracter 7.

At this time, the receiving end output signal of the hybrid circuit 3 is sampled and held at SH19 as shown in FIG. 7j. Therefore, the tap coefficient correction calculation shown in FIG. 7g is executed within one sample period without causing any particular timing deviation. Also, the above sampled and held signal is
2 at the timing shown in Figure 7 k and l at SH24.
Sampling is performed in stages, and the sampling outputs are as shown in Figures m and n. Since the signal delayed by these two stages of sampling and holding is given to the subtracter 7, the timing of the pseudo echo signal in the subtracter 7 and the receiving end output signal is matched, and thereby The echo signal is now canceled at the correct timing. The residual received signal thus obtained is sampled at the timing shown in FIG. 7o, and is output as shown in FIG. 7p.

As is clear from the operation timings shown in FIG. 7 a to p, according to this device, the system for correcting the tap coefficient and the system for canceling the echo signal by the generated pseudo-echo signal are independent. Therefore, there is no need to perform D/A conversion and A/D conversion processing at high speed within one sample period as in the conventional case, and the processing can be performed with sufficient time. That is, since the D/A conversion process of the pseudo echo signal and the correction process of the tap coefficient can be performed in parallel, sufficient time margin can be created within one sample period. Therefore, it is possible to increase the number of bits of information handled at one timing and the tap length of the tap coefficient by that much, making it possible to perform highly accurate processing. Furthermore, D/A conversion and A/
Since more time is available for the D conversion process, even if the bit length of temporary data is long, it can be handled satisfactorily. Therefore, it is possible to stably perform high-precision echo signal cancellation processing, and the above-mentioned time margin eliminates the need to use high-speed arithmetic elements, making it possible to simplify the device configuration, etc. Above all, it has a tremendous effect.

Note that the present invention is not limited only to the above embodiments. For example, it is possible to estimate the echo path characteristics using a training signal, but it is of course also possible to estimate the echo path characteristics adaptively using a telephone signal during a call. Further, the tap length of the estimated echo path characteristic obtained in the form of an impulse response may be determined according to the specifications of the apparatus. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

1 and 2 are basic configuration diagrams of the conventional device, FIG. 3 is a diagram showing the D/A conversion A/D conversion section with timing adjustment in the conventional device, and FIG. A diagram showing the operation timing of the conventional device, FIG. 5 is a basic configuration diagram of the device of the present invention,
FIG. 6 is a schematic configuration diagram of a device according to an embodiment of the present invention, and FIGS. 7a to 7p are diagrams showing operation timings of the device according to the embodiment. DESCRIPTION OF SYMBOLS 1...A/D converter, 2...Echo canceller calculation part, 2a...Echo canceller calculation part main body, 3...Hybrid circuit, 6...D/A converter,
7...Subtractor, 11...A/D converter, 12, 18,
26...LPF, 13, 19, 24, 25...SH, 1
4...Register, 15...Tap coefficient register, 16
₁ , 16 ₂ ~ 16 _o ... Multiplier, 17... Adder, 20
...Shift register, 21...Subtractor, 22...Coefficient unit, ₂₃₁ , ₂₃₂ to _23o ...Multiplier.

Claims (1)

[Claims] 1. A means for estimating the echo path characteristics of a hybrid circuit in the form of an impulse response, a coefficient register for storing tap coefficients at a plurality of points indicating the estimated echo path characteristics, and a means for estimating the echo path characteristics of a hybrid circuit in the form of an impulse response; a register for storing transmission data of multiple sample points obtained by D-conversion;
an arithmetic circuit that generates a digital pseudo-echo signal by convolving and integrating the transmission data of multiple sample points stored in this register and tap coefficients of multiple points stored in the coefficient register; and a receiving end output of the hybrid circuit. a subtracter for obtaining a residual received signal by subtracting a signal obtained by D/A converting the digital pseudo-echo signal from the signal; comprising a digital subtracter for subtracting the pseudo echo signal to obtain a cancellation residual signal, and a correction circuit for correcting tap coefficients at a plurality of points stored in the coefficient register based on the cancellation residual signal, The arithmetic circuit performs a convolution operation in the first half of one sample period to generate a digital pseudo-echo signal, and the correction circuit updates the tap coefficients of multiple points stored in the coefficient register in the second half of one sample period. an echo canceller device, characterized in that it provides a tap coefficient for the next sample period. 2 A/D the receiving end output signal of the hybrid circuit.
The echo canceller device according to claim 1, wherein the converted signal is delayed for the first half of one sample period in which the digital pseudo-echo signal is generated, and then is applied to the digital subtracter. .