JPH02143536A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To assure the yield of gate electrode pattern in the gate length not exceeding 0.5mum by a method wherein a negative type photoresist layer is formed by exposure and development using a mask in fine lineal width and then an evaporated Al layer is etched away using a pattern of the formed negative type photoresist layer as a mask and then a positive type photoresist is exposed and developed using the evaporated Al layer as a mask. CONSTITUTION:An evaporated Al layer 6 is formed on the surface of a positive type photoresist layer in the unexposed state and then the Al layer 6 is spin- coated with a negative type photoresist to be prebaked in an N2 atmosphere circulating oven to form a negative type photoresist layer 7. The negative type photoresist layer 7 is exposed and developed; the Al layer 6 is etched away by 85% phosphoric acid using the pattern of the formed negative type photoresist layer 7 as a mask; furthermore the positive type photoresist layer 5 is exposed and developed using the pattern of the formed Al layer 6 as a mask. Through these procedures, an opening width in 0.35mum can be assured using a mask in lineal width of 0.5mum by selecting the optimum exposure requirements in case of patterning the negative type photoresist layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode having a short gate length and low resistance by a lift-off method.

[Conventional technology]

The following will explain the gate electrode of a GaAs FET as an example.

FIG. 2 shows a method of forming a gate electrode of a conventional GaAs FET.

A photoresist layer 2 is formed on a semiconductor substrate 1 in which an N active layer is epitaxially grown on the surface of a semi-insulating GaAs single crystal substrate, the photoresist layer 2 is patterned using a mask, and the exposed substrate layer 1 is recess-etched. Second
FIG. 2(a)), a metal layer 3 is deposited [FIG. 2(b)],
Lift on.

[Problem to be solved by the invention]

The width of the gate electrode (hereinafter referred to as gate length) of a GaAs FET is generally required to be as small as about 0.5 μm in order to improve the characteristics in the microwave region.

This gate length is determined by the line width of the pattern of the photoresist layer 2, but as long as the current close exposure of ultraviolet light or deep ultraviolet light is used, it is almost impossible to form a photoresist line width of 0.5 μm using the conventional lift-off method. This is a limit, and achieving it requires extreme caution.

Further, forming a photoresist pattern of 0.5 μm or less requires an expensive device such as an electron beam exposure device.

On the other hand, when the gate length is shortened, the gate resistance increases if the deposited thickness of the gate metal is constant.

Reducing this gate resistance is also an important parameter for improving FET microwave characteristics.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to use a gate electrode pattern with a gate length of 0.5 μm or less.
It is an object of the present invention to provide a lift-off method that can be realized with high yield by contact exposure with ultraviolet light or deep ultraviolet light.

[Means to solve the problem]

In order to achieve the above object, the present invention forms a positive photoresist layer, a vapor-deposited Al layer, and a negative photoresist layer from below on the surface of a predetermined semiconductor substrate, and forms the upper negative photoresist layer with a line width of 0.5 μm. The pattern of the negative photoresist layer is exposed to light and developed using a mask.
After etching the formed Al layer, the bottom-layer bot-type photoresist is exposed and developed using the formed Al layer as a mask, and a vapor-deposited metal layer is formed on the exposed semiconductor substrate layer by a lift-off method. The heat treatment causes only the bottom photoresist to flow and contact the vapor deposited metal layer, narrowing the opening width of the pattern of the bottom photoresist layer, etching and removing the vapor deposited metal layer, and recess etching the exposed semiconductor substrate layer. Then, a gate electrode is realized in the recess-etched part by a lift-off method.

〔Example〕

FIG. 1 shows an embodiment of the invention.

Semiconductor substrate 1 in which an N active layer is epitaxially grown on the surface of a semi-insulating GaAs single crystal substrate with a specific resistance of 1060 m or more
On the other hand, after separating the N active layer into each element by mesa etching, and completing the formation of the source/drain electrodes 4 on the surface of the N active layer (see Fig. 1(a)), a bottom-type photoresist was applied to the surface. MP-2400 (Shipley) was spin-coated at 200 rpm and heated to 95°C in an air circulation oven.

A prebaking process is performed for 30 minutes to form a positive photoresist layer 5.

Al is vapor-deposited on the surface of this bottom-type photoresist layer 5 in an unexposed state to form a vapor-deposited Al layer 6 with a thickness of about 2000×, and then a negative-type photoresist layer 6 is formed on this Al layer 6.
0DUR・120 (Tokyo Ohka needle) at rotation speed 400 O
Rotate coating at rpm, open with N2 atmosphere circulation, 85
C. for 30 minutes to form a negative photoresist layer 7.

Next, using a mask with a line width of 0.5 μm, the negative photoresist layer is exposed and developed, and using the pattern of the formed negative photoresist layer 7 as a mask, the Al layer 6 is coated with 85% cynic acid (
The formed A
Using the turn of the l layer 6 as a mask, form a hollow photoresist layer 5.
is exposed and developed [Fig. 1(b)].

Place it on the semiconductor substrate l exposed by the above operation.
A metal layer 8 is deposited by a method [FIG. 1(C)].

Since this metal layer 8 will be removed later, Al was selected as a material that does not allow the etching solution used to etch the GaAs substrate.

Note that the negative photoresist layer 7 (ODUR・12o
) When patterning, by selecting the optimal exposure conditions,
An opening width of 0.35 μm could be obtained using a mask with a line width of 0.5 μm.

Next, by heat treatment at a temperature in the range of 130 DEG to 150 DEG C., only the bottom-shaped photoresist layer 5 is made to flow and come into contact with the vapor-deposited metal layer 8 [FIG. 1(d)]. The photoresist layer becomes fluid as the temperature increases. MP -240 below 130℃
The fluidity of the positive photoresist layer 5 of 0 is insufficient, and 15
When the temperature exceeds 0° C., the upper negative photoresist layer 7 of 0DUR-120 also becomes fluid.

After the above heat treatment, the vapor deposited metal layer 8 is removed by etching with HCl, the exposed semiconductor substrate layer 1 is recess-etched, and a gate electrode 3 is formed on the recess-etched semiconductor substrate layer l by a lift-off method [Fig. e)].

Through the above steps, a gate electrode with a gate length of 0.35 μm could be obtained with a high yield.

Even when the vapor-deposited metal layer 8 is formed in the above process, the bottom-type photoresist layer 5 is made to flow, and the means for narrowing the opening width of the photoresist layer is omitted, the positive-type photoresist layer of MP-2400 is formed using a mask with a line width of 015 μm. Compared to the gate length obtained by exposure and development, we were able to uniformly form a narrower pattern.

In the above process, even if the gate electrode 3 is made somewhat thicker, it is reliably separated from the vapor-deposited metal layer 3 deposited on the photoresist layer 7, so that the gate resistance can be sufficiently reduced.

[Effect of idea]

As explained above, according to the present invention, a gate electrode with a gate length of 0.5 μm or less and low resistance can be formed with high yield without requiring an expensive exposure device and without increasing costs. For example, this has the effect of making it easier to improve the microwave characteristics of GaAs FETs and the like.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a method of forming an r-4 electrode of a conventional GaAs FET. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate layer, 3... Kate electrode, 4...
・Source/drain electrode, 5... Positive type photoresist layer, 6... Vapor deposited Al layer, 7... Negative photoresist layer, 8... Vapor deposited metal layer, Note that the same reference numerals in the drawings are the same or correspond to each other. Show parts. Patent applicant New Japan Radio Co., Ltd. Figure 1 Figure 1 Figure 2

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which a gate electrode with a short gate length and low resistance is formed on a semiconductor substrate on which an active layer is epitaxially grown, the active layer is epitaxially grown on the surface and is grown on the surface of a semiconductor substrate separated into individual elements from below. A positive photoresist layer, a vapor deposited Al layer, and a negative photoresist layer are formed, and the negative photoresist layer is exposed and developed using a mask with a fine line width. Using the pattern of the formed negative photoresist layer as a mask, the vapor deposited Al The layer is etched, the positive photoresist is exposed and developed using the formed Al layer pattern as a mask, a vapor-deposited metal layer is formed on the exposed semiconductor substrate by a lift-off method, and the above-described metal layer is formed by heat treatment within a certain temperature range. Only the positive photoresist is flowed and brought into contact with the vapor deposited metal layer, the vapor deposited metal layer is etched and removed, the exposed semiconductor substrate layer is recess-etched, and a gate electrode is formed on the recess-etched semiconductor substrate layer by a lift-off method. 1. A method of manufacturing a semiconductor device, comprising a step of forming a gate electrode.