JPH02141990A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To execute batch writing to an arbitrary memory cell block by partitioning a memory cell array into plural memory cell blocks, designating a memory cell block by a block selecting means, and executing the batch writing to the designated memory cell block. CONSTITUTION:When a signal to command flash clear is inputted to a seizure signal generating circuit 9, a window pulse W and a select pulse S are outputted from the circuit 9. When the pulse W is inputted to a timer circuit 8, a counter 6 and a decoder 5 are made into an operable state. The pulse S is generated correspondingly to the pulse W and counted by the counter 6. The count value is sent to the decoder 5. The decoder 5. The decoder 5 outputs a signal to designate a memory cell block 3 having the same number as the count value. Next, a flash clear enable signal FCE is outputted from the circuit 8 to all the flash clear control circuits 41-4n, and the circuit 4 corresponding to the block 3 designated by the decoder 5 flash-clears the block 5 to '0'. Thus, the batch writing to the memory cell block can be executed.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B1 Overview of the invention C9 Background art 9 Problems to be solved by the invention E1 Means for solving the problems F1 Effects G. Examples [Figures vJ1 to 3] a9 Circuit configuration [7JJ1 Fig. 1 b6 Circuit operation [Fig. 2 J C1 Another embodiment [Fig. 3] H9 Effects of the invention (A, Industrial application field) The present invention relates to a semiconductor memory, in particular, a memory cell array that includes a plurality of memory cell blocks. The present invention relates to a new semiconductor memory which is divided into two parts and can be written into only an arbitrary meso cell block at once.

(B. Summary of the Invention) In order to enable partial batch writing of a memory cell array in a semiconductor memory, the present invention divides the memory cell array into a plurality of memory cell blocks, and further provides block selection means. The block selection means can specify a memory cell block and perform batch writing.

(C. Background Art) It has already been introduced in Japanese Patent Application No. 62-290408 that random access memories generally have a flash clear function. This flash clear function is a function that can set all bits of data to 0 or 1 within, for example, several microseconds when a signal is applied from the outside.

The technical idea proposed in the above-mentioned patent application No. 62-290408 is that - In order to reduce the peak value of the current flowing during bulk writing, the memory cell array is divided into multiple memory cell blocks (memory cell groups), and each memory This is to perform batch writing to cell blocks at mutually different timings.

(D. Problem to be Solved by the Invention) By the way, in both conventional semiconductor memories and the semiconductor memory proposed in Japanese Patent Application No. 62-290408, the same data is written into the entire memory cell array of one semiconductor memory. I was only able to write in bulk.

However, there is an increasing demand for semiconductor memories to have a function that allows only specific portions to be written at once. This is because memory capacity continues to increase, and the commercialization of 1Mbit semiconductor memory has already been fully realized, the commercialization of 4Mbit semiconductor memory has almost been realized, and the commercialization of 16Mbit and 64Mbit semiconductor memory is on the rise. There is a possibility of commercialization, and one memory chip can now store one screen's worth of data. and,
An image processing apparatus that must have a variety of image processing functions is naturally required to have an image processing function that clears a portion of the screen as one function. Therefore, when a semiconductor memory that stores one screen is used as an image memory for storing image signals in the image processing device, the semiconductor memory is necessarily required to have a function to clear only a portion of the memory cell array. It is. And there is currently nothing that can meet that demand.

The present invention has been made in response to this demand, and an object of the present invention is to enable batch aging to be carried out only in an arbitrarily designated portion of a memory cell array.

(E. Means for Solving the Problems) In order to solve the above problems, the f-conductor memory of the present invention divides the memory cell array into a plurality of memory cell blocks, and further provides block selection means to A feature of the present invention is that a memory cell block can be designated by a selection means to perform batch writing.

(F. Effect) According to the semiconductor memory of the present invention, the memory cell array can be divided into a plurality of memory cell blocks, and the memory cell blocks can be designated by the block selection means to be aged all at once. Batch writing can be performed for .

(G. Embodiment) [FIGS. 1 to 3] Hereinafter, one semiconductor memory of the present invention will be explained in detail according to the illustrated embodiment.

Figure 1 and '! FIG. R2 is for explaining one embodiment of the semiconductor memory of the present invention, FIG. 1 is a circuit block diagram, and FIG. 2 is an operation timing chart.

(a, circuit configuration) [Fig. 1] In the drawing, l is a semiconductor memory, 2 is a memory cell array of the semiconductor memory 1, and the memory cell array 2 is divided into n memory cell blocks 31 to 3 II. . One flash clear control circuit 4.corresponds to each memory cell block 31-3n. ~4o
is provided. The flash clear control circuit 41~
4n is a flash clear enable signal FCE which will be described later.
When the memory cell block 3 receives a signal from a decoder, which will be described later, it writes 0, for example, into all memory cells in the memory cell block 3 corresponding to itself.

A decoder 5 decodes the output signal of the counter 6 and outputs a signal specifying the memory cell block 3. The output of the decoder 5 is input to the flash clear control circuit 4. The counter 6 counts the serial signal S input from the outside to the semiconductor memory 1 through the input pin Pinb, and sends a multi-bit digital signal indicating the count value to the decoder 5. A block selection circuit 7 is constituted by the J-decoder 5 and the counter 6.

A timer circuit 8 outputs a clear signal CLR and a flash clear enable signal FCE at appropriate timings to be described later, upon receiving a wind pulse W input from the outside to the semiconductor memory 1 through an input pin Pina, and outputs a clear signal CLR and a flash clear enable signal FCE to the decoder 5 and counter 6. Clear the flash clear control circuits 41 to 4o to enable flash clearing.

Reference numeral 9 denotes an activation signal generation circuit provided outside the semiconductor memory 1, which sends a wind pulse W and a select pulse S for specifying the memory cell block 3 to the semiconductor memory 1 upon receiving a signal instructing flash clear. do. The memory cell block 3 is designated by the number of select pulses S.

Note that the pin Pina for inputting the wind pulse W may be a pin that uses the chip enable signal CE as an input pin. That is, one pin
a to the input of the wind pulse W and the chip enable signal C
It may also be used as the input for E.

This is because the semiconductor memory is enabled when the chip enable signal CE is at a "low" level, and the pin Pina is essentially idle during the enabling period. Of course, just because Pina is just for fun doesn't mean it's 1.
If No. 3 is input and the high level state continues for a long time, the semiconductor memory l will become inoperable. However, the pulse width of the wind pulse W is very narrow, at most several hundred nanoseconds, so the wind pulse W will not be able to reach the enabled state. There is no risk of it being read as a signal to stop. Therefore, it is fully capable of 6 guns for dual use.

(b. Circuit operation) [FIG. 2] Next, the operation of flash clearing an arbitrary memory cell block 3 of the present semiconductor memory 1 will be described according to FIG.

First, when a signal commanding flash clear is input to the activation signal generation circuit 9, a wind pulse W and a select pulse S having the same number of pulses as the number of the memory cell block to be flash cleared are output from the activation signal generation circuit 9. be done. The wind pulse W is input to the timer circuit 8, and upon receiving the wind pulse W, the timer circuit 8 immediately changes the clear signal CLR from "low" to "high" and starts the counter 6.
and makes the decoder 5 operational. The select pulse S is generated by the starting signal generating circuit 9 as many times as necessary during the generation period of the wind pulse W, and this is counted by the counter 6. Then, a parallel signal indicating the count value is sent to the decoder 5.

Then, the decoder 5 enters a state in which it outputs a signal specifying the memory cell block 4 having the same number as the count value.

Then, when a certain period of time T has elapsed after the wind pulse W was generated, the wind pulse W falls. Accordingly, a flash clear enable signal FCE is output from the timer circuit 8 to all flash clear control circuits 4I to 4n, and the flash clear enable signal FCE is outputted from the timer circuit 8 to all flash clear control circuits 4I to 4n. ~4o becomes capable of flash clearing, and the flash clear control circuit 4 corresponding to one memory cell block 3 designated by the output of the decoder 5 clears that memory cell block 3.
Flash clear to "0". If the number of select pulses S generated during the wind pulse W generation period is 1, the flash clear control circuit 4. Memory cell block 3. Batch writing of "0" to the data will be executed. Then, when the time required to clear the flash has elapsed, the flash clear enable signal FCE disappears and the clear signal CLR
It also falls from "high" to "low". Due to the stiffness, the flash clear control circuits 41-4.degree. become unable to clear the flash, and the counter 6 and decoder 5 are cleared.

This completes one flash clear. In addition, in Fig. 2, ts is set time, t□
is the hold time. 1. is Select Pulse S!
The period is, for example, about 40 nsecC. The pulse width T of the wind pulse W is 1. +1□+nt,
becomes.

In this embodiment, the number of bits of the counter 6 is m, and the decoder 5 sends the m-bit signal to n memory cell blocks 3. It is designed to convert into a signal that specifies and selects one from ~3n, and there are 2 between m and n.
”=n holds true. Therefore, the number of memory cell blocks 3 that can be flash cleared within one flash clear operation cycle is only one.

Therefore, in this embodiment, when flash clearing the entire memory cell array 2, zero flash clear operations are required.

However, it is also possible to flash-clear a plurality of memory cell blocks 3 at the same time within one batch write operation cycle by setting the relationship 2''>n. That is, in the semiconductor memory 1 shown in FIG.
The signal to clear the flash is output only from the main line, but by increasing the number of bits m of counter 6,
> n (of course, the circuit configuration of the decoder 5 must also be appropriately complicated). A flash clearing signal is output from multiple of the n output lines of the decoder 5, and once This allows any plurality of memory cell blocks 3, 3, . . . to be flash cleared at the same time.

Incidentally, instead of writing "0" by flash clearing, "l" may be written.

(c, Another Embodiment) [FIG. 3] FIG. 3 shows another embodiment of the semiconductor memory of the present invention.

In this embodiment, an n-bit shift register 7a is used as a block selection means, and an n-bit serial signal is used as a select pulse signal S to select the shift register 7a.
is input, the stiffness is serial-parallel converted and applied to the flash clear control circuits 41 to 411, so that l or a plurality of memory cell blocks specified by the select pulse signal S can be flash cleared at the same time. still,
In this embodiment, the timer circuit 8 is the shift register 7a.
It has a built-in oscillation circuit that generates the clock pulse CLK that drives the oscillation circuit.

As described above, the semiconductor memory of the present invention can have various embodiments.

(H, Effect of invention) As described above, the semiconductor memory of the present invention is provided.

The memory cell array has a memory cell array divided into a plurality of memory cell blocks, and block selection means for selecting the memory cell blocks, and the block selection means can perform batch writing to any memory cell block. It is characterized by this.

Therefore, according to the semiconductor memory of the present invention, it is possible to divide the memory cell array into a plurality of memory cell blocks, specify the memory cell blocks by the block selection means, and perform batch writing, so that data can be written to any memory cell block. This allows batch writing to be performed.

[Brief explanation of the drawing]

1 and 2 are for explaining one embodiment of the semiconductor memory of the present invention. FIG. 1 is a circuit block diagram, FIG. 2 is an operation timing chart, and FIG. 3 is a diagram of the semiconductor memory of the present invention. FIG. 3 is a circuit block diagram showing another embodiment. Explanation of symbols l...Semiconductor memory, 15'...Memory cell array, ~39,...Memory cell block,...Decoder, 6...Counter,...Block selection means,...Shift register stage ). (Block selection hand

Claims (3)

[Claims] (1) It has a memory cell array divided into a plurality of memory cell blocks, and block selection means for selecting the memory cell block, and the block selection means can perform batch writing to any memory cell block. A semiconductor memory characterized by the following: (2) Claim (2) characterized in that the block selection means comprises a counter that counts the number of pulses input during the window pulse, and a decoder that selects the memory cell block corresponding to the output signal of the counter. 1) Semiconductor memory described (3) The semiconductor memory according to claim (1), wherein the block selection means comprises a shift register that receives a serial signal and outputs a parallel signal specifying a memory cell block.