JPH02141086A - Ternary synchronization delay detecting circuit - Google Patents

Abstract

PURPOSE:To automatically regulate a delay time lag by slicing the output signal of a differential amplifier, and detecting the mean value of the output signal. CONSTITUTION:A first synchronization separator circuit part 21 to separate a ternary synchronizing signal from a D/A-converted luminance (Y) signal, a second synchronization separator part 22 to separate the ternary synchronizing signal from either one of D/A-converted color difference signal PR or a PB signal, a mean value detecting part b, which differentially amplifies the separated synchronizing signal and detects the mean value of the signals after slicing by means of the parts 21 and 22, and a means 6, which delays the digital signal of the Y signal based on a detection value, are provided. Consequently, the two ternary synchronizing signals, which are synchronization-separated, are differentially amplified, the mean value of the sliced output signal is detected, and the delay time lag can be detected. Thus, the delay time of the digital signal of the Y signal inputted to the D/A amplifier 11 according to the magnitude of the mean value output is changed, and the delay time lag can be automatically regulated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a three-level synchronization delay system that automatically detects delay time differences between component signals caused by digital transmission of a television signal having a three-level horizontal synchronization signal, such as a high-definition component signal. This relates to a detection circuit.

Conventional technology When high-definition component signals are transmitted in parallel using three transmission lines, the detection limit for the delay time difference between each signal is 3.
It is said to be 6nS9C. Considering the case of analog transmission of a component signal, if a coaxial cable is used as a transmission path and the signal is transmitted over 100 meters, a delay time difference of about ±16 nsec will occur due to the wavelength shortening rate deviation of the cable.

Conventionally, therefore, it was necessary to take measures such as adjusting the cable length or inserting a delay line for analog signals. In addition, when transmitting component signals by digitizing them, in addition to the delay time difference due to coaxial cables, A/D, D/
A delay time difference occurs due to the low-pass filter used during A conversion, and this is larger than the delay time difference due to the coaxial cable. That is, a prefilter for band-limiting the input signal and a smoothing filter for smoothing the output signal from the D/A converter are usually used immediately before the A/D converter. According to high-definition studio standards, the sampling frequency of the Y signal is specified as 74.25 MH2, which is twice the sampling frequency of the PR and PR signals. Therefore, the filters used for the PR and PB signal systems have a narrower band than the filters used for the Y signal system, so the delay time is longer than that of the filter for the Y signal system. According to actual measurements by the inventor, there was a delay time difference of about 200 nS6C.

Therefore, conventionally, when designing a transmission device, the delay time difference of the filters was measured in advance, and on the receiving side, a shift register was installed to delay the Y signal at the digital signal stage, or when the Y signal was demodulated into an analog signal. Delay countermeasures were taken at this stage, such as installing analog delay lines in advance.

Problems to be Solved by the Invention In the conventional technology as described above, it is necessary to thoroughly investigate the length of the coaxial cable used for the device, deviation in delay, etc. at the design stage, and it is necessary to thoroughly investigate the delay deviation of the length of the coaxial cable used for the device. Even in this case, it is extremely difficult to estimate the delay time difference below the detection limit in advance due to the delay margin of logic elements and timing changes due to deterioration of digital waveforms, and it is necessary to make design changes after assembly. However, the problem was that it took a long time to make adjustments.

SUMMARY OF THE INVENTION In order to solve the above problem, it is an object of the present invention to provide a delay adjustment circuit that does not require adjustment by detecting and automatically adjusting delay time differences.

Means for Solving the Problems In order to solve the above problems, the present invention provides a first synchronization separator that separates a ternary open period signal from a D/A converted Y signal, and a D/A converted PR. Or a second synchronization separator that separates a ternary open signal from either one of the PR signals, and an average value that differentially amplifies the synchronization signal separated by these, slices it, and then detects the average value of the signal. A detecting section and means for delaying the digital signal of the Y signal based on the detected value are provided.

Effect: By differentially amplifying two synchronously separated three-value open period signals and detecting the average value of the sliced output signals with the above configuration, a delay time difference can be detected. Therefore, by changing the delay time of the digital signal of the Y signal input to the D/A converter according to the magnitude of this average value output,
The delay time difference can be adjusted automatically.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 11 is a D/A converter for D/A converting the Y signal, 12 is a D/A converter for D/A converting the PR signal,
21 and 22 are synchronization separators that separate three-level horizontal synchronization signal parts from the output signals from the D/A converters 21 and 22, respectively; 3 is a differential amplifier that differentially amplifies the two separated synchronization signals; 4 is a slicer that slices the output signal from the differential amplifier 3 at a set level; 5 is an average value detector that detects the average value of the output signal from the slicer 4; and 6 is a slicer that detects the average value of the output signal from the slicer 4; This is a delay unit that delays the digital signal of the Y signal.

The digital Y signal is sent to the D/A converter 1 via the delay section 6.
1, is demodulated into an analog signal, and is output through a low-pass filter (LPF).

The demodulated Y signal is branched and the synchronization signal period is separated by the first synchronization separator 21. The separated synchronization signal is applied to the non-inverting input terminal of the differential amplifier 3. The PR signal is similarly demodulated by the D/A converter 12, passes through the LPF, and is separated into synchronization signal periods by the second synchronization separator 22.

The separated synchronization signal is applied to the inverting input terminal of the differential amplifier 3. The differential amplifier 3 performs differential amplification by two people and outputs it to the slicer 4. The slicer 4 slices the upper and lower amplitudes of the output signal from the differential amplifier 3 at preset levels, and outputs the slices to the average value detection section 6 . The average value detection unit 6 detects the average value from the output signal from the slicer 4, and the delay unit 6 detects the average value from the output signal from the slicer 4.
outputs a voltage of the following magnitude according to the average value.

FIG. 2 shows signal waveforms at major points in this embodiment.

In the figure, a to c show the delay relationship between two synchronizing signals input to the differential amplifier 3, and the output waveform of the differential amplifier 3 and the output waveform of the slicer 4 at that time. P
If the R signal leads the Y signal, the sliced signal will have more pulses of positive polarity than pulses of negative polarity. Conversely, if the PR signal lags behind the Y signal, many pulses of negative polarity will appear in the sliced signal.

The diagram p:J3 shows the relationship between the delay between the two synchronizing signals and the average specific force field voltage detected by the average value detection section 6. If the PR signal advances with respect to the Y signal, the average value output voltage increases, and conversely, if it lags behind the Y signal, it decreases. By slicing the output signal of the differential amplifier 3 and detecting the average value in this way, it is possible to detect the delay time difference between the three-value open signal, that is, the delay time difference between the Y signal and the PR signal.

Therefore, using the characteristics shown in FIG. 3, the delay time of the Y signal may be changed in the delay section 6 so that the average value output voltage becomes zero.

To change the delay time, for example, a shift register and a launch circuit may be used. By shifting by one stage using a shift register, it is possible to delay by one time slot.

When the sampling frequency is 74.26MHz, one time slot is approximately 13 n5ec, and 13 n5ec
The delay time is variable with slap. However, as mentioned above, the detection limit for the delay time difference in terms of image quality is said to be 3.5 nSelC, so adjustment of one time slot or less is required.

This can be done by latching the shifted digital signal and slightly changing the phase of the clock applied to the launch circuit. This can be easily achieved by using a varicap or the like in the clock transmission path and changing the voltage applied to the varicap.

In order to automatically adjust these delay times using the output signal from the average value detection section 6, an N-stage shift register and a selector for selecting one of the N inputs by external control are provided. The outputs from each stage may be connected to a selector, and one of them may be selected depending on the average value output voltage. The delay time can then be adjusted automatically by changing the voltage applied to the varicap.

Effects of the Invention According to the present invention, it is possible to easily detect the delay time difference between two television signals having three-level opening signals, and when a high-definition television signal is digitally transmitted in the component signal format, Although a delay time difference occurs, it becomes possible to automatically adjust this delay time difference, which has great practical effects such as greatly shortening the design period and eliminating the need for adjustment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram of essential parts in the same embodiment, and FIG. 3 is an average value output voltage characteristic diagram with respect to delay time difference. 11.12...D/A converter, 21.22...
... Synchronous separation section, 3... Differential amplifier, 4.
... Slicer, 5 ... Average value detection section, 6
...Delay part. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (2)

[Claims] (1) A first synchronization separator that separates a three-value synchronization signal from one of two television signals each having positive and negative polarity three-value synchronization signals, and a first synchronization separation unit that separates a three-value synchronization signal from the other television signal. a second synchronous separator to separate; and a second synchronous separator to separate the first
a differential amplifier that differentially amplifies the first three-value synchronization signal and the second three-value synchronization signal output from the synchronization separation unit and the second synchronization separation unit; and a differential amplifier that slices the output signal of the differential amplifier. A three-value synchronous delay detection circuit comprising a slicer and an average value detection section that detects the average value of the output signal of the slicer. (2) The horizontal synchronization signal is a three-value synchronization signal with both positive and negative polarities, and the high-definition component signal consisting of a luminance signal (hereinafter referred to as Y signal) and two color difference signals (hereinafter referred to as PR and PB signals) is A/D. A receiver that receives the converted and transmitted signal includes a first synchronization separator that separates a ternary synchronization signal from the D/A converted Y signal;
a second synchronization separator that separates a ternary synchronization signal from either the A-converted PR signal or the PB signal; a differential amplifier that differentially amplifies a first three-value synchronization signal and a second three-value synchronization signal, a slicer that slices the output signal of the differential amplifier, and an average that detects the average value of the output signal of the slicer. A three-value synchronization delay detection circuit comprising: a value detection section; and means for delaying a Y signal input to the D/A converter using an output signal from the average value detection section.