GB2129634A - A self-adjusting delay device - Google Patents

Abstract

A self-adjusting delay device comprising: input means for receiving an input pulse train; a pulse edge phase detector (122) for receiving as a first input signal, the input pulse train and for producing an output signal indicative of the time interval between an edge transition of a pulse of the input pulse train and a second input signal of the detector; and variable delay means (128, 130) arranged to receive the input pulse train and controlled by the output signal of the detector (122) for producing a variable delay output pulse train to a working system (134), a feedback signal from the working system forming the second input signal of the edge detector. The invention is applicable to deskewing the fan-out of clock pulses in a computer system. <IMAGE>

Description

SPECIFICATION A self-adjusting delay device This invention relates to a self-adjusting delay device.

According to the present invention there is provided a self-adjusting delay device comprising: input means for receiving an input pulse train; a pulse edge detector means for receiving as a first input signal, said input pulse train and for producing an output signal whose magnitude is related to the time interval between an edge transition of a pulse ofthe input pulse train and a second input signal of said edge detector means; and variable delay means arranged to receive the input pulse train and the output signal of the edge detector means for producing a variable delay output pulse train to a working system, a feedback signal from the working system forming the second input signal ofthe edge detector means.

The invention is illustrated, merely byway of example, in the accompanying drawings, in which Figure lisa circuit diagram of a time differential delay meter having a delay lock loop according to the present invention; Figure 2 is a time domain waveform diagram showing the operation ofthe delay loop of Figure 1; Figure 3 is a circuit diagram of a self-adjusting phase equaliseraccordingtothe present invention; Figure 4 is a circuit diagram of a self-adjusting delay device according to the present invention; Figure 5 is a circuit diagram of a single input frequency dependent demodulator according to the present invention; Figure 6 is a circuitdiagram of a dual input frequency dependent demodulator according to the present invention;; Figure 7 is another embodiment of a delay lock loop according to the present invention in which a digital feedback controls operation.

Figure 8 is a graph showing the phase-frequency characteristics of a delay lock loop according to the present invention; Figure 9 is a circuit diagram of a phase modulator of a modulator and demodulator apparatus according to the present invention; and Figure 10is a circuit diagram of a phase demodulator of the modulator and demodulator apparatus of Figure9.

Referring now to Figure 1 there is illustrated a time differential meter 10 having a delay lock loop according to the present invention. Afirst (or A) input 12 and a second (or B) input 14 are provided. The input 12 is connected to a differential amplifier 16which shapes the input pulse so that it has a smooth characteristic and does not cause false actiyation. Asecond amplifier 18 is provided in association with a transmission line 20 of a predetermined length so that a pulse travelling through the line 20 has a predetermined time delay. Any otherfixed time delay device may be used in place ofthetransmission line 20.The line 20 is also labelled "lineA" in Figure 1.The line 20 is connected to a first or data input of a D-type flip-flop 22 which forms an edge transition detection device and acts in a way analogous to a phase detector although it is not identical to a phase detector.

Theflip-flop 22 is also an edgetransistion flip-flop and the sawtooth symbol on the flip-flop is used to indicate that as a matter of standard symbol notation.

It is possible to arrange that the delay lock loop of Figure 1 operates on the leading edges of both A and B pulse trains or on the trailing edge of both pulse trains or on the leading edge of one pulse train with respect tothetrailing edge ofthe other pulse train.

The input 14 is connected to a differential amplifier 24 which provides pulse shaping and smoothing for the B pulse train. The output ofthe differential amplifier 24 is connected to a variable delay device 26 which has an outputthrough a fixed length transmission line 28, also labelled "line B" in Figure 1. The line 28 is connected to a second or clock input ofthe flip-flop 22. The line 28 should be of a slightly different length than line 20. Outputs 30,32 corresponding to the respective states of the flip-flop 22 are connected to a voltage divider network composed of resistors 34, 36 from which a single voltage output 38 is derived at a centre tap thereof. Resistors 40,42 provide termina tionfortheflip-flop 22.Afeedback loop is connected from the output 38 byway of a line 44 through an elementary filter 46 to a line 55 and then to the centre tap between a pair or resistors 48,50. The filter 46 is merely provided to ensure thatthe line 44 has a direct cu rrentvoltage thereon without various voltage spikes caused by switching ofthe flip-flop 22.

The resistor50 is connected through avariable resistor 52 to a bus 54 which provides a fixed voltage reference to the second amplifier 18 and to both the differential amplifiers 16,24. Another elementary filter 56 is provided with respect to the bus 54 to ensure that only direct current is present. The resistor 48 is connected to an input of variable delay device 26 and, in combination with a capacitor 58, constitutes a filter.

A device 60 receives a first input from the line 44 and a second inputfrom the bus 54. The output of the device 60 is used to drive a first switch 62 and a second switch 64. The switch 62 controls a light emitting diode 66while the switch 64 controls a light emitting diode 68. The device 60 controls the switch 62 in its one state or condition and the switch 64 in its other state or condition, and the light emitting diodes thus provide an indication of which state or condition device 60 is in.

The operation ofthe circuit illustrated in Figure 1 will now be explained. The negativetransition of A and B pulse trains at inputs 12, 14 respectively are measured and presented as a directcurrentvoltage output at a pair of terminations 70,72 for measurement purposes.

The variable resistor 52 is used to adjust the calibration ofthe output so thatthe phase difference between the A and B pulse trains may be directly measured in time units. Naturally, the output may be displayed on an oscilloscope for example.

The differential amplifiers 16,24 shape the A and B pulse trains to a smooth shape for measurement purposes and control purposes of the flip-flop 22 and also transform the voltage reference to that reference voltage appropriate to the circuit. This reference voltage is derived from the reference voltage on the bus 54.

In the A channel the second amplifier 18 in combination with the transmission line 20 simply introduces a constant delay in the A pulse train provided to the data input of the flip-flop 22 so thatthe adjustment ofthe delay or reference of the delay through the B channel in the circuit may be both positive and negative. Without a fixed delay in the A channel, delay measurement could not be bilateral. If adjustment in only one direction was desired, this fixed delay would be eliminated.

Referring nowto the signal in the B channel as applied to the variable delay device 26, the feedback voltage developed by the flip-flop 22 is provided to a inverting input 73 ofthe variable delay device and then is connected to the clock in put of the flip-flop 22.

The negative going edge ofthe pulses of the B pulse train atthe clock input to the D-type flip-flop 22 causes the pulses ofthe A pulse train to be clocked into the flip-flop 22. Acapacitor 74 is connected between reference ground potential and the line 28 and is adjusted to calibrate the circuit so thatthere is zero outputwhen the A and B pulse trains have zero phase difference. The flip-flop 22 has a Q and aUor not Q output previously referred to as outputs 30,32 respectively. Thefeedbackvoltage on the line 55 is developed by the toggling, or switching, ofthe Q and not Q outputs of the flip-flop 22.The unfiltered voltage on the line 44 which isfiltered by the filter 46 provides a variable voltage on the line 55 which controlsthe threshold level at which the variable delay device 26 output toggles or switches with respect to the input level on the positive input ofthe variable delay device.

The amount oftime delay in a signal passing through thevariable delaydevice 26 is equal and opposite in magnitude to the delay between edge transitions of theAand B pulsetrains. The amount of delay change through the variable delay device 26 is dependent on the input references level thereof, the slope ofthe input transition and the amount of difference between the voltage Vbb and the voltage on the line 55.

The delay control circuit formed by the variable delay device 26 and the flip4lop 22 causes the feedback voltage on the line 44to go low when the not O output 32 is low. A "low" output on the output 32 indicates the clock input ofthe flip4lop 22 was early with respectto the data inputto the flip-flop 22. The going lowtransition voltage feedback to the variable delay device 26 causes the delay therethrough to increase. This increase in voltage, if sufficient, will delaythe clock signal enough to causethe clock input to fall behind the data input atthe variable delay device 26,thus setting the not 0 output 32 ofthe flip-flop 22to a high output.A "high" output atthe output 32 will cause feedback to the variable delay device 26 and decreasethe clock signal path delay time.Theaverngevalue ofthefiltered feedback on the line 55 provided to the variable delay device 26 is dependent on the amount oftimethe not Q output 32 ofthe D-type flip-flop 22 is in the high state and in the low state. The maximum change in voltageforthe filtered feedback is the ratio of the resistancevalueof the resistor 34 to the resistance value of the resistor 36.

The resistor 34 and the resistor 36 limit the feedback voltage swing caused bytheflip-flop22to bethe linear portion ofthe inputtransition voltage level to the variable delay device 26 and to prevent latch-up or locking up oftheflipJlop 22 if the input to channel A is removed. Reference should also be had to Figure 8 for further understanding ofthis operation.

Thefeedbackvoltage on the line 44 is filtered first by thefilter46 and also by the filter constituted by the resistor 48 and the capacitor 58 to smooth the switching transitions ofthe output voltage ofthe flip-flop 22 to provide a direct current level to the inverting input dfthe variable delay device 26. The time constant of these filters determines the lowest repetition rate which can be compared in A and B pulse trains. The filter time constant also determines the speed at which a measurement output can be accurately determined. Obviously, these filters will be constructed to provide as fast a response time as is desirable which is consistent with providing a sufficientlyfiltered direct current level so that the delay lock loop operates properly. The light emitting diodes 66,68 are controlled by the device 60.The device 60 compares the unfiltered feedback level from the line 44 ahead ofthe filter46 with the reference voltage level on the bus 54 which is provided at the inverting inputthereof. Ifthefeedbackvoltage level is more positive than the reference voltage level, then this is an indication thatthe flip-flop 22 feeback is acting to decrease the delayth rough the variable delay device 26 becausethe B channel input signal is arriving laterthan the A channel input signal. This condition will lightthe "long" light emitting diode 68 while the opposite condition will lightthe "short" light emitting diode 66.

If theflip-flop 22 and the variable delay device 26 combination is able to corrector differences in phase or more correctly in terms ofthe present invention, time differential, between the A and B channel inputs, both the light emitting diodes 66, 68 will be on indicating thatthe time differential delay meter is locked on the input signal and that a measurement is available atthe outputterminal 70,72. When the time differential between the A and B channels is greater than the range ofthe circuit, then the long orshort lightwill remain on while the other light will remain off. This is an indication that no output can accurately be derived. The lighting of only one signal light indicates phase difference between the A and B channels is greaterthan the range ofthetime differential delay meter.

The resistor 50 and the variable resistor 52 constitute a voltage divider circuitwhich can be used to calibrate the output ofthe time differential delay meter to provide a convenient relationship between time intervals and voltage intervals. The ratio ofthe resistance value ofthe resistor 50 to the resistance value of the resistor 52 is a function of the transition time ofthe variable delay device 26 and the number of individual feedback controlled circuits in the B channel. For example, the circuit may be designed to shown the relationship of one picosecond to 0.1 mV.

Thus, the time differential delay meter may be calibrated to that relationship.

Referring nowto Figure 2, the waveforms are shown in the time domain and ar labelled with respect to Figure 1. Figure 2 is self-explanatory showing the operation of the time differential delay meter in response to edge transitions on pulses in the A and B channels to provide increasing or decreasing delays through the variable delay device 26.

Referring now to Figure 3, a self-adjusting phase equaliseraccording to the present invention is shown.

Aclock input signal is received at input 100 and is provided to the data input of an edge transition flip4lop 102 similartothat ofthe D-typeflip-flop 22 shown in Figure 1. Thefeedback output of the flip-flop 102 is passed through a filter 1 04to a pair of delay control devices 106, 108 ofthe same type as the variable delay device 26 shown in Figure 1. The delay control device 106 controls a variable delay in a transmission path 110 while the delay control device 108 controls a variable delay in a transmission path 112. The clockinputsignal is connected through the path 112 through a fan-out orfeedback network 1 14to thevariousoperating orworking ranks at various locations in a computer.This is represented generally by box 116. Time related feedbackfrom individual working ranks is provided through a transmission line of exactlythe same length to have the same time delay asthetime delaythroughthetransmission lines on thefeedbacknetwork 1 in providing the clock signalsto the working ranks of the computer. A feedbacksignal is providedtothe path and provides the clock inputto the flip-flop 102.

The self-adjusting phase equaiiser of Figure 3 uses theflip-flop 102 in a way analogousto a phase detector. Phase shiftfrom a clock input signal to various individual working ranks in a computer undergo phase shift if the basic clockfrequency changes in a high clock rate computer system. Clock frequency changes are made in ordertotesttheclock frequency margins ofthe computerwith respectto the individual working ranks ofthe computer which are controlled by a master clock oscillator. The selfadjusting phase equaliser of Figure 3 corrects for all oscil latorfrequency changes within the operating range of the variable delay transmission paths.Phase shifts as detected at the working rank 116 due to changes in the clocktime delaythrough thefeedback network 114 are significantly reduced. Both the clock delay in the feedback network and in the transmission paths are variable. A correcting voltage generated by the flip-flop 102 as passed through the filter 104 changes the time delay in both delay control devices 106,1 08to maintain a constant phase relationship in all clock circuits.

Referring nowto Figure 4, a self-adjusting delay device 120 according to the present invention is shown. An edge detection flip-flop 122 receives a clock input signal on a data input channel. The voltage related output is passed through a line 1 24to a filter 126 to provide a direct current to a delay control device 128. The clock input signal is connected through a variable delay channel 130 controlled bythe delay control device 128 to a fan-out system 132 for a computer clock control system. The working rankof thecomputeris indicated by reference numeral 134.

Feedbackfromtheworking rank is provided th rough an equal time delay channel to the clock input of the flip-flop 122. The delay lock loop of Figure 4forms a self-adjusting delay device for deskewing the clock fan-out in a computer system. Clockfan-out skew can occurdueto integrated circuit chip ageing, replacement of chips, replacement of circuit boards, changes in cabling, and other factors relating to ageing and operation of the computer system. The self-adjusting delay device shown in Figure 4 can correct for all phase differences within the range of the variable delay channel 130 and can also compensate for changes in clock freq uency. The fl ip-flo p 122 provides a correction signal voltage which is filtered by the filter 126 and connected to the delay control device 128.The correction voltage occurs if the signal phase at the data and clock inputs oftheflip-flop 122 are not equal.

If there is a phase difference, the delay control device 128 corrects the delay by adjusting the variable delay ch annel 130 until a the phase at i nputs to the flip-flop 122 are equal. Because the working rank 134 is halfway between the delay control device 128 and the flip-flop 122, clock frequency changes in phase are reduced by a factor of 2.

Referring nowto Figure 5, a single input frequency dependent demodulator 140 according to the present invention is shown. An input signal on a line 142 is provided to a data inputA of an edge transition flip-flop 144which produces an output correction voltage on a line 146which is passed through a filter 148. The input signal on the line 142 is also passed through a fixed delay device 150 which may be simply a length oftransmission cable to a variable delay channel 1 52 and final ly to a clock input B of the flip-flop 144. A delay control device 154 controls the operation of variable delay channel 152 and is controlled by the voltage outputfrom the filter 148.An output from the filter 148 is provided astheoutputofthedemodulator in which phase shifts in the input signal on the line 142 have been converted to amplitude shifts in the filtered signal for amplification or measurement. These phase shifts are created artificially bythefixed delay device 150 so that phase shifts in the input signal can be detected. The flip-flop 144, operating in a way analogous to a phase detector, locks onto a delayed cycle ofthe input pulse train at the data input A of the flip-flop. This is shown by the notch symbol on the transition ofthe signal.The clock input B ofthe flip-flop is locked on eitherthe leading ortrailing edge ofthe input pulse train with respect to the signal at the data input The delay ofthe signal clock input is shown by use of the symbol on a later pulse in the pulsetrainto showthe time delay.

Referring nowto Figure 6, a dual input frequency dependent demodulator according to the present invention is shown. A reference oscillator 160 provides an input pulse train to a data input A of an edge detecting flip-flop 162 operating in a way analogous to a phase detector. An input signal is provided on an input line 164through a variable delay channel 166to a clock input B ofthe flip-flop 162. The variable delay channel 166 is controlled by a delay control device 168 which receives a feedback signal through a filter 170 from the output of the flip-flop 162. An output of the filter 170 provides a voltage output in which phase shifts with respectto the signal produced by the reference oscillator 160 of the input signal on the line 164 are converted to voltage amplitude shiftsfor measurement or detection purposes. Thus, the input signal on the line 164 may be controlled to lock on to the frequency ofthe oscillator 160.

Referring nowto Figure 7, another embodiment of a delay lock loop according to the present invention in which a digital feedback control operation is shown.

An A channel reference signal is input to an adjustable delay network 180 which is adjusted to zero the circuit.

The outputfrom the adjustable delay circuit 180 is connected to a data input D of an edge detecting flip-flop 182. A programmable delay circuit 184 provides an inputto a clock input c ofthe flip-flop 182 and this also becomes the phase corrected output pulse ofthe circuit. A B channel input is provided to both the programmable delay circuit 184 and a sample rate device 186. The sample rate device 186 has an output connected to the input of an up-down counter 188. The up-down counter 188 is, in turn, connected with the programmable delay circuit 184. A driver display circuit 190 monitors the output of the up-down counter as connected to the programmable delay circuit 184. The output of flip-flop 182 is provided as an input into the up-down counter 188.A 0 output of the flip4lop causes a down count if it is one while a Q or not Q output of the flip-flop 182 causes an up count if one. The operation of this embodiment of the present invention is similarto thatwhere an analog feedback is provided except that, of course, the feedback is a digital feedback.

To zero adjustthe delay lock loop of Figure 7, signals are provided to the A and B channel inputs with a zero phase difference and the adjustable delay network 180 is adjusted for zero indication on the display device of the driver display circuit 190. This can be setto be in the middle ofthe range ofthe programmable delay circuit 184 if both positive and negative delay correction is desired or at either end ofthe range if only correction in one direction is desired.

If signal atthe input D of the flip-flop 182 is high atthetime a clock signal at a clock input CK is received, theflip-flop will set placing a binary one atthe down count enable on the up-down counter 188 and a binary zero atthe up count enable. Atthe next edge of a pulse atthe B channel input, the up-down counterwill down count reducing the delay through the programmable delay circuit 184 by onetime period.Once the signal has propagated through the programmable delay circuit 1 84to the clock input of the flip-flop 182, which is at a time earlier than before, the B input is again detected. lithe D inputto the flip-flop is still a high on the next pulse at the B channel input, the up-down counter counts down one more time period and reduces the programmable delay to cause the B channel input to occur at an earlier time period. The delay through the programmable delay circuit 184 will keep reducing until at clock time in the flip-flop 182 the input D is low.Atthattime, theflipflop will clear, placing a binary one on the up count enable of the up-down counter and binary zero at the down count enable, enabling the up-down counter to be up counted on the next pulse atthe B channel input. In this case, the programmable delay circuit 184 will be increased by one count At this time, the delay lock loop is locked on the signal at the B channel inputs and theflip4lop 182 will toggle between set and clear causing the up-down counter 188 to increase and decrease the delaythrough the programmable circuit 1 84 by one time unit. The output of the up-down counter can nowbeprocessedordisplayedasthe phase difference between the signals A and B channel inputs orthe output from the programmable delay circuit can be used to drive other circuits.The delay lock loop of Figure7 can be used in all ofthe same configurations as the delay lock loops shown in Figures 1 to 6. The circuit shown in Figure 7 compares leading edges of pulses atthe A and B channel inputs if theflip4lop 182 is a leading edge triggered D-type flip-flop. Similarly, the trailing edge may be detected if desired, orthe circuit may be configured so thatthe leading edge of a signal at the A channel input is detected while thetrailing edge ofthe signal atthe B channel input is detected orviceversa.

There are several significant differences between the delay lock loop of Figure 7 and those of Figures 1 to 6. Primarily, there is no analog feedbackvoltage.

There are no low frequency locking limitations. Of course, a digital voltmeter is not required to measure feedback voltage. The delay inserted in the B channel input is digitized fordisplay or processing purposes in further devices. The up-down counter and programmable delay circuit comprises a memory delay feedback circuit. In the absence of a signal atthe B channel input, no correction occurs. Delaythrough the programmable delay circuit does not change. When a signal atthe B channel input does occur, thefirst pulse will be phase corrected as long as its phase relationship with the signal attheA channel input has not changed. No pulse narrowing or change of pulse shape occurs with the corrected output signal.

Figure 8 is a frequency phase relationship graph which explains the delay lock loop of Figure 1 and which serves to distinguish it from the characteristics of a phase lock loop circuit.

Referring nowto Figure 9, a modulator and demodulator apparatus according to the present invention has an edge detection flip-flop 200 which receives a data input signal from an oscillator 202 and which provides a 0 and a O or not 0 output to a voltage divider network composed of resistors 204,206. The oscillator 202 also produces a transmitted output signal on a line 208 which is referred to as a pilot signal. The output of the oscillator 202 is also connected as a signal inputto a variable delay control device 210 which has its output connected to a clock inputoftheflip4lop 200. The output ofthe variable delay control device210alsoformsthe modulated signal output ofthe circuit after passage through a half cycle, one shotflip-flop 212 which produces a transmitted signal. The output ofthe voltage divider network is connected to a filter 214 having a first band pass frequency characteristic. The output ofthe filter 214 is connected as a control signal for a control device 216forthe variable delay control device 210.

The signal to be modulated is provided on an input line 218where it is summed together with the signal from the filter 214 and provides an input signal to the control device 216.

Referring nowto Figure 10, a demodulator ofthe modulator and demodulator apparatus for demod ulating the signal generated by the modulator of Figure 9 is shown. The pilot signal generated bythe oscillator 202 in Figure 9 is provided as the data input to an edge detection flip-flop 220 which has 0 and or not Q outputs connected to a voltage divider network composed of resistors 222,224. The phase modulated signal generated as the output oftheflip-flop 212 in Figure 9 is provided as an input data signal to a variable delay control device 226 as shown in Figure 10. The delay control device 226 has its output connected to the clock input oftheflip-flop 220.The output of the voltage divider network is connected as an inputto a filter 228 having a second band pass characteristic differentfrom that of the filter 214 shown in Figure9.Theoutputofthefilter228 is connected with a control device 230 which controls the variable delay control device 226. The output of the filter 228 also comprises the demodulated output signal from the demodulator. It is desirable that the filters 214,228 have completely different band pass characteristic although it is believed that the circuit would be functional if some overlap of band character istics was to occur. For example, the filter 214 might have a frequency characteristics rolling off from direct current to attenuate at some given frequency.The filter 228 mighttherefore have a band pass characteristic above the predetermined frequency ofthe filter 214.

The pilot signal generated bythemodulatorof Figure 9 may be directly connected through appropriate signal lines to the demodulator of Figure 10 or various subcarrier relationships may be generated or the signals may be harmonically related and locked togetherexceptforthe modulation deviations.

Obviously many variations of conveying the two signals from the modulator to demodulator may be employed all within the scope ofthe communications art.

Byway of expla natio n, the flip-flops 212 in the modulator of Figure 9 serves the function of stretching the phase modulated orrtput so th at the phase modulated output signals are outside the pass band of the filter 214. Signals falling within the pass band range ofthefilter 214 are rapidly attentuated or eliminated as a result of the basic operation of the delay lock loop. It is possible to generate phase modulated signals with the embodiment of the invention shown in Figure 9. The filter 214 does have the desirable effect of filtering outofthetransmitted signal certain complements ofthe modulating signal falling within the pass band ofthe filter.Thus, the input signal to be modulated is merely added directly to the output of the filter 214.

Using the circuit configurations of Figures 9 and 10 but in which a digitally controlled feedback loop such as that shown in the embodiment of Figure 7 would provide forthe additional feature of data coding. This would be implemented by adding additional logic gates in the feedback loop between the flip-flop 182 and the up-down counter 188 as shown in Figure 7 but in a modulator such as shown in Figure 9to insertthe coding functions in the feedback loop. This could be implemented most simply by causing the up-down counterto have a nonlinear up and down count characteristic. For example, the counter could be madeto increment byone unitand decrement bytwo in orderto provide a nonlinearcodingfunction.Then, a receiver would be required which would have the complementarynonlinearcharncteristicfordemod- ulation. Another example of modulation coding could beto increment and decrement bytwo unitsforsmall deviations of signal output but to increment and decrement the counter by one unitfor modulating signals above a threshold level, thus distorting the information carried if a lineardemodulatorwere used.

Only a demodulatorwith a precise predetermined digital nonlinearity characteristic complementary to the modulator characteristic would reproduce the modulated signal accurately.

Claims (3)

CLAIMS 1. Aself-adjusting delay device comprising: input means for receiving an input pulse train; a pulse edge detector means for receiving as a first input signal, said input pulse train and for producing an output signal whose magnitude is related to the time interval between an edge transition of a pulse ofthe input pulse train and a second input signal of said edge detector means; and variable delay means arranged to receive the input pulse train and the output signal of the edge detector means for producing a variable delay output pulse train to a working system, a feedback signal from the working system forming the second input signal of the edge detector means. 2. Aself-adjusting delay device substantiallyas herein described with reference to an as shown in the accompanying drawings. Newclaimsfiled on 28 November 1983 Superseded claims 1,2 New claims:

1. Aself-adjustingdelaydevicecomprising: input means for receiving an input pulse train; pulse edge detector means for receiving, as a first input signal, the input pulse train and for producing an output signal related to the time interval between an edge transition of a pulse of the input pulse train and a second input signal ofthe edge detector means; first variable delay means connected to receive the input pulse train for producing a firstvariable delay output pulse train with respect to the input pulse train, the first output pulse train being provided on a first transmission linethrough a fan-out system to a computer clock control system which is arranged to provide a first feedback signal through a second transmission line having the same time delay as the first transmission line, thefirstfeedback signal forming the second input signal ofthe edge detector means; and feedback means for producing a second feedback signal from the the output signal of the edge detector means to provide a control input to thefirst variable delay means to control the outputthereof.

2. A device as claimed in claim 1 comprising second variable delay means arranged to receive the first feedback signal from the computer clock control system for providing a second variable delay output pulse train with respect to the output signal of the computer clock control system, the second output pulse train forming the second input signal of the edge detector means, and the second feedback signal providing a control input to the second variable delay means to control the output thereof.

3. Aself-adjusting delay device substantially as herein described with reference to Figure 3 or 4 of the accompanying drawings.