GB8320339D0 - Self-adjusting delay device - Google Patents
Self-adjusting delay deviceInfo
- Publication number
- GB8320339D0 GB8320339D0 GB8320339A GB8320339A GB8320339D0 GB 8320339 D0 GB8320339 D0 GB 8320339D0 GB 8320339 A GB8320339 A GB 8320339A GB 8320339 A GB8320339 A GB 8320339A GB 8320339 D0 GB8320339 D0 GB 8320339D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- self
- delay device
- adjusting delay
- adjusting
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8320339A GB2129634B (en) | 1980-03-10 | 1983-07-28 | A self-adjusting delay device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/129,056 US4309673A (en) | 1980-03-10 | 1980-03-10 | Delay lock loop modulator and demodulator |
US06/129,286 US4338569A (en) | 1980-03-11 | 1980-03-11 | Delay lock loop |
GB8320339A GB2129634B (en) | 1980-03-10 | 1983-07-28 | A self-adjusting delay device |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8320339D0 true GB8320339D0 (en) | 1983-09-01 |
GB2129634A GB2129634A (en) | 1984-05-16 |
GB2129634B GB2129634B (en) | 1984-10-31 |
Family
ID=27262167
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8320339A Expired GB2129634B (en) | 1980-03-10 | 1983-07-28 | A self-adjusting delay device |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2129634B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2197553A (en) * | 1986-10-07 | 1988-05-18 | Western Digital Corp | Phase-locked loop delay line |
US4922141A (en) * | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
TW340262B (en) | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
US6158030A (en) * | 1998-08-21 | 2000-12-05 | Micron Technology, Inc. | System and method for aligning output signals in massively parallel testers and other electronic devices |
FR2968787A1 (en) * | 2010-12-13 | 2012-06-15 | Commissariat Energie Atomique | DEVICE AND METHOD FOR SIGNAL PROPAGATION DELAY COMPENSATION |
EP2775655B1 (en) | 2013-03-08 | 2020-10-28 | Pro Design Electronic GmbH | Method of distributing a clock signal, a clock distributing system and an electronic system comprising a clock distributing system |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB676253A (en) * | 1950-02-16 | 1952-07-23 | Derek Anthony Underwood Rush | Improvements in or relating to pulse-synchronising circuits |
US3644756A (en) * | 1970-08-05 | 1972-02-22 | Ibm | Time analog converter circuit for jitter-free operation |
US3748572A (en) * | 1972-05-04 | 1973-07-24 | Honeywell Information Inc | Wide frequency range phase shifter device |
JPS5665530A (en) * | 1979-10-31 | 1981-06-03 | Sony Corp | Pll circuit |
US4250454A (en) * | 1979-03-26 | 1981-02-10 | International Telephone And Telegraph Corporation | Electronic trigger for a radio frequency source |
-
1983
- 1983-07-28 GB GB8320339A patent/GB2129634B/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2129634A (en) | 1984-05-16 |
GB2129634B (en) | 1984-10-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |