JPH02140037A - Atm exchange - Google Patents

Abstract

PURPOSE:To eliminate the need for a cell separation/insertion circuit and a cell multiplex/demultiplex circuit by arranging an ADP processing section to the rear side of an ATM switch and utilizing the ATM switch so as to collect/ distribute cells for a signal channel. CONSTITUTION:A subscriber line signal device 1 comprising an ADP processing section 100 applying adaptation processing and an LAPD.LSI 101 applying layer 2 protocol processing of a signal channel is connected to a relay line side of the ATM switch 30. The device 1 is connected to a processor 40 applying layer 3 protocol processing of the signal channel, header conversion table revision, initial value setting of a switch 30 and control of the LAPD.LSI 101 or the like. A memory 41 is used for a storage area and a work area for a program executed by a processor 40. A subscriber line interface section 10 and a relay line interface section 20 apply addition/delete of an optical/electric signal and a route information part to each cell or the like respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switch, and particularly to an ATM (Asynchronous
(Transfer Mode) switching equipment.

[Conventional technology]

I S D N (Integrated 5ervi
ces Digital Network), an information channel for user information transfer.

Signal channel (D
It has two types of channels:

As a signal channel processing method in an ID5N switch, for example, the Institute of Electronics, Information and Communication Engineers Technical Research Report 5E87-8
Figure 1 of “Signal processing method of 5 rI interface switch”
2, or as described in Japanese Patent Laid-Open No. 131652/1982, the signal channels and information channels from multiple subscriber lines are separated, and only the signal channels are once multiplexed to guide the signal processing device. After that, Layer 2 (LAPD: Link Accesses) of the signal channel
s Procedure on the D-chan
nel) and a method for performing layer 3 (call control) processing is known.

By the way, the CCITT (International Telegraph and Telephone Consultative Committee) is currently considering broadband l5DN as the next generation l5DN. Broadband I5DN attempts to provide subscribers with switching services at a line speed of, for example, 150 Mbit/S, and according to CCITT Recommendation 1.121 draft, ATM (Asynch)
The ronous Transfer Mode (asynchronous transfer mode) switching system has been cited as a promising means of realizing the broadband I5DN.

The ATM switching system is a system in which all data, including signals and information, is transmitted and received in the form of fixed-length packets called "cells."1For example, as shown in FIG. 5(A), a signal frame 50 is added When a subscriber terminal transmits, it first decomposes the frame 5o into fixed-length cells 51A to 51N (this process is called segmenting), and sends out the cells to the subscriber line. On the exchange side, the received cell 5
The signal frames 50 are reproduced from 1A to 51N (this processing is called rearassembling), and then signal processing is performed. Conversely, when a signal frame is transmitted from the exchange side to a subscriber terminal, segmenting is performed on the exchange side and reassembling processing is performed on the subscriber terminal.

This segmenting/reassembling process is performed by CC
In the draft ITT Recommendation 1.121, it is positioned as a function of the adaptation layer.

Hereinafter, in this specification, the processing section of the adaptation layer including segmenting/reassembly processing will be referred to as rADP.
processing section.

The system configuration and signal processing when the above-mentioned ATM switch is implemented using the same method as the conventional 15DN switch are described in the 11th section.
This will be explained with reference to the figures. In the same figure, 11 (11~
1 to 1l-j) are optical fibers with a transmission speed of about 150 Mbit/s, and 10 (10-1 to 1O-j) are optical fibers with a transmission speed of about 150 Mbit/s, and 10 (10-1 to 1O-j) are optical fibers/f! 12 is a subscriber line interface unit for exchanging signals, etc.; 30 is an ATM switch for exchanging cells;
(12-1 to 12-j) are 8-bit buses.

Subscriber line interface section 10 and ATM switch 3
Cell separation/insertion circuit 16 (16-1 to 16
-j) is installed, and the receiving system (subscriber line interface section 1
0 to the ATM switch 3o), only the signal channel cell is separated and taken out, and the transmission system (ATM
Cells from the switch 3o toward the subscriber line interface section 1o) insert cells of a signal channel. Cell data from each cell R/insertion circuit 16 is multiplexed by a multiplex/separate circuit (MUX) 17 and connected to the subscriber line signaling device 1 via a bus 19. The subscriber line signaling device 1 includes a circuit (MUX) 18 that multiplexes/demultiplexes cell data for each subscriber line, and an ADP processing unit 100 (100-1) that performs the segmenting/reassembling process described above.
~100-j).

LAPD/LSI that performs layer 2 processing of signal channels
l0I (101-1 to 101-j) and bus 103
It consists of

[Problem to be solved by the invention]

However, according to the above method, in order to concentrate only the cells of the signal channel, a cell separation/insertion circuit 16 is required for each subscriber line, and a MUX 17 and a bus for connecting them are required. Furthermore, in the subscriber line signaling device 1, the MUX 18 and the AD for each subscriber line are
A P processing section is required.

An object of the present invention is to provide a subscriber line signaling device with a simpler configuration;
Another object of the present invention is to provide an ATM switch having a trunk line signaling device.

[Means to solve the problem]

In order to achieve the above object, the present invention collects and distributes cells of a signal channel using an ATM switch by installing a subscriber line signaling device including an ADP processing unit on the trunk line side of an ATM switch. , is characterized in that adaptation processing is performed common to each subscriber line.

The present invention further provides a trunk line signal device including an ADP processing section.
It is characterized by being installed on the subscriber line side of the TM switch.

Note that as a similar method for connecting a subscriber line signaling device and a subscriber terminal via a switch, for example, Japanese Patent Laid-Open No. 63-78
There is a method described in Japanese Patent No. 637, but the above-mentioned conventional method does not take adaptation processing into consideration, and also requires a circuit such as a subscriber line scanning unit to detect a signal frame.

[Effect]

According to the present invention, the ADP processing unit is placed behind the ATM switch, and cells of a signal channel are collected/distributed using the ATM switch, so that cells can be separated/distributed.
An insertion circuit and a cell multiplexing/demultiplexing circuit are not required. In addition, by executing adaptation processing in common for each subscriber line or for each trunk line,
The amount of hardware required for adaptation processing can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are system configuration diagrams showing embodiments of the present invention, respectively, and include an ADP processing unit 100 that performs adaptation processing such as segmentation and reassembly, and a layer 2 protocol processing of signal channels. LAPD-LSllol (101-1~101-Q
) is connected to the trunk line side of the ATM switch 30 via the bus 15. The subscriber line signaling device 1 also performs layer 3 protocol 1 processing of the signal channel, updates of a header conversion table (described later), initial value setting of the ATM switch 30, and LAPD-LSI processing via the bus 103. It is connected to a processor 4o that performs control and the like.

A memory 41 is used as a program storage area and a work area to be executed by the processor 40. 11
(11-1 to 1i-j) are, for example, 150 Mbit
It is an optical fiber etc. with a transmission speed of about 14/s.
(14-1 to 14-k) are, for example, 150 Mbit
It is an optical fiber with a transmission speed of about 600 Mbit/s or 600 Mbit/s. Also.

12 (12-1 to 12-j), 13 (13-1 to 1
3-k) and 15 are buses each having a width of, for example, 8 bits, and the subscriber line interface section 10 and the trunk line interface section 20 respectively transmit route information for optical/electrical signals and 5 individual cells. Add/delete sections, etc. Note that although the lines 11-1 to 14-k are each shown as a single line in the figure, they each consist of a pair of a human power line and an output line.

30 is an ATM switch for exchanging fixed length cells;
For example, it is possible to employ the method described in the Technical Report 1N38-38 "A Proposal of rATM Switching Architecture" by the Information Network Study Group of the Institute of Electronics, Information and Communication Engineers. In the same figure, if the number of input/output buses of the ATM switch is 32x32.

j=32. =31. Here, if you want to secure a 32x32 input/output bus for exchanging cells of the information channel, set the number of input/output buses of the ATM switch to 32x33, or 32x34, etc., and connect one or two buses on the trunk line side to the signal line. It is sufficient to use a dedicated channel bus.

In the embodiment shown in FIG. 1, each subscriber line has LAPD-
The LSI is installed (j=α), but if j>Q
The number of LAPD-LSIs can be reduced as j < Q
By doing so, backup LAPD-LSI is available in the event of a failure.
It is also possible to have a configuration with Furthermore, the embodiment shown in FIG. 2 performs layer 2 processing of signal channels for a plurality of subscriber lines (11-1 to 1i-j) using one
This shows the method executed by l.

FIG. 3 shows the transmission system 10 in the ADP processing section 100.
A block diagram showing 0A, FIG. 4, shows the above ADP processing section 1.
2 is a block diagram showing a receiving system 100B in 00. FIG.

In the CCITT Recommendation 1.121 draft mentioned above, self-formatting, cell size, etc. have not yet been determined. Therefore, in the ADP processing shown in FIGS. 3 and 4 above, the process shown in FIG.
The self-automation shown in is assumed. Each cell has 36
It is composed of a 4-byte cell ladder 52 and a 32-byte information field 53. The numbers of the originating and destination terminals and data transmitted between terminals necessary for call control are set in the above information field. The first 12 bits of the cell ladder 52 are ■CN (Vir
tual Channel Number) field 520, and a reserved field 521.
and HCS (HeaderC) for cell header abnormality detection.
heck5equence) field 522. Further, at the beginning of the information field 53, there is a 2-byte ADP ladder 54. Therefore, the frame data storage area 55 shown in FIG. 2A is 30 bytes per cell. The ADP header 54 includes a 2-bit cell type field 542 that indicates whether the cell is at the beginning of the frame, end of the frame, middle of the frame, or 1 cell = 1 frame, and a 1-by-1 field that indicates the effective information length of the information field.
- area 543 and a reserve area 541.

For example, if the inter-flag frame length of frame 50 in FIG. 5A is 6 bytes, if this is segmented into cells, the cell type will be 1 cell = 1 frame and the effective information length will be 6. If the frame length is 40 bytes, the first cell whose cell type is the beginning of the frame and whose effective information length is 30, and the cell type which is the last cell of the frame and whose effective information length is 10.
The second cell is divided into two cells.

Note that the route information section 5 attached to the beginning of the cell in FIG. 5(B)
6 is added only within the ATM exchange, and each cell is transmitted to the subscriber [11 and the relay 1114 in a format in which the route information section 56 is deleted. This route information section records information indicating which outgoing line the cell should be transmitted to when exchanging cells at the ATM switch 30, the subscriber line line number, the trunk line line number, etc. used for

Next, regarding the details of the transmission system 100A of the ADP processing section,
This will be explained with reference to FIG.

The transmission line selection unit 110a selects signal lines 102a (102a-1 to 102a-Q) each consisting of a set of three lines: transmission data (TxD), transmission clock (TxC), and echo (E).
) corresponding LAPD-LSIIOI (1
01-1 to 101-Q), and performs contention control when frames are sent simultaneously from multiple LAPDs.
It has the ability to extract only frames from a specific line. As this contention control procedure, the D channel access procedure described in CCITT Recommendation 1.430 can be used. The line number selected as a result of contention control is notified to the control unit CTL 190A, and the transmission data is sent to the frame detection unit 112. Note that the transmission line selection section 110a is a line that is necessary only in the first embodiment of the present invention.

The frame detection unit 112 detects D of the intra-frame address part.
L CI (Data Link Connection
n Identifier) to the CTL190A, and also sends the FCS (Frame
After deleting the '0' bit for flag identification from the data up to the Chsck 5equence part.

The data is converted into 8-bit parallel data and sent to the counter section 116. Further, if the data is the last data in the frame, this fact is notified to the counter section 116 via the Fina1 notification line.

The counter unit 116 transfers the frame data to the FIFO
A: Transfer 1204m. If 30 bytes of data is transferred to FIFO-A 120 and FIFO-A becomes full, or if the last data of the frame is transferred, the cell identification 542 shown in the ADP header format of FIG. 5 (I3) The effective information length 543 is notified to the CTL 190A, and thereafter data sent from the frame detection unit 112 is transferred to the FIFO-B 1212 i:. FI
Even when transferring F O-H data, FIF
When the O-B becomes full or the last data of the frame is transferred, the counter section 116 notifies the cell type and effective information length to the CTL 190A, as in the case of transferring data to FIFO A. The subsequent data is FIFO-
Transfer to A120. In the above manner, FIFO・A
and FIFO-B are used alternately.

The CTL unit 190A includes, for example, μCPU, ROM, and R
AM, it has an internal DLCI/header correspondence table 191, and this table contains one line number and a DLC
The contents of the header corresponding to each combination of Z (Figure 5 (B)
) from route information 56 to ADP header 54.
Bye 1-) is.

It is set from the processor 40 via the bus 103. C
Upon receiving the notification of the serial number and DLCI, the TL unit 190A searches the DLCI/header correspondence table 191 and stores the contents of the corresponding header in the header register 118.
write to.

However, in the second embodiment of the present invention, DLCI/
Search the header correspondence table 191, then DLCI
Using the conversion table 195, the unique LCI is converted into the DLCI to be actually transmitted to the subscriber device. Thereafter, upon receiving notification of the cell type and effective information length from the counter unit 116, the corresponding register in the header register is rewritten according to the ADP header format 54 in FIG. 5(B), and the selector (S E L) 122 Start.

The 5EL 122 first transmits the data in the header register 118, then transmits the data in the FIFO-A 120, and completes the cell transmission.

When the 5EL 122 is next activated by the CTL 190A, it transmits the data in the header register 118 and then the data in the FIFO-B 121, completing the cell transmission. Thereafter, the 5EL 122 alternately transmits the contents of FIFO-A and FIFO-B.

Note that the CTL unit 190A performs the search process for the DLCI/header correspondence table 191 and the process for setting the ADP header in the header register separately, and furthermore, the data in the header register 118 is read by the 5EL 122. If the header does not change even when the cell is transmitted, the amount of processing for creating a header associated with cell transmission can be reduced. For example, when transmitting one frame by dividing it into multiple cells, the search process for the DLCI/header correspondence table is performed only when transmitting the first cell of the frame, and for subsequent cells, only the ADP header part in the header register 118 is searched. By rewriting , there is no need to search the DLCI/header correspondence table 191 for each cell.

Next, details of the reception system 100B of the ADP processing section.

This will be explained with reference to FIG.

The cell writing unit 124 is connected to the ATM switch 30 via the reception bus 15b, and receives cells of the signal channel from the subscriber device. The received cell data is transferred to the address indicated by the WQ (WriteAddress) register in the cell writing section 124. Thereafter, data in the free address PIFO 130 is set in the write address register WA 125 in preparation for receiving the next cell.

126 is a buffer memory (BFM), and on the BFM there is a first buffer BF in FIFO format for once receiving and storing cells arriving at a speed of 150 Mbit/s, and then a reassembling process. For this reason, it is composed of second buffers BF-1 to BF-n in FIF○ format prepared for each combination of line number and VCN in the cell header. In addition, the configuration of FIFO format BP on BFM126, how to use chain pointer, and WA
Regarding the usage of RA (Read Address) and free address FIFO, see the above-mentioned document rATM.
A Proposal for a Switching Architecture".

The control unit CTL190B has a read address register RA192 for the first buffer BF, and among the contents of the cell at the address indicated by RA, the line number recorded in the route information section, the VCN in the cell header, and the ADP header The cell type is checked, and the cell data is first transferred to the second buffer BF-i having the corresponding line number and VCH combination. In this case, data is not transferred from memory to memory, and the second
Transfer processing is executed only by rewriting the buffer address table 193 and buffer chain pointer.

Also, as a result of checking the cell type in the ADP header,
When the reception of cells for one frame is completed, the start address of the buffer in which the first cell of the frame is stored and the line number are stored in the transfer order storage PIFO 194. The CTL 190B activates the parallel-to-serial conversion section (P/S section) 128 according to the data in the transfer order storage FIFO, and at the same time specifies the outgoing line number to the reception line selection section 110b. Note that in the second embodiment of the present invention, the DLCI conversion table 195 is used when the P/S unit 128 is activated.

Unique LCI from DLCI from subscriber equipment
, and simultaneously notifies 278 copies of this unique LCI.

The P/S unit 128 is activated by the CTL 190B.
Read the data at the specified address, convert the data other than the header part into serial data, insert '0', add the cell type flag, and then send this data to the receiving line selection unit 110.
Send to b. Note that in the second embodiment of the present invention, conversion from unique to LCI is also performed.

The reception line selection unit 110b selects a signal line 102 that is a set of two lines: reception data (RxD) and reception clock (RxC).
LAPD by b (102b-1 to 102b-u)
- It is connected to LSIiOl (101-1 to 101-fl) and has the function of sending data only to the signal line with the line number specified by CTL 190B. In addition, the reception line selection section 1
10b, like the transmission line selection section L10a shown in FIG. 3, is necessary only in the configuration of the first embodiment of the present invention, and is unnecessary in the configuration of the second embodiment of the present invention.

FIGS. 6 and 7 are diagrams showing an example of a specific structure of a transmitting system 100A and a receiving system 100B of an ADP processing section configured by applying a microprocessor to the control CTL. These are functionally the same as the circuits described in FIGS. 3 and 4.

The transmission system 100A shown in FIG. 6 includes an interface 301 for connection to the bus 103 on the processor 40 side, a path beater 302, a microprocessor 303, a program memory 304, and a RAM 305 that constitute the CTL 190A. , the transmission line selector 110a and the frame detection unit 11 already explained in FIG.
2° counter section 116. Header register 118. A 6-bus arbiter 302 in which selectors 122 are interconnected by an internal bus 108 is connected to a microprocessor 3.
04 and a request to use the bus 108 from the external processor 40 that is output via the interface circuit 301!
This is for one-way control. In RAM305, D
An LCI/header table 191, a DLCI conversion table 195, and a work area 196 used by the microprocessor for ADP processing are formed.

The transmission circuit selector 110A has a line number register 311, and when the selected line number is set in the register 311, the transmission circuit selector 110A sends a
03, the microprocessor 303 reads the contents of the register via the internal bus 108.

The DLCI register 312 of the frame detection unit 112, the effective information length register 313 of the counter unit 116, and the cell type register 314 are also processed by the microprocessor 303 in the same manner.
is read.

Similarly to the transmitting system, the receiving system 110B shown in FIG. 7 has a configuration in which the elements shown in FIG. Writing to the received cell is done via the upper internal bus 108, and the writing to the buffer area BF
The microprocessor 303 also transfers data from the second buffer area to the second buffer areas BF-1 to BF-n and from the second buffer area to the P/S converter 128 via the internal bus. - In the above embodiment, the CTL unit 1 using μCPU
Although each hardware of the ADP processing unit 100 is controlled by 90A and 190B, the transmitting system and the receiving system may be controlled by one μCPU. Furthermore, it is also possible to improve the processing speed by implementing all the functions of the CTL section in hardware without using the μCPU. In this case, in FIG. 4, the first buffer BF for speed matching (waiting) is abolished, the contents of the header are checked in the cell writing section, and the cell data is directly sent to the second buffers BF-4 to BF-n. You may transfer it.

Next, the detailed configuration of the subscriber line interface 10-1 will be explained with reference to FIG.

The subscriber line interface 10-1 is an ATM switch 3.
a route information deletion port 1201 for deleting the route information 56 attached to the beginning of each cell 51 input from 0 through the reception bus 12a; and an electrical-to-optical converter (E10 converter) 203 for converting the serial data into an optical signal and outputting it to the receiving optical fiber lla.

The subscriber line interface 10-1 also includes an optical-to-electrical converter (0/E converter) for converting an optical cell signal inputted from a subscriber terminal via a transmission optical fiber llb into an electrical signal. ) 204, a serial/parallel conversion circuit 205 for converting the serial signal output from the 0/E converter 204 into 8-bit parallel data, a header separation circuit 206, a header insertion port g207, and a header conversion table. 208.

As already mentioned, each cell transmitted from a subscriber terminal consists of a cell link 52 and an information field 53, as shown in FIG. 5(B). The hex separation circuit 206 separates the header part 52 from the received cell, and converts the VC included in the header part 52 into N (input VCN) 520'a header conversion table/20.
8, the information field 53 is input to the header insertion circuit 207.

The header conversion table 208, as shown in FIG.
6 and header information 52 including the new VCN 520, and by using the VCN 520' output from the header separation circuit 206 as an address, the corresponding record can be output to the header insertion circuit 207. The header insertion circuit 207 adds the route information 56 read from the table 206 and the new header 52 to the beginning of the record information field 53 consisting of,
The data is sent to the ATM switch 30 via the transmission data bus 12b.

Note that the contents of the header conversion table 206 are
0 is set via bus 104. For example, if the input cell is for signal processing (signal channel use), a conversion record with route information that associates the input cell with bus 15 is preset in the address corresponding to the VCN attached to this input cell. The cell after header conversion is outputted to the bus 15 by the ATM switch 30, assembled into a signal frame by the subscriber line signaling device 1, and the contents of the information field thereof are notified to the processor 40. There is.

FIG. 10 shows that the subscriber line signal processing method shown in the first and second embodiments described above is also applied to trunk line signal processing, and the trunk line signal device 2 is installed on the subscriber line side of the ATM switch 30. Show the installed configuration.

The trunk line signaling device 2 may have basically the same structure as the subscriber line signaling device 1 shown in FIG. 1 or 2. Further, the trunk line interface section 20 can also have the same circuit configuration as the subscriber line interface section 10 shown in FIG.

The message (information field) assembled from the signal channel cells input from the subscriber terminal is sent to the processor 4.
Similar to the process notified to 14.0, cells for signal channels transmitted from other ATM switches are sent to optical fibers 14. Trunk line interface 20. A via bus 13
The message is input to the TM switch 30 and is input to the trunk line signal device 2 via the bus 25, where the frame assembly process and layer 2 process are executed, and the message extracted from the received frame is notified to the processor 40. be done.

The processor 40 performs layer 3 processing on signal channel messages received from the subscriber line signaling device 1 or the trunk line signaling device 2. As a result, if it is necessary to transmit a new signaling channel message to another ATM switch, for example in response to the reception of a signaling channel message from the originating subscriber terminal, the above-mentioned message is transmitted to trunk line signaling device 2. issue a transmission request. Trunk line signal bag 2!2
performs layer 2 processing (such as c-frame generation) and frame-to-cell decomposition (segmentation) processing on the message received from the processor 40, and sends the generated cells to the ATM switch 30 via the bus 25. do. These cells are AD in trunk line signaling device 2.
According to the route information 56 added by the P processing section, the bus 1
3-1 to 13-, and delivered to the other party's exchange. Conversely, a message to be transmitted to the local subscriber terminal in response to a message received from the subscriber terminal or exchange on the other party's side (destination) is given from the processor 40 to the subscriber line signaling device 1, and sent to the subscriber line signaling device 1. The line signal device disassembles the cell into cells and connects the ATM switch 30 to the bus °12-1.
~12-j to the subscriber terminal.

In this way, the processor performs call control using the signal channel, and the signal channel messages sent from the processor are used to control the calls to the local subscriber terminal.

Notify the subscriber terminal on the other side of the VCN to be attached to the cell for the information channel. Also, corresponding to these VCNs,
A new conversion record is written to the header conversion table 208 in the subscriber line interface and the trunk line interface, and when information channel cells are input from the subscriber terminal, each input cell is header converted according to the above conversion record, and the ATV The switch 30 allows for distribution to the scheduled route 1-.

In the embodiments shown in FIGS. 1 and 2, when VCNs are managed for each subscriber line, a case may occur where cells with the same VCN are simultaneously input from different subscriber lines. At this time, in a system in which the ADP processing unit 100 is commonly installed in multiple subscriber lines, if cells are identified only by VCH, cells of different subscribers will be mixed together.
Normal reassembly processing cannot be performed. In the present invention, when receiving a cell from a subscriber line, each subscriber line interface unit 10-1 adds route information 56 to the cell, records the subscriber line line number in this part, and
In the P processing unit receiving system, this subscriber line line number and VC
By identifying the cell with N, normal reassembling processing can be realized. In addition, without recording the subscriber line line number, the VCN of the cell is converted into a VCH unique to the VCN used in the subscriber lines up to 1...j at the subscriber line interface section 1o. You may also do so. Furthermore, when DLCI is managed for each subscriber line, a case may occur where different subscribers use the same DLCI at the same time. At this time, a second embodiment (second embodiment) in which the LAPD-LSI is installed commonly for multiple subscriber lines.
According to the method shown in Figure), the same DLC can be sent to different subscribers.
Unable to identify two or more links with I.

In this case, a DL CI conversion table is provided in the ADP processing unit 100, and between the LAPD-LS I 1.01 and the ADP processing unit 100, the DLCI used in the subscriber lines up to 1...j is However, if a unique LCI is used, normal link identification can be performed.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the ATM
By installing the subscriber line signaling device in the exchange on the trunk line side of the ATM switch and installing the ADP processing unit in common to each subscriber line, we have realized a subscriber line signaling device in the same manner as the conventional 15DN exchange. This eliminates the need for cell separation/insertion circuits for each subscriber line, buses for concentrating and distributing lines, and multiplexing/demultiplexing circuits, which are required when This has the effect of reducing

Furthermore, the same effect as described above can be obtained by installing the trunk line signal device on the subscriber line side of the ATM switch and installing the ADP processing unit in common to each trunk line.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention;
FIG. 2 is a system configuration diagram showing a second embodiment of the present invention;
FIG. 3 is a block diagram showing the transmitting system 100A in the ADP processing section 100, FIG. 4 is a block diagram showing the receiving system 100B in the ADP processing section 100, and FIGS.
) is a diagram for explaining frames and self-formatting, FIG. 6 is a diagram showing one example of a specific configuration of the ADP processing section transmission system 100A, and FIG. 7 is a diagram showing one example of a specific configuration of the ADP processing section receiving system 100B. FIG. 8 is a configuration diagram of the subscriber line interface unit 1o, FIG. 9 is a configuration diagram of a header conversion table, FIG. 10 is a system configuration diagram showing another embodiment of the present invention, and FIG. 11 is a diagram showing an example. AT is the conventional subscriber line signal processing method.
FIG. 2 is a diagram showing a configuration diagram of an ATM switch when applied to an M switch. 10... Subscriber line interface section, 20... Trunk line interface section, 3o... ATM switch, 40
... Processor, 1... Subscriber line signaling device, 2...
- Trunk line signal processing device, 100... ADP processing unit, 1
01...LAPD-LSI. (11: Finish'ek"J frame 32nd? Figure 4λ

Claims (1)

[Claims] 1. A switch circuit having a plurality of input terminals and a plurality of output terminals and for determining the direction of each fixed-length packet input from the input terminal, and a signal frame for transmitting and receiving signal frames. a processing unit; receiving the fixed-length packets from the subscriber equipment, assembling a signal frame; transmitting the frame to the signal frame processing unit; receiving the signal frame, assembling the fixed-length packet; In an ATM switch having an adaptation processing unit that transmits fixed-length packets to the subscriber equipment, the adaptation processing unit is installed on the trunk line side of the switch circuit, and the fixed-length packets for signal frames are processed using the switch circuit. An ATM exchange characterized in that it transmits/receives for each subscriber line. 2. A switch circuit having a plurality of input terminals and a plurality of output terminals, for determining the direction of each fixed-length packet inputted from the input terminal, a signal frame processing section for transmitting and receiving signal frames, and other ATMs. The fixed-length packets are received from the exchange, a signal frame is assembled, and the frame is transmitted to the signal frame processing section.The signal frame is also received, the fixed-length packet is assembled, and the fixed-length packet is sent to the ATM In an ATM switch having an adaptation processing unit for sending data to the exchange, the adaptation processing unit is installed on the subscriber line side of the switch circuit, and the fixed length packet for signal frames is sent to each trunk line using the switch circuit. An ATM switch characterized by transmitting/receiving. 3. A switch circuit having a plurality of input terminals and a plurality of output terminals, for determining the direction of each fixed-length packet inputted from the input terminal, and a switch circuit for the subscriber line for transmitting and receiving signal frames for the subscriber line. a signal frame processing section, which receives the fixed length packets from the subscriber equipment, assembles a signal frame, transmits the frame to the subscriber line signal frame processing section, and receives the signal frame and assembles a signal frame; a subscriber line adaptation processing unit that assembles long packets and transmits the fixed length packets to the subscriber equipment; a trunk line signal frame processing unit that transmits and receives trunk line signal frames; A fixed length packet is received, a signal frame is assembled, the frame is transmitted to the trunk line signal frame processing section, a fixed length packet is received, a fixed length packet is assembled, and the fixed length packet is sent to the other ATM. In an ATM switch having a trunk line adaptation processing unit that sends data to the exchange, the subscriber line adaptation processing unit is installed on the trunk line side of the switch circuit, and the trunk line adaptation processing unit is installed on the trunk line side of the switch circuit. By installing it on the line side, fixed-length packets for signal frames for subscriber lines and trunk lines can be transmitted/received for each subscriber line and trunk line using the same switch circuit. ATM exchange machine. 4. ATM according to claim 1 or 3
1. An ATM switching system characterized in that adaptation processing for a plurality of subscriber lines is executed by fewer adaptation processing units than the number of subscriber lines. 5. ATM according to claim 2 or 3
1. An ATM switching system characterized in that adaptation processing for a plurality of trunk lines is executed by fewer adaptation processing units than the number of trunk lines. 6. ATM according to claim 1 or 3
An ATM exchange characterized in that a subscriber signal frame processing section is provided for each subscriber line. 7. ATM according to claim 1 or 3
1. An ATM exchange characterized in that a subscriber line signal frame processing section is provided commonly to each subscriber line. 8. ATM according to claim 2 or 3
1. An ATM switch, characterized in that a trunk line signal frame processing section is provided for each trunk line. 9. ATM according to claim 2 or 3
1. An ATM switch, characterized in that a trunk line signal frame processing section is provided commonly for each trunk line. 10. The ATM switch according to claim 1, 2, or 3, wherein the fixed length packet input from the input terminal and the fixed length packet assembled by the adaptation processing section include the An ATM switch characterized in that it collects/distributes fixed length packets for signal frames by adding an information section for routing within the switch. 11. The ATM switch according to claim 10, which records the line number of a subscriber line or trunk line in the routing information section of the fixed-length packet input from the input terminal, and performs signal processing. An ATM switching system characterized in that, in the section, a frame assembly process is performed for each signal link from the line number recorded in the routing information section and the identification number in the fixed length packet. 12. The ATM switch according to claim 1, 2, or 3, wherein the identification number in the fixed-length packet input from the input terminal is a unique identification number within the ATM switch. A characterized in that frame assembly processing is performed for each signal link by exchanging the
TM switch. 13. AT according to claim 7 or 9
A switching system characterized in that the adaptation processing unit performs link identification of a signal channel by exchanging a link identification number in a signal frame with a unique link identification number in the frame processing unit.
TM switch.