JPH08331155A - Atm exchange - Google Patents

Abstract

PURPOSE: To reduce an amt. of hardware by installing a subscriber line signal device on the side of the repeating line of an ATM switch and installing an ADP processing part in common with each subscriber. CONSTITUTION: By installing a subscriber line signal device 1 including an ADP processing part 100 on the side of the repeating line of an ATM switch 30, the cell of a signal channel is collected and distributed by using the ATM switch 30, and the adaptation processing common to each subscriber line is performed. For the signal from the repeating line, a repeating line signal device including the ADP processing part 100 is installed on the side of the subscriber line of the ATM switch 30. By arranging the ADP processing part 100 on the rearside of the ATM switch and collecting/distributing the cell of the signal channel by the ATM switch, the separation/insertion circuit of the cell and the multiplex/demultiplex circuit of the cell become unnecessary. By executing the common adaptation processing, an amt. of hardware required for the adaptation processing can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch, and more particularly to an asynchronous transfer mode (Asynchronous Transfer Mode).
Made: hereinafter referred to as ATM), an ATM switch for exchanging fixed-length packets.

[0002]

2. Description of the Related Art ISDN (Integrated Services Digita)
l Network) has two types of channels: an information channel (B channel) used to transfer information transmitted and received between users and a signal channel (D channel) used to transfer control signals for setting a communication path. . As a configuration for processing the signal channel in the ISDN exchange, for example,
As shown in FIG. 12 of the Institute of Electronics, Information and Communication Engineers Technical Research Report SE87-85 "Signal processing method of I interface switch", or as disclosed in JP-A-62-131652, signal channels from a plurality of subscriber lines. And the information channel are separated by the input interface of each exchange, only the signal channel is once separately multiplexed and guided to the signal processing device without passing through the switch, and then the signal channel layer 2 (LAPD: Link Access Procedure on the D
A configuration is known in which each of the -channel) processing and the layer 3 (call control) processing is performed.

Meanwhile, the International Telegraph and Telephone Consultative Committee (CCITT) is currently studying a broadband ISDN as a next-generation ISDN. Broadband ISDN is
High speed for subscribers (eg 150 Mbit / s)
It is intended to provide a signal exchange service having a line speed, and CCITT Recommendation I. According to the 121st draft, the ATM switching system is cited as a promising realization means of the above-mentioned wideband ISDN. This ATM switching system is a system for transmitting and receiving all data including signals and information in fixed length packets called "cells". For example, as shown in FIG. 5 (A), when the subscriber terminal transmits the signal frame 50 to the exchange, the frame 50 is once disassembled into fixed length cells 51A to 51N (this process is called segmentation). ), And sends this cell to the signaling device provided on the exchange side via the subscriber line. On the exchange side, the signal frame 50 is reproduced from the received cells 51A to 51N (this processing is referred to as reassembly), and then the signal processing is executed. On the contrary, when the exchange side transmits the signal frame to the subscriber terminal, the exchange side performs the segmenting and the subscriber terminal performs the reassembly process. This segmenting / reassembly process is based on CCITT Recommendation I.S. 121
In the draft, it is positioned as the function of the adaptation layer, and hereinafter, the processing unit of the adaptation layer including the segmenting / reassembly process will be referred to as “ADP processing unit”.

The above-mentioned ATM switch is replaced with a conventional ISDN.
The system configuration and signal processing when it is realized by the same configuration as the exchange will be described with reference to FIG. In the figure, 1
1 (11-1 to 11-j) is an optical fiber having a transmission rate of about 150 Mbit / s, 10 (10-1 to 10-j), for example.
j) Subscriber line interface section for exchanging optical / electrical signals, 30 is an ATM switch for exchanging cells, 12
(12-1 to 12-j) are 8-bit buses.

A cell separation / insertion circuit 16 (16-1) is provided between the subscriber line interface section 10 and the ATM switch 30.
16-j) are installed, and in the receiving system (the cell from the subscriber line interface unit 10 to the ATM switch 30),
Only the cells of the signal channel are separated and taken out, and the transmission system (from the ATM switch 30 to the subscriber line interface unit 1
In the cell toward 0), the cell of the signal channel is inserted. Cell data from each cell demultiplexing / inserting circuit 16 is multiplexed by a demultiplexing / demultiplexing circuit (MUX) 17 and connected to the subscriber line signaling device 1 via a bus 19. The subscriber line signaling device 1 includes a circuit (MUX) 18 that multiplexes / demultiplexes cell data for each subscriber line and the aforementioned segmenting / demultiplexing circuit.
ADP processing unit 100 (10 for performing the reassembly process
0-1 to 101-j) and the LAPD LSI 101 (101-1 to 101-101) that performs the layer 2 processing of the signal channel.
-J) and the bus 103.

[0006]

However, according to the above method, the cell separation / insertion circuit 16 is required for each subscriber line in order to concentrate only the cells of the signal channel, and the MUX 17 and those A bus is required to connect Further, even in the subscriber line signaling device 1, the MU
X18 and an ADP processing unit for each subscriber line are required. Therefore, as the speed and bandwidth of the exchange system as described above are increased and the capacity is increased, these configurations become large in scale, which is not desirable in terms of economical efficiency and reliability. A simpler configuration ensures reliable high-speed signal transmission. A structure capable of processing is required.

An object of the present invention is to provide an ATM switch having a subscriber line signaling device or a trunk signaling device having a simpler structure. Specifically, while providing a signaling device having a configuration suitable for an ATM switch with a simple configuration and efficiently arranging these signaling devices in an ATM switching system, the cost and reliability are excellent, and high-speed switching is possible. An object of the present invention is to provide a switching system having a signal processing capability suitable for the system. Further, when handling an ATM signal, a conversion rule between a signal frame and a fixed length cell is determined so that the signal processing device can easily process the signal, and a cell having a configuration suitable for signal processing is provided.

[0008]

In order to achieve the above object, according to the present invention, a subscriber line signaling device including an ADP processing section is installed on the trunk side of an ATM switch.
The TM switch is used to collect and distribute the cells of the signal channel, and the adaptation process is performed commonly to each subscriber line. Further, for signals from the trunk line, a trunk line signal device including an ADP processing unit was installed on the subscriber line side of the ATM switch. Since both configurations collect and distribute signals via switches, the subscriber line signaling device and the trunk line signaling device may be shared.

According to the above configuration, the ADP processing section is arranged on the rear side of the ATM switch, and the cells of the signal channel are collected / distributed by using the ATM switch, thereby separating / inserting the cells. No circuitry and no cell multiplexing / demultiplexing circuitry is required. Further, since the adaptation process is executed commonly for each subscriber line or for each trunk line, the amount of hardware required for the adaptation process can be reduced.

As a similar system for connecting the subscriber line signal device and the subscriber terminal via a switch, for example, there is a system described in Japanese Patent Laid-Open No. 63-78657. It is not taken into consideration, and a circuit such as a subscriber line scanning unit is required to detect a signal frame. A signal device including the above ADP processing unit is arranged at the rear side of an ATM switch to provide a signal channel. The configuration operation is different from that of the signal processing apparatus of the present invention, which performs the adaptation processing only by performing the cell collection / distribution of.

Further, according to the present invention, a variable length information is divided into information chunks, and as a fixed length ATM cell for transmission / reception in a communication network of an asynchronous transfer mode, a first header including an identifier relating to a destination of information. And the length of the information chunk, and an order identifier for identifying either the first information chunk containing the first bit of the information or the final information chunk containing the last bit of the information or the intermediate information chunk other than the first information chunk and the final information chunk. An ATM cell composed of a second header containing the information and an information section is used, and the variable length information and the cell can be assembled / disassembled based on the order identifier of the second header. Furthermore, an adaptation circuit having a structure for assembling / disassembling a packet each time this cell is transmitted / received is provided, and this circuit is provided with a simple structure of a counter, a buffer, a header addition / conversion table, and a control circuit for controlling these, Adaptation processing can be easily and surely performed using the information of the second header.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an ATM exchange according to the present invention will be described below with reference to the drawings. 1 and 2
FIG. 1 is a system configuration diagram showing an embodiment of the present invention, respectively, an ADP processing unit 100 that performs adaptation processing such as segmentation and reassembly, and a LAPD / LSI that performs layer 2 protocol processing of a signal channel.
The subscriber line signaling device 1 including 101 (101-1 to 101-l) is connected to the trunk line side of the ATM switch 30 via the bus 15. In addition, the subscriber line signaling device 1 receives the layer 3 of the signaling channel via the bus 103.
Protocol processing, updating of the header conversion table described later, initial value setting of the ATM switch 30, LAPD
It is connected to a processor 40 that controls the LSI 101 and the like. The memory 41 is a memory used as a program storage area and a work area executed by the processor 40. Subscriber line 11 (11-1 to 11-
j) is an optical fiber or the like having a transmission rate of about 150 Mbit / s, for example, and is a trunk line 14 (14-1 to 14-).
k) is, for example, 150 Mbit / s or 600 Mbit / s
It is an optical fiber having a transmission speed of about s. Further, the signal lines 12 (12-1 to 12-j), 13 (13-1 to 13)
-K) and 15 are buses each having a width of, for example, 5 bits, and the subscriber line interface unit 10 and the trunk line interface unit 20 respectively perform optical / electrical signal conversion and a route information unit for individual cells. Add / delete etc. In the figure, signal lines 11-1 to 14-k
, Each shown as a single line, each consisting of a pair of input and output lines.

Reference numeral 30 is an ATM switch for exchanging fixed-length cells. For example, an ATM switch adopting the method described in Technical Report IN88-38 "A proposal of ATM switching architecture" of the Institute of Electronics, Information and Communication Engineers Information Network Research Group is adopted. it can. If the number of input / output buses of the ATM switch is 32 × 32, then j = 32 and k = 31 in the figure. Here, if it is desired to secure a 32 × 32 input / output bus for exchanging cells of the information channel, the number of input / output buses of the ATM switch should be 32 × 33, 32 × 34, etc. Alternatively, the two buses may be dedicated buses for signal channels.

In the embodiment of FIG. 1, the LAPD / LSI is installed for each subscriber line (j = 1), but the number of LAPD / LSI can be reduced by setting j> l.
By setting j <l, a backup LAPD in case of failure occurs.
It may be configured to have an LSI. In the embodiment of FIG. 2, the processing of the layer 2 of the signal channel for the plurality of subscriber lines (11-1 to 11-j) is performed by one LAPD / LS.
The method executed by I101 is shown.

FIG. 3 is a block diagram showing the transmission system 100A in the ADP processing section 100, and FIG. 4 is the ADP processing section.
3 is a block diagram showing a receiving system 100B in the processing unit 100. FIG. The CCITT Recommendation I.121 draft has not yet determined the cell format and cell size. Therefore, in the ADP processing of FIGS. 3 and 4 described above,
The cell format shown in FIG. 5 (B) is defined and used in the ATM switching system. Specifically, the cell length of each cell is 36 bytes, and the 4-byte cell header 52
And an information field 53 of 32 bytes. The source and destination terminal numbers required for call control and the transmission data between the terminals are set in the information field 53. The first 12 bits of the cell header 52 are a VCN (Virtual Channel Number) field 520 for cell identification, and a reserve field 521 and an HCS (Header Check Sequence) for cell header abnormality detection.
It shall have a field 522. The information field 53 has a 2-byte ADP header 54 at the beginning. Therefore, the area 55 in which the frame data shown in FIG. 9A can be stored is 30 bytes per cell. Then, in the ADP header 54, a 2-bit cell type area 542 indicating that the cell is one of frame start / frame end / frame middle / 1 cell = 1 frame, and a 1-byte area indicating the effective information length of the information field. 543 and a reserve area 541 are provided.

For example, when the inter-flag frame length of the frame 50 of FIG. 3A is 6 bytes, if this is made into cells (segmenting), the cell type is 1 cell = 1 frame and the effective information length is 6 cells. Becomes Also, the frame length is 4
In the case of 0 bytes, the cell is divided into two cells, that is, a first cell having a cell type of a frame and a valid information length of 30, and a second cell having a cell type of a frame and having a valid information length of 10.

The route information section 56 attached to the head of the cell in FIG. 5B is added only in the ATM switch, and the above-mentioned route information section on the subscriber line 11 and the trunk line 14 is added. Each cell is transmitted in a format in which 56 is deleted. This route information section records information indicating to which outgoing line the cell should be transmitted when the ATM switch 30 exchanges the cell, the subscriber line number, the trunk line number, and the like. It is used for In the ATM exchange of the present invention, the interface unit 1
0 and 20 and the ADP processing unit 100 add the route information unit 56, so that the cell for performing signal processing between the signal processing device and the subscriber line or the relay line is surely collected and distributed even through the switch 30. It is configured to be.

Next, details of the transmission system 100A of the ADP processing section will be described with reference to FIG. The transmission line selection unit 110a uses the transmission data (TxD) and the transmission clock (TxD).
xC), an echo (E), which is one signal line 102.
a (102a-1 to 102a-1) corresponds to L
It is connected to the APD-LSI 101 (101-1 to 101-l) and has a function of performing contention control when frames are simultaneously transmitted from a plurality of LAPDs and extracting only a frame of a specific line. As the procedure of this competition control,
The D channel access procedure described in CCITT Recommendation I.430 can be used. As a result of the contention control, the selected line number is notified to the control unit CTL 190A, and the transmission data is sent to the frame detection unit 112. The transmission line selection unit 110a is a line required only in the first embodiment (FIG. 1) of the present invention.

The frame detection section 112 is a DL of an intra-frame address section of the frame signal shown in FIG.
CI (Data Link Connection Identifier) to CTL1
90A is notified and the FCS (Fr
The data up to the (ame Check Sequence) part is deleted to 0 bits for flag identification, then converted to 8-bit parallel data and sent to the counter part 116. If the data is the last data of the frame, the fact is notified to the counter unit 116 via the Final notification line.

The counter section 116 stores the frame data as
Transfer to the FIFO A120. When 30 bytes of data are transferred to FIFO-A120 and FIFO-A becomes full, or when the last data of the frame is transferred,
The cell identification 542 and the valid information length 543 shown in the ADP header format of FIG. 5B are notified to the CTL 190A,
After that, the data sent from the frame detection unit 112 is transferred to the FIFO / B 121. Even when data is transferred to the FIFO.B, if the FIFO.B is full or the data at the end of the frame is transferred, the counter unit 116 is similar to the case of transferring the data to the FIFO.A. The cell type and effective information length are notified to the CTL 190A, and the subsequent data is transferred to the FIFO / A 120. As described above, the FIFO · A and the FIFO · B are alternately used.

The CTL unit 190A is, for example, μCPU, R
It is composed of OM and RAM, and internally has a DLCI / header correspondence table 191, in which header contents corresponding to each combination of line number and DLCI (from route information 56 to ADP header 54 in FIG. 5B) are stored. Up to 10 bytes) are set from the processor 40 via the bus 103. Upon receiving the notification of the line number and the DLCI, the CTL unit 190A searches the DLCI / header correspondence table 191, and writes the content of the corresponding header in the header register 118.

However, in the second embodiment of the present invention (FIG. 2), the DLCI / header correspondence table 191 is searched, and then the DLCI conversion table 195 is used to actually change the subscriber device from the unique DLCI. To the DLCI to be sent to. After that, when the notification of the cell type and the valid information length is received from the counter unit 116, FIG.
According to the ADP header format 54 of (B), the corresponding register in the header register is rewritten and the selector (SEL) 122 is activated.

The SEL 122 has the header register 11 first.
The data in 8 is transmitted, and then the data in the FIFO · A 120 is transmitted to complete the cell transmission. SEL122
Next, when it is activated by the CTL 190A, the data in the header register 118 is transmitted, and then the FIFO B1
The data in 21 is transmitted to complete the cell transmission. Hereinafter, the SEL 122 alternately transmits the contents of FIFO · A and FIFO · B. In the CTL unit 190A, the process of searching the DLCI / header correspondence table 191 and the process of setting the ADP header in the header register are separately performed, and the data in the header register 118 changes even when the SEL 122 reads them. If this is not done, it is possible to reduce the amount of processing for creating a header associated with cell transmission. For example, when one frame is divided into a plurality of cells and transmitted, the DLCI / header correspondence table search processing is performed only when the cell at the beginning of the frame is transmitted, and for the subsequent cells, only the ADP header section in the header register 118 is used. Is rewritten, it becomes unnecessary to search the DLCI / header correspondence table 191 for each cell.

Next, details of the receiving system 100B of the ADP processing section will be described with reference to FIG. The cell writing unit 124
It is connected to the ATM switch 30 via the reception bus 15b and receives cells of the signal channel from the subscriber unit.
The received cell data is stored in WQ (Wr
ite Address) is transferred to the address indicated by the register. After that, in preparation for the next cell reception, an empty address F
Write data in IFO 130 to address register W
Set to A125.

Reference numeral 126 is a buffer memory (BFM). On the BFM, a first buffer BF of the FIFO format for temporarily receiving and storing cells arriving at a rate of 150 Mbit / s, and then a buffer Second buffers BF-1 to BF-1 of the FIFO format prepared for each combination of the line number and the VCN in the cell header for the assembling process.
F-n. In addition, F on BFM126
Structure of IFO type BF and usage of chain pointer, and WA and RA (Read Address) and free address F
The usage of the IFO is shown in the above-mentioned document "A Proposal of ATM Switching Architecture".

The control unit CTL190B has a first buffer B.
It has a read address register RA192 for F,
Among the contents of the cell of the address indicated by RA, the line number recorded in the route information part and the VCN in the cell header
Then, the cell type in the ADP header is checked, and first, the cell data is transferred to the second buffer BF-i having the combination of the corresponding line number and VCN. in this case,
No data is transferred from memory to memory, CTL19
The transfer process is executed only by rewriting the second buffer address table 193 in 0B and the buffer chain pointer. If the cell type in the ADP header is checked and reception of a cell for one frame is completed, the start address of the buffer storing the start cell of the frame and the line number are stored in the transfer order storage F.
It is stored in the IFO 194. The CTL 190B uses the parallel-to-serial converter (P
/ S section) 128 is started, and at the same time, the receiving line selecting section 11
Specify the outgoing line number for 0b. In the second embodiment (FIG. 2) of the present invention, when the P / S unit 128 is activated, the DLCI conversion table 195 is used to obtain a unique DLCI from the DLCI from the subscriber unit, and the unique DLCI is obtained. The DCLI of the same time to the P / S unit at the same time. P
Upon activation from the CTL 190B, the / S unit 128 reads the data at the specified address, converts the data other than the header to serial data, inserts "0", adds the cell type flag, and then selects this data as the receiving line. Part 110b
Send to. It should be noted that in the second embodiment of the present invention, conversion into a unique DLCI is also performed.

The reception line selection unit 110b uses the signal lines 102b (102b-1 to 102b-1) each including two sets of reception data (RxD) and reception clock (RxC) to form the LAPD LSI 101 (101-1 to 101-1). 101-
l) and has a function of sending data only to the signal line of the line number designated by the CTL 190B. The receiving line selecting unit 110b is the transmitting line selecting unit 1 shown in FIG.
Like 10a, it is only needed in the configuration of the first embodiment of the invention (FIG. 1) and not in the configuration of the second embodiment of the invention.

FIGS. 6 and 7 show a transmission system 100 of an ADP processing section constructed by applying a microprocessor to the control CTL.
FIG. 5 is a diagram showing an example of a specific structure of A and a receiving system 100B, and these are functionally the same as the circuits described in FIGS. 3 and 4. The transmission system 100A shown in FIG. 6 is an interface 3 for connecting to the bus 103 on the processor 40 side.
01, a bus arbiter 302, a microprocessor 303 constituting the CTL 190A, and a program memory 30.
4 and the RAM 305, and these elements, the transmission line selector 110a, the frame detection unit 112, the counter unit 116, the header register 118, which have already been described in FIG.
The selector 122 is configured to be interconnected by the internal bus 108. The bus arbiter 302 is for adjusting and controlling the use request of the bus 108 from the microprocessor 304 and the external processor 40 output via the interface circuit 301. In the RAM 305, a DLCI / header table 191, a DLCI conversion table 195, and a work area 196 used by the microprocessor for ADP processing are formed.

The transmission circuit selector 110A has a line number register 311. When the selected line number is set in the register 311, the transmission line selector interrupts the microprocessor 303, and the microprocessor 303 stores the register number. The contents are read via the internal bus 108. The DLCI register 312 of the frame detection unit 112, the valid information length register 313 and the cell type register 314 of the counter unit 116 are also read by the microprocessor 303 by the same method.

Similarly to the transmission system, the reception system 110B shown in FIG. 7 has a configuration in which the respective elements shown in FIG. 4 are interconnected by the internal bus 108, and the reception cell to the buffer memory 126 by the cell writing unit 124 is received. Is written via the upper internal bus 108, and data transfer from the buffer area BF to the second buffer areas BF-1 to BF-n and data transfer from the second buffer area to the P / S conversion unit 128 are also performed. ,
The microprocessor 303 is designed to perform the above-mentioned internal bus.

In the above embodiment, the ADP processing unit 1 is constituted by the CTL units 190A and 190B using the μCPU.
However, the transmission system and the reception system may be controlled by one μCPU. Also,
It is also possible to improve the processing speed by using all the functions of the CTL unit as hardware without using the μCPU.
In this case, in FIG. 4, the first buffer BF for speed matching (waiting) is eliminated, the content of the header is checked in the cell writing unit, and the second buffers BF-1 to BF-1 are directly connected.
Cell data may be transferred to F-n.

Next, the detailed configuration of the subscriber line interface 10 will be described with reference to FIG. The subscriber line interface 10 deletes the route information 56 which is input from the ATM switch 30 via the reception bus 12a and is attached to the head of each cell 51.
A serial-to-serial conversion circuit 202 for serially outputting the cell data from which the route information has been deleted bit by bit, and an electric circuit for converting the serial data into an optical signal and outputting the optical signal to the receiving optical fiber 11a. And an optical converter (E / O converter) 203. Further, the subscriber line interface 10 is provided with an optical fiber 11b for transmission from the subscriber terminal.
An optical-electrical converter (O / E converter) 204 for converting an optical cell signal input via the optical signal into an electric signal, and an O / E converter
Serial-parallel conversion circuit 205 for converting the serial signal output from the converter 204 into parallel data in units of 8 hits
, Header separation circuit 206, and header insertion circuit 207
And a header conversion table 208.

As described above, each cell transmitted from the subscriber terminal has a cell header 52 as shown in FIG. 5 (B).
And an information field 53. The header separation circuit 206 separates the header portion 52 from the received cell,
VCN (input VCN) 520 'included in the header section 52
To the header conversion table 208 and the information field 53 to the header insertion circuit 207.

In the header conversion table 208, as shown in FIG. 9, the header information 5 including the route information 56 and the new VCN 520 at the address corresponding to the value of the input VCN 520 '.
2 is stored, and the VCN 520 ′ output from the header separation circuit 206 is used as an address.
A record corresponding to this can be output to the header insertion circuit 207. The header insertion circuit 207 receives the route information 56 read from the table 206 and the new header 52.
A record consisting of and is added to the beginning of the information field 53, and the ATM switch 30 is connected via the transmission data bus 12b.
Send to

The contents of the header conversion table 206 are as follows.
It is set by the processor 40 via the bus 104. For example, when the input cell is for signal processing (for signal channel),
A conversion record having route information associating the input cell with the bus 15 is preset in the address corresponding to the VCN attached to the input cell, and the cell of the header converter is transferred to the bus 15 by the ATM switch 30. It is output and assembled into a signal frame by the subscriber line signaling device 1, of which the contents of the information field are processed by the processor 40.
Will be notified.

In FIG. 10, the subscriber line signal processing system shown in the first and second embodiments described above is also applied to the trunk line signal processing, and the trunk line signal device 2 is used as a subscriber line of the ATM switch 30. The configuration installed on the side is shown. The trunk signal device 2 is
It may have the same basic structure as the subscriber line signaling device 1 shown in FIG. 1 or 2. In addition, the trunk line interface unit 20
Can have the same circuit configuration as the subscriber line interface unit 10 shown in FIG.

Message (information field) assembled from cells for signaling channels input from subscriber terminals
The cell for the signal channel transmitted from another ATM switch is input to the ATM switch 30 via the optical fiber 14, the trunk line interface 20, and the bus 13 in the same manner as the process in which the processor 40 is notified to the processor 40. Bus 25
Is input to the trunk line signal device 2, where the frame assembly process and the layer 2 process are executed, and the processor 40 is notified of the message extracted from the received frame.

The processor 40 performs layer 3 processing on the signaling channel message received from the subscriber line signaling device 1 or the trunk signaling device 2. As a result, if it is necessary to send a new signaling channel message to another ATM switch in response to the receipt of the signaling channel message from the calling subscriber terminal, for example, the message is sent to the trunk signaling device 2. Issue a request to send. The trunk signal device 2 performs layer 2 processing (frame generation processing, etc.) and frame-to-cell disassembly (segmentation) processing on the message received from the processor 40, and the generated cell is transmitted via the bus 25 to the ATM. It is sent to the switch 30. These cells, according to the route information 56 added by the ADP processing unit in the trunk line signal device 2,
It is output to any of the buses 13-1 to 13-k and delivered to the partner exchange. On the contrary, the message to be transmitted to the subscriber terminal on the local station side in response to the message received from the subscriber terminal on the partner side (destination) or the exchange is given from the processor 40 to the subscriber line signaling device 1, It is disassembled into cells by a line signal device and is transferred from the ATM switch 30 to the bus 12-
It is delivered to the subscriber terminal via any of 1 to 12j.

In this manner, the processor performs call control by the signal channel, and the signal channel message sent from the processor determines the VCN to be attached to the information channel cell to the subscriber terminal of the own station and the subscriber terminal of the partner station. Notice. Corresponding to these VCNs, a new conversion record is added to the header conversion table 208 in the subscriber line interface and the trunk line interface, and when an information channel cell is input from the subscriber terminal, each input cell is The header is converted by the above conversion record, and AT
The M switch 30 allows the route to be distributed to the planned route.

In the embodiment shown in FIGS. 1 and 2, when the VCN is managed for each subscriber line, a case may occur in which cells having the same VCN are simultaneously input from different subscriber lines. At this time, in the method in which the ADP processing unit 100 is commonly set for a plurality of subscriber lines, if cells are identified only by the VCN, cells of different subscribers are mixed and normal reassembly processing cannot be executed. .
In the present invention, when receiving a cell from a subscriber line, each subscriber line interface unit 10-i adds route information 56 to the cell, records the subscriber line number in this portion, and further receives the ADP processing unit reception. In the system, a normal reassembly process can be realized by identifying the cell by this subscriber line number and VCN. It should be noted that the subscriber line interface unit 10 converts the VCN of the cell into a VCN unique to the VCNs used in the subscriber lines up to 1 ... j without recording the subscriber line number. You may Furthermore, when managing the DLCI for each subscriber line, a case may occur in which different subscribers simultaneously use the same DLCI. At this time, the LAPD LSI
According to the method of the second embodiment (FIG. 2) in which a plurality of subscriber lines are commonly installed, the same D is applied to different subscribers.
Unable to identify more than one link with LCI. In this case, a DLCI conversion table is provided in the ADP processing unit 100, and the LAPD / LSI 101 and the ADP processing unit 1 are provided.
Between 00 and D, which is used by subscriber lines up to 1 ... j
If a unique DLCI is used for LCI, normal link identification can be performed.

[0041]

As is clear from the above description, according to the present invention, the subscriber line signaling device in the ATM switch can be used as an AT.
By installing it on the trunk side of the M switch and installing the ADP processing unit for each subscriber line in common, a subscriber line required when implementing a subscriber line signaling device in the same manner as a conventional ISDN exchange A cell separation / insertion circuit for each, a bus for concentrating and distributing, and a multiplexing / separation circuit can be omitted.
Since the number of P processing units can be reduced, the amount of hardware can be reduced.

Also, with respect to the trunk line signal device, by installing this on the subscriber line side of the ATM switch, the same effect as described above can be obtained.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a system configuration diagram showing a second embodiment of the present invention.

3 is a block diagram showing a transmission system 100A in an ADP processing unit 100. FIG.

4 is a block diagram showing a receiving system 100B in the ADP processing unit 100. FIG.

FIG. 5 is a diagram for explaining a frame and a cell format.

FIG. 6 is a specific configuration 1 of an ADP processing unit transmission system 100A.
The figure which shows an example.

FIG. 7 is a specific configuration 1 of an ADP processing unit reception system 100B.
The figure which shows an example.

FIG. 8 is a configuration diagram of a subscriber line interface unit 10.

FIG. 9 is a configuration diagram of a header conversion table.

FIG. 10 is a system configuration diagram showing another embodiment of the present invention.

FIG. 11 is a diagram showing a configuration diagram of an ATM exchange when the conventional subscriber line signal processing system is applied to the ATM exchange.

[Explanation of symbols]

1 ... Subscriber line signal device, 2 ... Trunk line signal processing device, 10 ... Subscriber line interface unit,
20 ... Trunk line interface section, 30 ... ATM switch, 40 ... Processor, 100 ...
ADP processing unit, 101 ... LAPD
LSI.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinobu Gohara 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Company Hitachi Ltd. Totsuka Plant

Claims (3)

[Claims] 1. An ATM switch which outputs a fixed length cell input from a plurality of input lines to any one of a plurality of output lines according to routing information added to the cell, wherein the input line and the output line are accommodated. An ATM switch having a line interface for transmitting and receiving the cell, and a plurality of input terminals and output terminals connected to the line interface, and for exchanging the transmitted and received cell between the input terminal and the output terminal, A signal processing device connected to any one of the input line and the output line of the plurality of input lines and the output line via the ATM switch; and a control device for controlling the ATM switch, wherein the ATM switch is A control cell including control information of an exchange is provided with the signal processing device and an input line of any of the plurality of input lines and output lines. The configuration is such that data is transmitted and received between the signal processing device, and the signal processing device includes an adaptation processing unit that performs conversion between the control cell and a frame signal, a frame signal processing unit that performs protocol processing of the frame signal, and the frame signal in the frame. An ATM exchange comprising a circuit for transmitting and receiving between a signal processing unit and a control device. 2. The adaptation processing section is provided for the AT.
First storage means for receiving and storing cells from the M switch, processing means for processing a header added to the cells, and the plurality of cells stored in the first storage means for the frame processing section. A cell decomposing means comprising: a second accumulating means for accumulating as a frame signal, and a means for reading the second accumulating means by the output of the processing means and transmitting a frame signal to the frame processing section. Characteristic ATM switch. 3. The adaptation processing unit detects a frame signal from the frame processing unit, a storage unit for storing the frame signal up to a predetermined length, and a completion of storage in the storage unit. The cell assembling means comprising: counting means and means for transmitting to the ATM switch as a cell in which a signal of the accumulating means is added with a predetermined header by the output of the counting means. ATM switch.