JPH02138630A - Microprocessor controller - Google Patents

Abstract

PURPOSE:To automatically dissolve the non-interchangeability by securing such a constitution where a microprocessor having the next highest computing process ability functions to continue the due process when an unprocessable interruption is occurred during the working of a microprocessor having the highest computing process ability. CONSTITUTION:A switch means 4 gives the preference to one of processors 8 and 14 that has the higher computing ability. When an unprocessable interruption is occurred during the working of the microprocessor having the higher computing ability, the other microprocessor functions to continue the arithmetic operation. When the 2nd microprocessor 14 executes a 1st instruction, a switch signal is outputted to the means 4 and the 1st microprocessor 8 works with the switch signal. Thus all registers of the microprocessor 14 are set, and all registers and return addresses are outputted after execution of the 1st instruction. Thus the microprocessor 14 reads all registers and return addresses, and starts the process at an instruction next to the 1st one. As a result, the non- interchangeability is automatically dissolved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to, for example, a microprocessor control device that switches between compatible microprocessors using object code, and particularly relates to control when a special interrupt occurs. be.

[Prior Art] Fig. 6 is a schematic configuration diagram of a conventional microprocessor control device, in which (1) is a memory, (2) is an input/output device, (4) is a changeover switch, and (8) is an 80286
CPU, (14) is 8086 CPU. 7th
The figure is a diagram explaining the flow of instructions. This will be explained below using FIGS. 6 and 7.

Conventionally, for example, the 8086 CPU (8) was compatible with the 80286 CPU (8) in object code.
4) When a special interrupt occurs, the existing software developed for A special interrupt processing routine (25) is entered, and upon completion of this routine, the return address (28) is set as the instruction 62.

In addition, in the 80286 CPU (8), if the instruction 61 occurs, even if the special interrupt routine (25) ends,
Its return address (26) is set to instruction 61.

Now, the 80286 CPU (8) again executes instruction 6
1, it loops and the next program cannot be executed, and the 8086 CPU (14) does not loop and executes from the next instruction, each of which has different operations.

To explain the above specifically, the 8086 CPU (14) is compatible with the 80286 CPU (8) in terms of object code, but the method of generating a return address for divide-by-zero interrupt processing is different.

Therefore, when a divide-by-zero interrupt occurs, incompatibility occurs because the interrupt processing return address is different. For example, 80286 CPU (8) and 8086 C
If P U (14) is operating at the same time, in the command DIV, DXS BX, if it is BX-0, 80
86 CPU (14), 80286 CPU (
8) Both generate a divide-by-zero interrupt, but the return address from the processing routine is 80286 CPU (8
) refers to the instruction that caused the interrupt, but 8086
The CPU (14) indicates the instruction following the instruction that caused the interrupt. If the interrupt processing routine returns with BX-0, 80286 CPU (
8), a divide-by-zero interrupt occurs again and the program loops. However, in the 8086 CPU (14), the return address from the processing routine points to the next instruction after the instruction that generated the interrupt, so subsequent processing is executed. This will cause incompatibilities such as
To run the program, reset the corresponding CPU again using the manual digital switch (6), and
The program was executed again after switching from 6 CPU (8) to 8086 CPU (14).

[Problems to be Solved by the Invention] Even if the conventional microprocessors described above are compatible in object code, they handle each special interrupt differently, resulting in loops or not accepting the processing. CPU that can process
In order to do this, there was a problem in that it had to be reset using a manual digital switch or the like.

This invention was made to solve such problems, for example, 80286 CPU (8) and 8086
When a main program is executed using a CPU (14) microprocessor, even if a special interrupt occurs with instruction 61 in the 80286 CPU microprocessor, the CPU that can process the interrupt is automatically transferred to the CPU that can process the interrupt using the interrupt processing routine. To provide a control device for a microprocessor that can switch over to execute special interrupt processing and continue the program from the next instruction when the processing is completed.

Furthermore, when there are multiple microprocessors, a microprocessor capable of special interrupt processing is stored in the storage means, and when a special interrupt occurs, the switching means selects the corresponding microprocessor, and the corresponding microprocessor executes the processing. When the program is finished, the switching means operates the original microprocessor to continue the main program.

Another object of the present invention is to provide a microprocessor control device that sequentially operates microprocessors in order to search for a microprocessor capable of special interrupt processing without storing microprocessors capable of special interrupt processing in a storage means.

[Means for Solving the Problems] A microprocessor control device according to the present invention includes a plurality of microprocessors that are compatible with each other in object code and have different arithmetic capabilities, and a microprocessor that has excellent arithmetic capabilities. Prioritizes the operation of the microprocessor in
If an interrupt that cannot be processed occurs in an operating microprocessor, the microprocessor is capable of handling the interrupt and switches to the next microprocessor with arithmetic capability to perform the arithmetic operation.

Further, when a first instruction is executed, a microprocessor that generates a special interrupt whose return address for the interrupt processing specifies the next address of the first instruction, and a second microprocessor that is activated by a switching signal and Set all the registers of the microprocessor to that register, and
a first microprocessor that outputs all registers and return addresses after executing an instruction; and a first microprocessor that is compatible in object code with the first microprocessor; After outputting a switching signal to execute the first instruction, a second microprocessor reads all registers and return addresses of the first microprocessor and executes processing from the instruction following the first instruction. It is equipped with a microprocessor. In addition, a plurality of microprocessors are compatible with each other in object code, have different computing capabilities, and have a predetermined operating order, and each time an unprocessable interrupt occurs, the microprocessor is and switching means for operating the microprocessor.

[Operations] In this invention, if the switching means gives priority to the operation of a microprocessor with superior arithmetic ability among a plurality of microprocessors, if an interrupt that cannot be processed occurs while that microprocessor is operating, the processing will be interrupted. A microprocessor capable of performing calculations and having calculation capability is then used to perform calculation operations.

Furthermore, when the second processor executes the first instruction, a switching signal is output to the switching means, and when the first microcomputer is activated by the switching signal, all registers of the second microprocessor are changed to that register. set,
Execute the first instruction to output all registers and return addresses.

Then, the second microprocessor reads all registers and return addresses and executes processing from the instruction following the first instruction.

Furthermore, when the switching means operates one of the plurality of microprocessors having a predetermined operation order,
Whenever an unprocessable interrupt occurs, the corresponding microprocessor is operated based on a predetermined operation order.

C Embodiment] FIG. 1 is a schematic configuration diagram showing an embodiment of the first invention, in which (1) is a memory, (2) is an input/output device (hereinafter referred to as I10), and (3) is a memory. (1) is an inverter that inputs the selector signal (3) and converts it into an inverted signal; (7) is the selector signal (hereinafter referred to as the selector signal);
3) and the reset terminal of the 80286 CPU (described later), (8) is the 80286 CPU, and (9) is the 80286
Address bus and data bus output from cPU (8), (11) is output from inverter (4) and 8028
6 CPU (8) AND that inputs the output address bus and data bus and outputs a HIGH signal (hereinafter referred to as 1) only when both are input.
, (13) inputs the output of the inverter (4), and the reset terminal of the 8o86 CPU (described later), (14) is the 8086
CPU.

(15) Address bus and data bus output from the 8086 CPU, (17) inputs the output of the inverter (4) and the address bus and data bus output from the 8086 CPU (14). AND that outputs a signal of 1 only when there is an input, (20)
is an output terminal connecting the outputs of A N D (11) and A N D (14).

A microprocessor system configured as described above.

The control device can, for example, be controlled by software.
When U (14) is operated and the select signal (3) is set to 0, the reset terminal (7) of the 80286 CPU (8) becomes 0. Here, 80286 CPU (8
) is in a reset state, and when the reset terminal (7) becomes 0, the reset state is canceled and the device enters an operating state.

In addition, the select signal (3) is inverted to 1 by the inverter (4), and A N D (11) and 8086C
It is output to the reset terminal of PU (14). A N
D (11) is the output of inverter (4) and 80286
When the address bus and data bus output from the CPU (8) are input, an address bus and a data bus (12) whose values are 1 only in the range where both inputs are 1 are output from the output terminal (20).

Furthermore, the output of the inverter (4) is also output to the reset terminal (13) of the 8086CPU, and the 8086C
P U (14) enters the reset state when the reset terminal (13) inputs a select signal of 1, so 80
Contrary to the 286 CPU (8), the 8086 CPU (14) address bus and data bus (15) are not output to the A N D (17) because it is not in an operating state. Therefore, A N D (17) is the input of the CPU select signal (3) and the input of the 8086 CPU (1
Since the address bus and data bus (15) in 4) are 0, there is no output from A N D (17).

Next, when the CPU select signal (3) is 1, 80
The reset terminal (7) of the 286 CPU becomes 1, and the 802
86 CPU (8) enters the reset state. Therefore, the address bus and data bus (9) are not output from the 80286 CPU (8). Also, CPU
When the select signal (3) is 1, the inverter (4)
Since the output of is inverted and is O, both signals input to AND (11) are 0, so 80286 CP
The address bus and data bus of U (8) are not output.

In addition, the reset terminal (13) of the 8086 CPU becomes 0, and the 8086 CPU (14) is released from reset and becomes operational, and the address bus and data bus become A.
It is output to N D (17). A N D (17)
Since both inputs are 1, 8 086 CPU (14
) address bus and data bus (15) to the output terminal (
20).

In the above example, the microprocessors are 8086 CPU and 80
Although the description has been made using the H.286 CPU, it may be a control device that has functions equivalent to a microprocessor that is configured from a part of the functions of a compatible CPU or microprocessor using other object codes.

FIGS. 2(a) and 2(b) are flowcharts explaining the first invention.

The first invention will be explained in detail below using FIGS. 1 and 2. In this explanation, all internal interrupts are treated as special interrupts.

80286 CPU (8) executes a division instruction (hereinafter instruction 6)
1), if the quotient of the operation result exceeds the maximum value allowed by the instruction, the 80286 CPU
(8) determines that an O division side input has occurred based on the flag, and forcibly reads the zero division interrupt vector in the reserved memory area, starting from address 00000 (H) to 00003 (H).
Control is transferred to the address set in (S201).

At this time, the flag register, code segment (hereinafter referred to as C8) and instruction pointer (hereinafter referred to as IP
) are respectively saved in the stack area of memory (1), and the interleaved enable flag (hereinafter referred to as IF) and trap flag (hereinafter referred to as TF) are cleared. Next, if commercially available application software is developed for the 80286 CPU (14), there is no need to execute the process of the present invention.
Determine whether to execute special interrupt processing (3203)
.

Here, if there is no need to execute special interrupt processing, an interlaced return is made to execute instruction 61 (S20
4).

Next, from 80286 (14) to 8086 CPU (
8), the address of the interrupt routine set in the interrupt vector is read and the address is set in the IP (9205).

Then, the single step interrupt vector, which is the function when the 80286 CPU (8) generates a special interrupt, is saved in the stack area of the memory (1) (820
7). Next, rewrite the saved single-step interrupt vector to, for example, 123 (S209), and
IV, set the IF and TF saved in the stack area to 1 so that only the DXSBX instruction is executed in a single step (5211), and when the instruction 61 is executed again with an interleaved return (8213), step S
211 IF and TF setting values are read, and step 52
Read the single step interrupt vector address rewritten in 09, DIV of instruction 61 in a single step,
A single step interrupt vector 123 is generated to execute only the DXSBX instruction, and control is transferred to the switching routine 123.

In this process, 80286 CPU (14) to 8
086 In order to switch to CPU (8), it is determined whether it is a special interrupt (5215), and if it is determined that it is a special interrupt, the switching flag 1 prepared in memory (1) is read (S
217), and if it is not a special interrupt, the switching flag 0 is read (S219).

Next, if the switching flag is 1, all registers AX
, BX, CX, DX, S I, DI, BP.

ES, DS, SS, and SP are saved in the stack area of memory (1) 5221), and at this time, TF and IF are set to 1. Next, the CPU select signal is set to 1 (S223). Then, as explained in Fig. 1, the reset terminal (13) of the 80286 CPU (8)
) becomes 1, so the 80286 CPU (8) goes into the reset state and the 8086 CPU (14) goes into the operating state. The 8086 CPU (14) does not initialize when the reset terminal (13) becomes 0 (8225),
Read the specified processing address. Here, if it is 108, address 108 is set to IP and jumps to 108 (S227). Then 8086 CPU (14
) starts operating from the reset state 108 and 80286
Check the switching flag read by CPU (8) (S2
29), if it is 0, normal reset processing, for example 110, is executed (8230).

If it is 1, all registers saved in memory (1) in step 8223, AX, BXSCXSDXSS ISD I, BP.

Set ES, DSSSSSSP to the register of 8086 CPU (14) 5231), and save the flag register to 8086C.
Set in the flag register of PU (14) (823
2). At this time, TF and IF are set to 1.

Next, the instruction 61 is set in C8 and IP of the 8086 CPU (14) (8233). Then, the interlaced return is made to execute instruction 61 (S214). Then, it reads the TF and IF set to 1, executes only one instruction, the DIV and DXSBX instructions of instruction 61, in a single step, and the 8086 CPU (14) generates a single-step interrupt vector and forces it to a divide-by-zero interrupt vector. transfer control. Here, in order to separate the single step interrupt vector from 80286 CPU (8), 122
shall be. At this time, 80286 CPU (8)
Similarly, CS and IP are each saved in the stack area of memory (1), and IF and TF are set to clear. Here, since the CS and IP of the 8086 CPU (14) have executed one instruction, they are set to point to the next instruction.

Then, the control is transferred to the called interrupt vector 122 processing routine (5235), and the TF and I
Set F to 0 and cancel single step (S23
13).

Next, it is determined whether it is a special interrupt (8238), and if it is a special interrupt, it reads switching flag 1 prepared in memory (1) (S240), and if it is determined that it is not a special interrupt, it reads switching flag 0 (8242). .

Next, all the registers AX, BX, CX, DX, SI when the 8086 CPU (14) executed instruction 61
Save SDI, BP, ESSDS, SS, and SP in the stack area of memory (1) 5243),
At this time, TF and IF are set to 0.

Then, the selector signal is set to 0 (924B).

When the selector signal is set to 0, the 8086 CPU (14) goes into the reset state and puts the 80286 CPU (8) into the operating state as explained in FIG. 80286CP
Switch to U(8).

When switched, the 80286 CPU (8) initializes (8248), sets the jump destination to, for example, 125, reads that address (S250), and returns to reset state 1.
Execution starts from 25. Next, step (S240)
The switching flag set in is checked and it is determined whether it is 0 or 1 (S252). If it is 0, 80286 CPU (8
) to execute the normal reset process 130 5254),
If it is 1, set the switching flag to 0 (325B) and save all registers AX, BX, C in step 5243.
X5DX, S ISD I, BPLES, DS.

5sSsp is set in the register of 808286 CPU (8) (825B).

With the above processing, the process 125 is completed, and 8086 C
The flag register that P U (14) forcibly saved in the stack area of memory (1) is saved to 80286 CPU
(8) Set in the flag register, 8086 CP
U (14) Save CS and IP to 80286
CPU (8) sets its IP and C8.

Now, if you do an interlaced return, C8 and IP will be set to the address of the next instruction, so 80286 CPU
In (8), the program is executed following instruction 62 of the main routine. Therefore, 8086 CPU (
14) and the 80286 CPU (8) are maintained.

Also, for 80286 CPU (14), 8
Compatibility can also be maintained with respect to interrupt segment offset overline interrupts that do not occur in the 086 CPU (8). This segment overline interrupt occurs in the 80286 CPU (8) when a memory access instruction such as MOV, AX, or [BI3 is attempted to access memory beyond a segment, such as BX-OFFFFH. This is an interrupt and does not occur in the 8086 CPU (14). Therefore, the present invention is also used in this case.

Also in segment overline interrupt, 80286
Since the CPU (8) generates a vector, the step (S207) in FIG. 2 is set to save the segment overline interrupt vector, and the same process as that described in FIGS. 2(a) and (b) is performed. 80286 CPU (8) to 8
086 CPU (14), and the incompatibility caused by this interrupt is resolved.

Furthermore, the μPD70116CPU, which is another upwardly compatible CPU of the 8086CPU, was added to the 8086CPU (14
), usually 80286CPU (8
), and when a special interrupt occurs due to division by 0, etc. as explained above, or when the μPD70116CP
When a U-specific instruction is executed, for example, the REPC instruction generates an invalid instruction interrupt in the 80286 CPU (8), so using the present invention, by setting step (S207) to read the invalid instruction interrupt vector, the 80286
By switching from the CPU (8) to the μPD70116 CPU for execution and returning to the 80286 CPU (8), application software created for the μPD70116 CPU can be executed at high speed on the 80286 CPU (8).

The first invention described above is an invention using two CPUs that are compatible in object code, and the second invention in which there are three or more CPUs will be described below.

FIG. 3 is a schematic configuration diagram showing an embodiment of the second invention, in which (1) is a memory, (2) is an input/output device (hereinafter referred to as I10), and (5) is a control bus, an address bus, and a data bus. A selector (5) connected to the bus and used to select the desired CPU.
a) is a CPU that controls the selector.

(8) is 80286CPU, (14) is 8086cPU
.

(21) is 80386 CPU, (22) is 80
There are 186 CPUs, each selected by a selector (5).

The microprocessor control device configured as described above allows each memory (1) to be used in common.For example, when a certain program is being processed in the 80286 CPU (8), division by zero is There is 8028
6 CPU (8) loops, so the selector (5
) reads a CPU capable of the processing from the memory (1) and outputs a signal to operate the corresponding CPU.

In this case, select 8086 CP U (14).

Furthermore, if an interrupt that cannot be processed by the 8086 CPU (14) occurs, for example, the 80386 CPU
If (21) is a corresponding CPU, select it.

This is the CPU (5a) provided inside the selector (5).
) reads a vector which is a special interrupt when division by 0 occurs in the 80286 CPU (8), for example, and executes the special interrupt routine process stored in the memory (1).

FIG. 4 is a flowchart explaining the second invention,
In the figure, dotted lines represent the hardware operations of the CPU.

This special interrupt routine is described below in Figures 3 and 4.
This will be explained using figures.

For example, if the instruction 61 is executed by the 80286 CPU (8) as in FIG. 2, the switching preparation process from step 8201 to step 5223 is executed (340
I). Then, the CPU (5a) of the selector (5) goes into the operating state, and the 80286 CPU (8) goes into the reset state. When the CPU (5a) receives the selector signal, it initializes (8403) and reads the address set in the memory (1) (3405). in this case,
Let the address be 300.

Next, it is read which CPU could not process from the selector signal (S407), the flag register is checked, and what kind of special interrupt it is is read (S409).

Next, the selector signal and flag register are used to read the CPU that can process from memory (1) (S411), set a signal to operate the corresponding CPU, and selector (5)
A selector signal is output from (3413). In this case, an 8086 CPU (14) is operated. Then C
P U (5a) stops operating and 8086 CPU
Control is transferred to (14). Then, as explained in FIG.
You can run the program from 2.

The second invention is 8086 CPU (14) and 80
286 (8), as long as the CPU that can process the memory (1) can be selected from the flag register and selector signal by its number etc., any Intel CPU with 16 bits or more will suffice, for example. 80286 CPU (8) to 80186 as necessary
CPU (22) or 80386 CPU
It is also possible to switch from (21) to 8086 CPU (14). In this case as well, an interrupt handling routine similar to the operation described above is executed.

Furthermore, it is also possible to attach the selector (5) and one or more types of CPUs of 16 bits or more from Intel to a microcomputer with a built-in CPU, and have the selector (5) execute the processing described above. .

In the second invention described above, the CPU to be selected in advance is stored in the memory (1), but if the CPU is not stored in the memory (1), the processing method described below is executed.

FIG. 5 is a flowchart showing an embodiment of the third invention, in which dotted lines represent hardware operations of the CPU.

For example, if a special interrupt occurs at instruction 61 while the 8086 CPU (8) is operating, the 8°86
As explained in FIG. 2, the CPU (8) transfers control to the special interrupt vector and executes the processing from step 8201 to step 8223. However, in this case,
The single step interrupt vector in step 5209 is rewritten to 100, for example, and the TF and IF in step 5211 are set to 0 to cancel single step. Then, the selector signal output in step 5223 is output to the selector (5) (501). Then selector (5) +7)
The CPU (5a) performs initialization 5503), reads the set processing address 400 (S505), and transfers control to the processing address.

Next, the CPU that cannot process is read from the selector signal (8507), and it is determined whether there is another CPU connected to the selector (5) (5508), and if not, an error is determined. Next, a selector signal for switching the CPU is output to the 8086 CPU (14)l (8509). Then, the CPU (5a) of the selector (5) stops operating, and the 8086 CPU (14) becomes operational.

Then, the 8086 CPU (14) executes steps 8225 to 8234 described in FIG. 2 (8510), and executes the set user interrupt routine (S512). Then 8086 CPU (1
4) is the flag register saved in memory (1) and C
8 and IP are restored and the program is executed from instruction 62.

When a special interrupt that cannot be processed by the 8086 CPU (14) occurs in instruction 200, the processing from step 8201 to step 5223 in FIG. 2 is executed.

At this time, the single step interrupt vector in step 5209 is rewritten to 101, for example, and TF and IF in step 5211 are set to 0 to cancel single step. Then, the selector signal output in step 5223 is output to the selector (5) (514).

Then, the processes of steps 8503 to 5507 are executed, and the CPU 801 next to the 8086 CPU (14)
Output selector signal to 86CPU (22) (8
51B).

Next, when the 80186 CPU (22) becomes operational, it again executes the processes of steps 8225 to 5234 and executes the instruction 200 (8518). Then, the set interrupt routine is executed (5520), it is determined whether the special interrupt processing can be performed (5522), and if possible, the program is executed from the instruction 201. If the process cannot be performed, the process from step 8236 to step 5245 is executed (5524), and the CPU of the selector (5) (5a
) outputs a selector signal that operates. Then 801
86 CPU (22>) stops operating.

Next, the CPU (5a) executes the processes from step 8503 to step 5507, and the 80186 CPU (5a)
22) outputs a selector signal that operates the 80386 CPU (21) next to it. When this selector signal is output, the CPU (5a) stops its operation.

That is, if there is a program that cannot be processed, it is run one after another until there is a CPU that can process it.

Further, in the third aspect of the invention, switching processing is possible if the CPU is 16 bits or more manufactured by Intel Corporation.

[Effects of the Invention] As described above, according to the present invention, if there is an interrupt that cannot be processed among the instructions while operating the second microprocessor, which has superior arithmetic processing ability, the next The first microprocessor, which has a processing power of 1, executes the instruction, and the second microprocessor continues processing from the next instruction, thereby automatically resolving the incompatibility.

Furthermore, when multiple microprocessors are connected to the switching means, by storing which microprocessor cannot process the interrupt, even if an interrupt that cannot be processed occurs, the microprocessor that can process it is immediately activated. Therefore, it has the advantage of being compatible with multiple microprocessors.

Furthermore, when one of the plurality of microprocessors is operating, if there is an interrupt that cannot be processed, the switching means operates the microprocessors one after another, so that the microprocessor that can be processed is automatically disabled without having to remember which microprocessor can be processed. This has the effect that compatibility can be resolved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the first invention, FIGS. 2(a) and (b) are flowcharts explaining the first invention, and FIG. 3 is a diagram showing the second invention. 4 is a flowchart explaining the second invention, FIG. 5 is a flowchart explaining the third invention,
FIG. 6 is a schematic configuration diagram illustrating a conventional example, and FIG. 7 is a diagram illustrating a conventional data flow. In the figure, (1) is memory, (2) is input/output device, and (3
) is the selector signal, (4) is the inverter, (5) is the selector, (5a) is the CPU, (6) is the switch, (7) is the reset terminal of 80286 CPU (8), (8)
is 80286 CPU, (9) is 80286 C
Address bus and data bus output from P U (8), (11) is AND, (13) is 8086 CP
U (14) reset terminal, (14) is 8086CP
U, (15) is the address bus and data bus output from the 8086 CPU, (17) is AND, (20) is the output terminal, (21) is the 80386 CPU, (22) is the 80
It has 186 CPUs. Agent Patent attorney Souji Sasaki (b) Figure 2

Claims (3)

[Claims] (1) (a) Have multiple microprocessors that are compatible with each other in object code and have different computing capabilities, and (b) Furthermore, give priority to the operation of the microprocessor with superior computing capabilities. , a microprocessor control device characterized by having a switching means that can handle an interrupt that cannot be processed by an operating microprocessor and causes the next microprocessor with arithmetic capability to perform an arithmetic operation. . (2) (a) A microprocessor that, when a first instruction is executed, generates a special interrupt in which the return address of the interrupt processing specifies the next address of the first instruction, and is operated by a switching signal. a first microprocessor that enters a state, sets all registers of a second microprocessor in its registers, and outputs all of the registers and the return address after executing the first instruction; (b) ) is compatible with the first microprocessor in object code, outputs the switching signal to switch to the first microprocessor when the first instruction is executed, and executes the first instruction; After the first
and a second microprocessor that reads all the registers and return addresses of the microprocessor and executes processing from the instruction following the first instruction. Microprocessor control unit. (3) (a) It has a plurality of microprocessors that are compatible with each other in object code, have differences in computing power, and have a predetermined operation order, and (b) In addition, interrupts that cannot be processed 2. The microprocessor control device according to claim 1, further comprising a switching means for operating a corresponding microprocessor based on said order each time a corresponding microprocessor occurs.