JPH02138331U - - Google Patents
Info
- Publication number
- JPH02138331U JPH02138331U JP4474089U JP4474089U JPH02138331U JP H02138331 U JPH02138331 U JP H02138331U JP 4474089 U JP4474089 U JP 4474089U JP 4474089 U JP4474089 U JP 4474089U JP H02138331 U JPH02138331 U JP H02138331U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- voltage conversion
- axis direction
- unit
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 239000011159 matrix material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図は本考案の実施例に係るキーマスリクス
読込回路の構成図、第２図は第１図のキーマスリ
クス読込回路におけるキーマスリクスの具体的構
成図、第３図は実施例の動作説明に供するための
もので、キーマスリクスにおけるキーの数を９個
にした場合の当該キーマスリクスの構成を示す図
である。第４図は従来例のキーマスリクス読込回
路の構成図である。
１０……電圧供給部、２０……電圧変換部、３
０……キーマスリクス、４０……回路部。
FIG. 1 is a configuration diagram of a key matrix reading circuit according to an embodiment of the present invention, FIG. 2 is a specific configuration diagram of a key matrix reading circuit in the key matrix reading circuit of FIG. 1, and FIG. 3 is a diagram for explaining the operation of the embodiment. FIG. 3 is a diagram showing the configuration of a key matrix when the number of keys in the key matrix is nine. FIG. 4 is a block diagram of a conventional key matrix reading circuit. 10... Voltage supply section, 20... Voltage conversion section, 3
0...Keymasrix, 40...Circuit section.
Claims (1)
Ｙ軸方向に複数本配列された電圧供給線のそれぞ
れの一端側に対して前記基準電源からの電圧を異
なる値の電圧に変換して供給する電圧供給部と、 前記基準電源からの電圧入力部、Ｙ軸方向に延
びるとともに、Ｘ軸方向に複数本配列された電圧
受給線のそれぞれの一端側に接続された複数の電
圧変換入力部、および、電圧変換出力部を有し、
前記電圧入力部と各電圧変換入力部のそれぞれと
の間において前記電圧変換入力部の数に対応した
異なる抵抗値を与える複数の組み合わせ抵抗が接
続され、前記組み合わせ抵抗の最終段が前記電圧
変換出力部に接続されてなる電圧変換部と、 前記各電圧供給線と前記各電圧受給線との各交
叉点のそれぞれに設けられてかつ各電圧供給線側
に一方の接点が電圧受給線側に他方の接点がそれ
ぞれ設けられてなる複数のキーからなるキーマス
リクスと、 前記電圧変換部の電圧変換出力部から出力され
てくる変換電圧に基づいて前記キーマスリクス内
の任意のキー入力を読み込み処理する回路部と、 を備えてなるキーマスリクス読込回路。[Scope of claim for utility model registration] Including a reference power source, extending in the X-axis direction,
a voltage supply unit that converts the voltage from the reference power source into voltages of different values and supplies the voltage to one end side of each of the plurality of voltage supply lines arranged in the Y-axis direction; and a voltage input unit from the reference power source. , having a plurality of voltage conversion input sections extending in the Y-axis direction and connected to one end side of each of a plurality of voltage receiving lines arranged in the X-axis direction, and a voltage conversion output section,
A plurality of combinational resistors providing different resistance values corresponding to the number of voltage conversion input units are connected between the voltage input unit and each of the voltage conversion input units, and the final stage of the combination resistance is connected to the voltage conversion output. a voltage conversion unit connected to the voltage converting unit; and a voltage conversion unit provided at each intersection point of each of the voltage supply lines and each of the voltage reception lines, with one contact on the voltage supply line side and the other contact on the voltage reception line side. a key matrix consisting of a plurality of keys each having a contact point, and a circuit section that reads and processes arbitrary key inputs in the key matrix based on the converted voltage output from the voltage conversion output section of the voltage conversion section. A key matrix reading circuit comprising , and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4474089U JPH074665Y2 (en) | 1989-04-17 | 1989-04-17 | Key matrix reading circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4474089U JPH074665Y2 (en) | 1989-04-17 | 1989-04-17 | Key matrix reading circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02138331U true JPH02138331U (en) | 1990-11-19 |
| JPH074665Y2 JPH074665Y2 (en) | 1995-02-01 |
Family
ID=31558305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4474089U Expired - Fee Related JPH074665Y2 (en) | 1989-04-17 | 1989-04-17 | Key matrix reading circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH074665Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013004052A (en) * | 2011-06-22 | 2013-01-07 | Marusan Name:Kk | Position sensor |
-
1989
- 1989-04-17 JP JP4474089U patent/JPH074665Y2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013004052A (en) * | 2011-06-22 | 2013-01-07 | Marusan Name:Kk | Position sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH074665Y2 (en) | 1995-02-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |