JPH02137269A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase breakdown strength in order that a gate oxide film may not be destructed when an excessive negative surge is applied to an output end by arranging a diode between a signal line connected to a gate and a power line, in the vicinity of a MOS transistor formed on a semiconductor substrate. CONSTITUTION:When an excessive negative surge with a peak voltage lower than ground potential by several hundreds volts is applied to an output end, the negative surge travels to the drain D of an output MOS transistor 1 through an output line 2, and further is transmitted to the gate of the output MOS transistor 1 and an internal signal line 4 via a parasitic capacitance 13 between the drain and the gate, within a very short time. On the drain D of the output MOS transistor 1, a parasitic diode 11 is formed. Between the internal signal line 4 in the vicinity of the gate and a grounded power supply, a diode 14 is arranged. The negative surge transmitted to the drain 10 is quickly weakened and absorbed via the parasitic diode 11. The surge transmitted to the gate of the output MOS transistor 1 and the internal signal line 4 is quickly weakened and adsorbed via the diode 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device with increased surge resistance in a MOS transistor (MOS) transistor formed on a semiconductor substrate.

[Conventional technology]

Figure 4 shows an N-channel open drain output type MOS used in conventional semiconductor devices such as semiconductor integrated circuits.
) is a circuit diagram showing a transistor output circuit, and 1 indicates an N-channel output MOS transistor. For output - OS) Drain D of transistor l is output 'llA
The source S and base are grounded, and the gate is connected to the pre-stage inverter 5 using an internal signal line 4.

The front-stage inverter 5 includes a P-channel MOS transistor 6,
N channel? The drains D of both are connected to each other and to the signal line 4, and the source S of the P-channel MOS transistor 6 is connected to the power supply, and the source S of the N-channel MoS transistor 7 is connected to the power supply. S is assumed to be a ground potential.

Then, both gates are connected to each other, and the input line 8
It is connected to the.

11.12 is N-channel MOS) transistors 1 and 7
The parasitic transistor 13 formed between the drain D and the semiconductor substrate is an N-channel transistor. It shows the parasitic capacitance formed between the drain D and gate of the IO3 transistor 1.

Figure 5 is the output in the MOS) transistor output circuit shown in Figure 4? FIG. 6 is a schematic plan view showing the structure of the lOS transistor 1 and its surroundings, and is also a cross-sectional structural diagram taken along the line Vl--Vl in FIG. 5. In the figure, reference numeral 21 indicates a semiconductor substrate of P- type conductivity, and a field oxide film 40 is formed on this semiconductor substrate 21. As shown in FIG. The surface of the semiconductor substrate 21 exposed in the hole drilled in the field oxide film 40 has a conductivity type of n by ion implantation or the like.
A diffusion drain region 22 of ゛ type and a diffusion source region 23 of conductivity type n゛ type are formed at a required interval, and a diffusion region 24 of conductivity type p゛ type is formed in contact with the diffusion source region 23. has been done. This diffusion region 24 is connected to a ground power source.

An overlying oxide film 41 is laminated to a predetermined thickness on the surfaces of the field oxide film 40, the diffusion drain region 22, and the diffusion source region 23. Diffusion drain regions 22 are formed in the overlying oxide film 41 in such a manner that they span between opposite ends of the diffusion drain region 22 and the diffusion source region 23.
A gate polysilicon 26 is formed between the diffusion source region 23 and the semiconductor substrate 21 with an extremely thin (several hundred thick) oxide film 41a separated therebetween.

A plurality of holes are formed in the overlying oxide film 41 so as to expose the diffusion drain region 22 , the diffusion source region 23 and the diffusion region 24 , and a contact portion 27 and a diffusion source region 23 in contact with the diffusion drain region 22 are formed in the holes. and diffusion region 24
The contact portions 28 are formed in contact with the AI!, and the contact portions 28 are formed on the overlying oxide film 41 in a manner that connects the contact portions 27. An output line 2 made of aluminum is formed, and a ground power wiring 30 also made of aluminum is formed to connect the contact portions 28.
Also, internal signal lines 4 are formed.

The output line 2 is connected to an output end 3 made of an aluminum pad, as shown in FIG. Semiconductor substrate 2Ln” type diffusion source region 23
is held at ground potential. Furthermore, as shown in FIG. 4.5, one end of the internal signal line 4 is connected to the gate polysilicon 26 via a contact portion 31, and the other end is connected to the pre-stage inverter 5.

The parasitic diode 11 is formed at the junction surface between the aforementioned n1 type diffusion drain region 22 and the p- type semiconductor substrate 21. Further, parasitic capacitance 13 is formed between n° type diffusion drain region 22 and gate polysilicon 24 with oxide film 41a sandwiched therebetween.

In such a conventional semiconductor device, when a high-level signal is applied to the input line 8 of the front-stage inverter 5, the P-channel MOS transistor is turned off, and the N-channel MOS transistor is turned on. The internal signal line 4 becomes low level.

Therefore, the output MO3) transistor 1, which is an N-channel MOS transistor, is turned off, and the output terminal 3 is in a high impedance, that is, a floating state.

On the other hand, when a low level signal is applied to the input line 8, the P channel MOS l-transistor is turned on, the N channel MOS transistor 7 is turned off, and the internal signal line 4 becomes high level. Therefore, the output MO3) transistor 1 is turned on, and the output terminal 3 becomes low level.

[Problem to be solved by the invention]

By the way, when a negative surge, that is, a surge with a leading voltage several hundred volts lower than the ground potential, is applied to the output @3 from the outside,
This negative surge is transmitted from the output line 2 to the drain D of the output transistor 1, and is weakened and absorbed by the parasitic diode 11 connected to the semiconductor substrate 1, which is at ground potential.

Further, in this process, the negative surge is transmitted to the gate of the output transistor 1 (MO3) and further to the internal signal line 4 via the parasitic capacitance 13 in a very short time, and is absorbed by the parasitic diode 12 of the front-stage inverter 5.

However, if the internal signal line 4 is long, it takes time for the intrinsic surge to be transmitted to the parasitic diode 12 that absorbs it. Gate polysilicon 26
As a result, a large potential difference is generated between the gate polysilicon 26, the ground potential diffusion source region 23, and the semiconductor substrate 21, and there is a possibility that the thin oxide film 41a may be destroyed.

When comparing the diffusion source region 23 and the semiconductor substrate 21, the diffusion source region 23 has a stable potential because it is connected to the ground power supply via the wiring 30, whereas the semiconductor substrate 21 has a stable potential because the diffusion source region 23 has a stable potential. Also through the back metal film 3
2 is connected to the ground power supply via the gate polysilicon 26, but the potential is negative on the gate polysilicon 26 due to the large bulk resistance and the presence of gate capacitance between the gate polysilicon 26 and the semiconductor substrate 21. They are susceptible to sexual surges. Therefore, the potential difference between gate polysilicon 26 and source region 23 is greater than the potential difference between gate polysilicon 26 and semiconductor substrate 21.

Moreover, in FIGS. 5 and 6, since the field oxide film 40 has a tapered surface at the boundary between the diffusion source region 23 and the field oxide film 40, the gate polysilicon 26 is formed along this tapered surface in the portion that crosses the boundary. As the oxide film 41a becomes curved, the electric field tends to concentrate in these parts, and the oxide film 41a
destruction is more likely to occur.

The present invention was made in view of the above circumstances, and its purpose is to improve the breakdown resistance so that the oxide film will not be destroyed even if an excessive negative surge is applied to the output terminal. To provide semiconductor devices.

[Means to solve the problem]

In the semiconductor device according to the present invention, a diode is provided in the vicinity of a MOS transistor formed on a semiconductor substrate between a signal line connected to the gate of the MOS transistor and a power supply.

[Effect]

According to the present invention, even if an excessively negative surge is applied to the output terminal and this negative surge is transmitted to the signal line via the parasitic capacitance, this can be quickly absorbed.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

Figure 1 shows an N-channel open drain output type M
OS) This is a circuit diagram of a transistor output circuit, and 1 in the figure
indicates an N-channel output MOS transistor. Output MOS) The drain D of the transistor 1 is connected to the output end 3 via the output line 2, the source S and base are grounded, and the gate is connected to the previous stage inverter 5 via the internal signal line 4. .

The pre-stage inverter 5 connects the drains D of the P-channel MOS transistor 6 and the N-channel S transistor 7 to each other, and also connects the drains D of the P-channel MOS transistor 6 and the N-channel S transistor 7 to the internal signal line 4.
The source S of the channel L/MOS transistor 6 is connected to the power supply, and the source of the N-channel MOS transistor 6 is connected to the ground potential. Both gates of the P-channel MOS transistor 6 and the N-channel 1OS transistor 7 are connected to an input line 8 in a mutually connected state. Parasitic diodes 11 and 12 are formed in each of the N-channel MO3) transistors 1 and 7, the anode side of which is connected to the drain D, and the cathode side of which is connected to the ground potential. A parasitic capacitance 13 is formed between them.

In the device of the present invention, a diode 14 is provided near the gate of the output MOS l-transistor 1, with the anode side connected to the internal signal line 4 connected thereto, and the cathode side connected to the ground wire. It is.

2 is a schematic plan view showing the MOS transistor 1 shown in FIG. 1;) an output MOS in the transistor output circuit; and FIG. 3 is a cross-sectional structural diagram taken along line mm in FIG. 2. A field oxide film 40 is laminated to a required thickness on the surface side of a semiconductor substrate 21 whose conductivity type is p- type, and an n° type diffusion film is formed in the semiconductor substrate 21 exposed in the hole drilled in this field oxide film 40. A drain region (hereinafter simply referred to as a drain region) 22, an n1 type diffusion source region (hereinafter simply referred to as a source region) 23 separated from this by a required distance, and a p+ type diffusion region 24 in contact with this are formed; Further, an n-type diffusion region 2 for forming the diode 14 is spaced apart from the p-type diffusion region 24 by a required distance.
5 is formed.

The surface of the drain region 22, the source region 23. Diffusion area 2
An overlay oxide film 41 is formed to a required thickness on the surface of 4.25 and the surface of the field oxide film 40, and this overlay oxide film 4
1, a thin gate oxide film 4 is provided between the n-type diffused drain region 22 and the n-type diffused source region 23 and between these two head regions 22 and 23 and the p-type semiconductor substrate 21.
Gate polysilicon 26 is placed across 1a.

Further, the upper oxide film 41 has a drain region 22 . Source area 23. Contact portions 27.2 are provided in a plurality of holes drilled at positions facing the diffusion regions 24.25 and in contact with these regions.
8.29 is formed, and on the overlying oxide film 41, the output line 2 is connected in a manner to connect each of the contact parts 27, and the ground power supply wiring 30 and the contact part 29 are connected in a manner to connect each contact part 28. Internal signal lines 4 are provided respectively, and a glass coat film 42 is laminated thereon in such a manner as to cover these lines.

The output line 2 is connected to an output end 3 made of an aluminum pad as shown in FIG. Substrate 21. n” type source region 23
is held at ground potential.

Furthermore, as shown in FIG. 2.3, one end of the internal signal line 4 is connected to the gate polysilicon 26 via a contact portion 31, and the other end is connected to the pre-stage inverter 5, as well as via a contact portion 29. It is connected to the diode 14 made up of the diffusion region 25 and the semiconductor substrate 21 .

In such a device of the present invention, the P-channel MOS transistor to which a high potential level (referred to as high level) signal is applied to the input line 8 of the front-stage inverter 5 becomes non-conducting (referred to as off); On the other hand, N-channel MOS
) Since the Ranjistaf becomes conductive (referred to as on), the internal signal line 4 becomes at the ground potential level (referred to as low level).

Therefore, the output MOS I-transistor 1 is turned off, and the output terminal 3 is in a high impedance (floating) state.

On the other hand, when a low level signal is applied to the input line 8, the P channel MOS transistor 6 is turned on and the N channel MOS transistor 6 is turned off, so that the internal signal line 4 becomes high level. Therefore, the output MOS transistor 1 is turned on, and the output terminal 3 becomes low level. This causes internal information to be output to the outside.

Next, the effect when a surge is applied to this MOS transistor output circuit from the outside via the output terminal 3 will be explained.

For example, when an excessively negative surge with a leading voltage several hundred volts lower than the ground potential is applied to the output terminal 3, this negative surge passes through the output line 2 to the drain D of the output MOS transistor 1.
In addition, it is transmitted to the gate of the output MO3) transistor l and to the internal signal VA4 within a very short time via the parasitic capacitance 13 between the drain and gate. A parasitic diode 11 is formed at the drain D of the output MO3) transistor 1, and a diode 14 is provided between the internal signal line 4 and the ground power supply near the gate. The electrical surge is transmitted through the parasitic diode 11,
Further, the negative surge transmitted to the gate of the output MO3) transistor 1 and the internal signal line 4 is quickly weakened and absorbed through the diode 14.

This process will be explained in more detail based on FIG. 2.3.

In FIG. 2, the negative surge applied from the output end 3 made of an aluminum pad is transmitted to the n-type drain region 22 through the output vA2, and then immediately transmitted to the n-type drain region 23 and gate polysilicon 26. .

The transmitted negative surge is transferred to the internal signal line 4 and the contact section 2.
9 to the n-type diffusion region 25, from where the p-
A portion of the energy is absorbed into the ground power supply through the semiconductor substrate 21 of the type, the expanded 'III jI region 24, and the ground power supply wiring 30, and a portion of the energy is absorbed from the semiconductor substrate 21 through the back metal film 32, respectively.

In addition, although the embodiment has described a configuration applied to an N-channel open drain output type MOS transistor output circuit formed on a p-type semiconductor substrate 21, the present invention is not limited to this in any way. The present invention can also be applied to an N-channel output transistor formed in a p-type island formed in 2008, and can also be applied to a CMO5 output circuit using P-channel and N-channel output transistors.

Furthermore, it can be applied not only to output circuits but also to input/output circuits. Furthermore, although the above-described embodiments have been described with respect to a MOS transistor having a polysilicon gate, the same effect can be obtained by applying the present invention to a MOS transistor having a metal gate such as an aluminum gate.

〔Effect of the invention〕

As described above (in the device of the present invention, a diode is provided near the gate of the MOS transistor and between the signal line connected to the gate and the power supply, so even if an excessive surge is applied to the output terminal, this will not occur). The present invention has excellent effects such as being able to quickly weaken and absorb the oxidation film, preventing the destruction of the oxide film interposed between the gate and the source, greatly increasing surge resistance, and achieving high reliability. It is something.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the device of the present invention, FIG. 2 is a schematic plan view of the MOS transistor and its surroundings in the circuit shown in FIG. 4 is a circuit diagram of the conventional device, FIG. 5 is a schematic plan view of the MOS transistor and its surroundings in the circuit shown in FIG. 4, and FIG. 6 is the Vl-Vl line in FIG. 5. FIG. 1... Output MOS transistor 2... Output line 3
...Output end 4...Internal signal line 5...Previous stage inverter 6...P channel MOS transistor 7...
・N-channel MOS) transistor 8...output line 1
1.12... Parasitic diode 13... Parasitic capacitance 1
4... diode 21... semiconductor substrate 22...
Drain region 23... Source region 24, 25...
... Diffusion region In the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 40: Field oxide film 41a oxide scale diagram procedural amendment voluntary) 1117□24EI 1. Indication of the case Patent Application No. 63-292984 2. Name of the invention semiconductor device 3. Person making the amendment Relationship to the incident Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Moriya Shiki, representative of Mitsubishi Electric Corporation 4, agent, 5. “Claims” and “Detailed Description of the Invention” of the specification to be amended
as well as Drawing 6, Contents of Amendment 6-1, "Claims" column of the specification, and the "Detailed Description of the Invention" column of the 6-2 specification (page 3 of the 11 specification From the first line to the fourth line of the same page, it says “It shows...
(Omitted) The phrase ``the surface of the semiconductor substrate 21'' has been corrected to ``the surface of the semiconductor substrate 21''. (2) The phrase "It is" on page 3, line 10 of the specification should be corrected as follows. "In addition, a field oxide film 40 is formed on the semiconductor substrate 21 in a portion where the formation of the above-mentioned diffusion region is unnecessary." (3) Page 3, line 13 of the specification On the 144th line of page 144, the phrase ``in the overlying oxide film 41 is the above'' is corrected to ``also the above.'' (4) The phrase "oxide film 41a" on page 3, line 17 of the specification is corrected to "gate oxide film 41a." (5) On page 4, line 10 of the specification, the words "aluminum bands" are corrected to read "aluminum pads." (6) In the first line of page 5 of the specification, the phrase "oxide film 41a" is corrected to "gate oxide film 41a." (7) “Thin oxide film 41a” on page 6, line 18 of the specification
The text has been corrected to read "thin gate oxide film 41a." (8) On page 7, line 16 of the specification, the phrase "oxide film 41a" is corrected to "gate oxide film 41a." (9) On page 7, line 20 of the specification, the phrase "oxide film" is corrected to "gate oxide film." Q [The statement "According to the present invention... (omitted)..." on page 8, line 4 to line 7 of the same page of the specification is corrected as follows. "The semiconductor device according to the present invention includes a gate of a first conductivity type MOS transistor formed on a semiconductor substrate, and the above-mentioned M
A diode formed by a first conductivity type diffusion-second conductivity type diffusion junction between a first power supply connected to a source of the OS transistor is provided near the MOS transistor. ” 0υ On page 8, line 11 of the specification, the phrase “on the signal line” is corrected to “on the above signal line.” On page 10, line 6 to line 9 of the specification, it is stated that ``the conductivity type is p- type... (omitted)... for the half-quad substrate 21.''
The statement has been corrected to read, "On the surface of the semiconductor substrate 210 whose conductivity type is p-type." 0■ On page 10, line 16 of the specification, the phrase ``formed'' should be replaced with ``formed.'' Also, field oxidation is applied to areas on the semiconductor substrate 21 where it is not necessary to form the above-mentioned diffusion region. A film 40 has been formed.'' 04) From page 10, line 19 to page 200 of the specification
is formed, and in this upper layer oxide film 41 there is a
It is formed. Also, the above is corrected. a9 In the first line of page 14 of the specification, the phrase "of aluminum bands" is corrected to "of aluminum pads." 06) On page 14, line 4 to line 5 of page 14 of the specification, the phrase "in the n-type drain region 23 and gate polysilicon 26" is corrected to "in the gate polysilicon 26." Q7+ On page 15, line 11 of the specification, the word "oxide film" is corrected to "gate oxide film." 6-3 Figure 3 of the drawing is corrected as shown in the attached sheet. 7. List of attached documents (1) Document stating the entire text of the amended scope of patent claims 1 copy (2) Corrected drawings 1 copy Document stating the entire text of the amended scope of patent claims 2. Scope of claims +1) A semiconductor device comprising a gate of a MOS transistor formed on a semiconductor substrate and a MOS transistor 91H. 40: Field oxide film 41a: Kate II & Kasaka figure

Claims (1)

[Claims] (1) A semiconductor device characterized in that a diode is provided near the gate of a MOS transistor formed on a semiconductor substrate and between a signal line connected to the gate and a power supply.