JPH02137263A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the decrease of threshold voltage caused by electric field concentration, restrain the inverse narrow channel effect, and microminiaturize a memory cell by installing a diffusion region of the sme conductivity type as a channel region on both ends in the width direction of the channel region of an island type epitaxial semiconductor layer. CONSTITUTION:The concentration of a semiconductor substrate 21a is made high, and that of an epitaxial semiconductor layer 21b is made comparatively low; an island type epitaxial semiconductor 21b is formed by isolating a part between grooves 23 with an insulator layer 22. On the peripheral part of the island type epitaxial semiconductor layer 21b, a P<+> type diffusion region 35 is formed, and arranged on the peripheral part where the gate electrode 30 of an MOS transistor functioning as a word line and the island type epitaxial semiconductor layer 21b intersect each other. The P<+> type diffusion region 35 is arranged on the peripheral end of an insulator layer 22 in the width direction of a channel region 28 of the MOS transistor, thereby preventing the decrease of the threshold voltage of a gate oxide film 29 caused by the electric field concentration at the peripheral end. As a result, the increase of current at the peripheral end in the width direction of the channel region 28 caused by electric field concentration can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a dynamic random access memory device, and more particularly to an improvement for increasing the integration density of a trench type one-transistor/one-capacitor type memory cell.

(b) Conventional technology DRAM as a semiconductor memory device has a remarkable degree of integration, but in order to achieve this high degree of integration, dynamic
It is essential to miniaturize memory cells, which are the basic components of random access memories (DRAMs).

Generally, a DRAM memory cell consists of one transistor and one capacitor, and stores information by accumulating charge in the capacitor. Therefore, if the capacitance of the capacitor is small, circuit malfunctions and soft errors due to alpha rays are likely to occur, so even if the memory cell is miniaturized, it is necessary to ensure a capacitance above a certain value (generally 50 fF or more). In response to these demands,
Trench-type memory cells, in which a trench is dug in a semiconductor substrate and a capacitor is formed within the trench, are beginning to be used.

FIG. 5 shows a cross section of a conventional trench type memory cell. - A capacitor is constructed by forming a dielectric film (4) on the side wall of a silicon groove (3) formed in a silicon substrate (1) and burying an electrode (polysilicon) (5) in the groove. In this structure, the sidewalls of the trench are used to form a capacitor, so in principle, even if the memory cell is reduced, the capacitor area can be secured by deepening the trench, so a constant capacitance can be obtained. .

However, the memory cell having the above structure has the following drawbacks. That is, although the trenches of adjacent memory cells are separated by the field oxide film (2), this separation is not perfect, so as the trench spacing becomes narrower, the depletion layers between the trenches of adjacent capacitors approach each other. Therefore, a nok current is likely to occur between the grooves. As a result, memory cell characteristics such as cell breakdown voltage and retention characteristics deteriorate. Therefore, it is necessary to set the groove spacing to a certain value or more. This leakage between grooves becomes more likely to occur as the grooves become deeper. In this way, it becomes difficult to narrow the distance between the trenches, which poses a major restriction on the reduction of memory cells. As a method for narrowing the above-mentioned trench spacing, there is a method of increasing the impurity concentration of the silicon substrate (1) to suppress the expansion of the depletion layer and make it difficult to generate leakage current. There are problems such as an excessively high threshold voltage of transistors formed on the same silicon substrate and a reduction in junction breakdown voltage, which naturally has limitations. Furthermore, conventional trench type memory cells have the disadvantage of being inherently vulnerable to soft errors caused by alpha rays.

In summary, conventional trench memory has the problem of deterioration of cell characteristics due to leakage current between trenches.
In order to avoid this, it is necessary to increase the distance between the grooves of adjacent memory cells, which is a major restriction on the reduction of memory cells, and the resistance to soft errors caused by alpha rays is weak. It has its drawbacks.

Therefore, Japanese Patent Application Laid-Open No. 158867/1983 proposes a semiconductor memory device that eliminates the drawbacks of the conventional trench type memory cell and can further promote ultra-high integration or high density.

FIGS. 6A to 6F are cross-sectional views showing states at each step of manufacturing this memory.

First, the structure of this memory will be explained with reference to FIG. 6F. As shown in the figure, this memory is a trench-type DRAM.
A substrate (1a) of a semiconductor containing a high concentration of impurities, for example P1 type silicon, an epitaxial semiconductor layer (1b) formed by epitaxial growth on the substrate (1a), for example a P silicon layer (1b), and an epitaxial layer (1b) formed by epitaxial growth on the substrate (1a).
1b) from each other and divides the epitaxial layer (1b) into island-like parts, such as an insulating layer such as a silicon oxide film (2
), through the epitaxial layer (lb), and through the substrate (1a
) A groove (3) extending into the groove (3) and a capacitor (13) formed on the side wall of the groove (3). This capacitor (13) has a dielectric film (4) formed on the side wall of the groove (3).
and an upper electrode (5) formed thereon.

The capacitor (13) is N that constitutes the source and drain.
A MOS formed of a type diffusion layer (9) and a gate electrode (also serving as a word line) (8) formed on the channel between the source and drain via a gate oxide film (6).
It is connected to the bit line (12) by a contact hole (11) via a transistor. Capacitor (1
The upper electrode (5) of 3) is insulated by the word line (8), which also serves as the gate electrode of other memory cells, and the silicon oxide film (7), and is also insulated from the bit line, etc. by the interlayer insulating film (10). There is.

Next, an example of a method for manufacturing the above memory will be described with reference to FIGS. 6A to 6F. First, add P-type impurities to 5 x 10
A silicon oxide film (2
) is deposited to a thickness of 1 to 2 μm over the entire surface, and then a silicon oxide film pattern (
2) (Fig. 1A).

Next, using the silicon oxide film (2) as a mask, as shown in FIG. The single crystal silicon layer (1b) contained in the silicon oxide film (
The film is selectively epitaxially grown to a thickness (1 to 2 μm) similar to the film thickness of 2). Through the steps up to this point, the silicon layer (epitaxial silicon layer) (lb) that forms the device on the high-concentration silicon substrate (1a) has its sides completely separated by the silicon oxide film (2) and becomes an island-like part. A separated structure is formed. This is a technique called selective epitaxial growth separation method.

Next, using the silicon oxide film and silicon nitride film patterned by phosphorography technology as a mask, the silicon is etched by reactive sputter etching to penetrate the epitaxial silicon layer (1b) and into the high concentration silicon substrate below. Grooves with a depth of 3 to 6 μm (
3) is formed (Fig. 1C). Next, after cleaning the surface of the groove (3) by chemical etching or sacrificial oxidation,
~200 thin silicon oxide film or 50-100
A capacitor dielectric film (4) such as a composite film consisting of a silicon oxide film as thin as a person's thickness and a silicon nitride film as thin as a 50 to 100 people is formed. Next, a polycrystalline silicon film (5) doped with impurities is deposited to fill the groove (3), and the surface of the polycrystalline silicon film (5) is flattened by an etch-back method. ) is patterned using lithography technology to form an upper electrode layer 5), thereby forming a trench capacitor (13) (
Figure 1 D).

After this, as shown in Figure 1E, a transistor gate oxide film (6) is formed to a thickness of 150 to 300 nm, and then a polycide film (8) (silicide such as Mo or W is placed on polycrystalline silicon). A layer (8) serving as a gate electrode and word line wiring is formed by depositing a layer (8) and patterning it using lithography technology. Note that it is also possible to use silicide or polycrystalline silicon instead of polycide. Thereafter, as shown in Fig. 1F, by the usual technique,
N-type diffusion layer that becomes the source and drain of the transistor (9>, interlayer insulating film such as PSG + BPSG <10),
A contact hole (11), a metal wiring (12) made of aluminum or aluminum alloy for a bit line, and a protective film (not shown) using a known technique are formed to complete the semiconductor memory device.

(c) Problems to be Solved by the Invention However, even in the above-mentioned improved semiconductor memory device, the silicon layer (1b) intersects with the gate electrode (8).
There is a risk that an inverse narrow channel effect may occur at the end of the island-like portion. The reverse narrow channel effect refers to the gate electrode (8)
The electric field from the silicon layer (1b) under the gate electrode (8)
This is a phenomenon in which the threshold voltage is concentrated at the edges of the island-like part of the channel region, and the threshold voltage at the edges is lower than that at the center of the channel region, and when the channel width is narrowed, the threshold voltage as a MOS transistor decreases. be.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and solves the conventional problems by providing a diffusion region of the same conductivity type as the channel region at the peripheral edge of the island-shaped epitaxial semiconductor layer. The present invention is intended to realize a semiconductor memory device that has greatly improved these points.

(*) Effect According to the present invention, diffusion regions of the same conductivity type as the channel region are provided at least at both ends of the channel region in the width direction of the island-shaped epitaxial semiconductor layer. It is possible to prevent the threshold voltage from decreasing due to the concentration of the electric field, suppress the reverse narrow channel effect, and realize the miniaturization of °C memory cells.

(F) Embodiment An embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 1 to 4. FIG. 1 is a top view of the semiconductor memory device of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along line I-II and line ■-■ in FIG. 1.

The semiconductor memory device of the present invention is a trench type DRAM, and includes a semiconductor containing a high concentration of impurities, such as a P+ type silicon substrate (21a), and an epitaxial layer, such as a P− type silicon layer (21b), on this substrate (21a). ), an insulator layer that divides the epitaxial layer (21b) into island-like parts, such as a silicon oxide film (22), and a groove <23) that penetrates the epitaxial layer (21b) and reaches into the substrate (21a). and a capacitor <24) formed on the side wall of the groove <23). This capacitor (24) includes a dielectric film (25) formed on the side wall of the groove (23) and an upper electrode (26) formed thereon.

The capacitor <24) constitutes the source and drain.
gate electrode (also serves as a word line) formed on the channel region (28) between the source and drain via the gate oxide film (29)
It is connected to the bit line (32) through a contact hole (31) through a MOS transistor formed by. The upper electrode (26) of the capacitor (24) is insulated by a silicon oxide film (33) and a word line (30) which also serves as the gate' of another memory cell, and is insulated from the bit line (33) by an interlayer insulating film (34). 32) etc.

The feature of the present invention lies in the P'' type diffusion region (35) provided around the island-shaped epitaxial semiconductor layer (21b).This P'' type diffusion region (35) is shown in FIG. As shown in , this P type diffusion region (35) is always provided at least at the peripheral edge where the gate electrode (30) of the MOS transistor intersects with the island-shaped epitaxial semiconductor layer (21b). As is clear from FIG. 3, the channel region (28) of the MOS transistor is provided at the peripheral edge of the insulator layer (22) in the width direction, and the gate oxide film (29) is formed due to concentration of electric field at the peripheral edge. This prevents the threshold voltage from decreasing. Therefore, according to the structure of the present invention,
It is possible to prevent the addition of current due to the concentration of electric field at the peripheral edge in the width direction of the channel region (28), and to prevent the threshold potential from decreasing due to the reverse narrow channel effect even if the MOS transistor is miniaturized.

Next, a method of manufacturing a semiconductor memory device according to the present invention will be described with reference to FIGS. 4A to 4D.

First, as shown in Figure 4A, 5×101 P-type impurities were added.
A silicon oxide film (22) with a thickness of 1 to 2 μm is deposited on the entire surface by CVD on a silicon substrate (21 m) containing a high concentration of ``w 5 A silicon oxide film pattern (22) is then formed.

Next, using the silicon oxide film (22) as a mask, as shown in FIG. A single-crystal silicon layer (21b) is selectively epitaxially grown to a thickness (1 to 2 μm) similar to that of the silicon oxide film (22). Through the steps up to this point, Silicon layer (epitaxial silicon layer) that forms the element (21b)
However, the side surfaces are completely separated by the silicon oxide film (22) to form a structure divided into island-like parts. This is a technique called selective epitaxial growth separation method.

Next, as shown in FIG. 4C, 9977 epitaxial layers (
21b) Nitriding the surface. That is, 1050”C1NH$
Epitaxial silicon lit (
21b) The surface is nitrided to form a silicon nitride film of about 100 layers (
36).

Next, as shown in the fourth diagram, using the silicon nitride film (36) as a mask, the silicon oxide film (22) is selectively wet-etched with a mixed acid to form about 2000 steps. As a result, the side surface of the epitaxial 9977 layer (21b) adjacent to the silicon oxide film (22) is approximately 2
000 people are exposed to the depth.

Next, as shown in FIG. 4E, a boron silicate glass (BSG) layer 37) is deposited on the entire surface, and low temperature annealing is performed at about 875 DEG C. for 30 minutes. As a result, boron is diffused from the epitaxial silicon layer (21b) whose side surfaces are exposed, forming a P+ type diffusion region (35) with a width of about 0.3 μm.This diffusion region (35) is a channel region (
28) and the silicon oxide film (22) in contact with the silicon oxide film (22) to prevent a decrease in threshold voltage. After that, a boron silicate glass layer (37) and a silicon nitride film layer 36 are formed.
) is removed by chemical etching.

Next, as shown in FIG. 4F, using the silicon oxide film and silicon nitride film patterned by lithography as a mask, the silicon is etched by reactive substrate etching to penetrate the epitaxial silicon layer (21b). , a groove 23) having a depth of 3 to 6 μm is formed that reaches into the lower high-concentration silicon substrate.

Next, as shown in FIG. 4G, after cleaning the surface of the groove (23) by chemical etching or sacrificial oxidation,
Capacitor dielectric film (2
5) Next, a polycrystalline silicon film (26) doped with impurities is deposited, the groove (23) is filled, and the surface of the polycrystalline silicon film (26) is flattened by an etch-back method. A trench capacitor (23) is formed by patterning the polycrystalline silicon film <26) by lithography to form an upper electrode (26).

Thereafter, as shown in FIG. 4H, a gate oxide film (29) of the MOS transistor is formed to a thickness of 150 to 300 mm.
Furthermore, polycide film (30) (MO on polycrystalline silicon)
A layer (30) containing silicide such as +W is deposited and patterned using lithography to form a layer (30) that serves as both a gate electrode and a word line wiring. Note that it is also possible to use silicide or polycrystalline silicon instead of polycide.

After that, as shown in Figure 1 ■, the MOS
N-type diffusion layer (27), which becomes the source and drain of the transistor, and an insulating film between the eyebrows such as PSG or BPSG (34)
, a contact hole (31), a metal wiring (32) made of aluminum or aluminum alloy for a bit line, and a protective film (not shown) using a known technique to complete the semiconductor memory device.

(G) Effects of the Invention As described above, according to the present invention, the semiconductor substrate (21a) has a high concentration, the epitaxial semiconductor layer (21b) has a relatively low concentration, and the insulating layer (22) for isolation has a high concentration. Groove (2
3) Since the grooves (23) are separated from each other, leakage current can be suppressed even if the distance between the grooves (23) is narrowed, and memory cells can be made at high density.

Furthermore, since a P+ type diffusion region (35) is formed around the epitaxial semiconductor layer (21b) surrounded by the insulator layer (22), at least in the lower part of the gate electrode (30),
Even if the channel width of the switching MOS transistor forming the memory cell is reduced, the reverse narrow channel effect can be suppressed, and further miniaturization of the memory cell can be realized.

[Brief explanation of the drawing]

FIG. 1 is a top view illustrating a semiconductor memory device according to the present invention, and FIGS. 2 and 3 are the m-I line and
4A to 4I are sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention, FIG. 5 is a sectional view illustrating a conventional semiconductor memory device, and FIG. FIGS. 6A to 6F are cross-sectional views illustrating a conventional method of manufacturing an improved semiconductor memory device.

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type with a high impurity concentration, an epitaxial semiconductor layer of one conductivity type formed by epitaxial growth on the substrate, an insulator layer that separates the epitaxial semiconductor layer from each other in an island shape, and the island-shaped In a semiconductor memory device comprising a memory cell formed in an epitaxial semiconductor layer, a diffusion region of one conductivity type is provided around the island-shaped epitaxial semiconductor layer in contact with the insulator layer to suppress a reverse narrow channel effect. A semiconductor memory device characterized by: (2) The diffusion region is a switching MOS of a memory cell.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided at both ends of a gate electrode of the transistor.