JPH02137185A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve defect decision ability by inverting memory cell data, to which inverted data are written, out of the prescribed number of memory cells, which are simultaneously selected, and reading the remained memory cell data as they are at the time of reading. CONSTITUTION:In memory cell array blocks 10a, 10b and 10d, when the selected memory cell is connected to a bit line BL, the same data as writing data are written in a test mode. Then, in a memory cell array block 10c, a value, for which the writing data are inverted, is written at the time of the test mode. At the time of reading, the information of the memory cell to which these inverted data are written, are inverted and read and in the remained memory cell, the information are read as they are. Accordingly, even when the inversion is generated, this generation of the data inversion can be detected without fail. Thus, the defect detection ability is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device, and in particular, to a dynamic semiconductor memory device, and in particular, to a dynamic semiconductor memory device, and in particular, to provide a function for simultaneously testing multiple bits of memory cells during a functional test of memory cells included in the semiconductor memory device. The present invention relates to a configuration for more accurately performing a functional test on a dynamic semiconductor memory device equipped with a dynamic semiconductor memory device.

[Prior Art] In recent years, as the capacity of semiconductor storage devices has increased, a problem has arisen in that the time required for functional tests to test whether memory cells in these storage devices are operating normally has become extremely long. It has arisen. In other words, as the capacity of semiconductor storage devices increases, the number of memory cells included therein also increases.
In the conventional configuration in which a functional test is performed by sequentially reading out the memory contents of memory cells one bit at a time, a problem has arisen in that the time required to perform a functional test on all memory cells increases significantly with the number of memories. Therefore,
A configuration for greatly reducing the time required for this functional test is described, for example, in IEEE Journal of Solid State Circuits, Volume 5C-20, No. 5, 1.
Kumanoya et al., “Highly Reliable 1 Megabit DRAM with Multi-ψ-Bit Test Mode (A Re
1iable 1-Mbit DRAM wit
h a Multi-Bit-Test Mod
e) As proposed in ``, when multiple bits of memory cells are simultaneously selected in a semiconductor memory device and the logical values of information read from the simultaneously selected memory cells are all the same, a certain logical value A method of simultaneously performing functional tests on multiple memory cells by outputting the data to the outside of the storage device (hereinafter, an operation mode in which the functional tests on multiple memory cells are performed simultaneously is referred to as a test mode) has come into use. Semiconductor memory devices equipped with such a test mode have been put into practical use.

FIG. 2 shows an example of the configuration of a conventional semiconductor memory device equipped with the above-mentioned test mode. In the configuration shown in Figure 2, 1
Mega (1 million) bit random access memory (
A simplified configuration of an IMDRAM (hereinafter referred to as IMDRAM) is shown.

In FIG. 2, the memory cell array 10 includes four memory cell array blocks 10a, 10b, 10c and 10.
It is divided into d. In the case of IMDRAM, each memory cell array block 10a-10d each has 256 bits of memory cells. Memory cell array block 10
In each of a to 10d, a memory cell array is arranged in rows and columns, a word line WL for selecting one row of memory cells, and a bit line B to which one column of memory cells is connected.
L and BL are provided. Bit line BL and complementary bit line B
The memory cells MC are arranged in pairs with the word line WL and the bit line pair BL, and the memory cell MC is arranged at the intersection with one bit line of the bit line pair BL, BL.
is provided. That is, the bit lines BL, BL provide a folded bit line configuration. Each memory cell array block 1
Each of 0a to 10d is provided with sense amplifiers 12a to 12d for sensing and amplifying information of a selected memory cell. Sense amplifiers 12a to 12d each include a unit sense amplifier provided for bit line pair BL, BL. Therefore, each of sense amplifiers 12a to 12d has 512 unit sense amplifiers in the case of an IMDRAM.

In order to select one word line in one row of the memory cell array 10, that is, in each memory cell array block 10a to 10d, a row address signal A is applied from the outside.
Address buffer 14 receives O-A9 and generates internal row address signals RAO-RA9, and address buffer 1
Row decoders 16a-16d are provided which receive internal row address signals RAO-RAS from 4 and select one word line in each memory cell array block.

The row decoders 16a to 16d decode the applied row address signals RAO to RAS, select a corresponding word line, and transmit the word line drive signal WL applied from the word driver 18 onto the selected word line. do.

Internal column address signals CAO-CA from address buffer 14 are used to select one set of bit line pairs BL, BL from each memory cell array block 10a-10d.
Column decoders 20a to 20d7 receive 8 and select the corresponding bit line pair! Address buffer 14 receives row addresses and column addresses in a time-division manner, and generates internal row addresses RAO-RA9 and internal column address signals CAO-CA9 in a time-division manner.

A nibble decoder 22 and a selection gate 24 are provided to select 1 bit, 4 bits simultaneously, or 4 bits sequentially depending on the operation mode among the 4 bits of memory cells simultaneously selected in memory cell array blocks 10a to 10d. .

The selection gate 24 connects the internal data lines DB, DB to the data output line of the memory cell array block 10a! 101. l
Transfer gate transistors Tri and Tr2 and internal data lines DB and DB are connected to data input/output line pair 1102 of memory cell array block 10b.
．． l102+: Transfer gate transistors Tr3 and Tr4 for connection and internal data lines DB and DB
are the data input/output lines of the memory cell array block 10c, respectively! 103. Transfer gate transistor Tr5. connected to l103. Tr6 and data lines DB, DB
are connected to the data input/output lines 1104. of the memory cell array block, respectively. It includes transfer gate transistors 'l'r7 and Tr8 connected to l104.

Nibble decoder 22 receives internal row address signal RA9 and internal column address signal CA9 applied from address buffer 14, and selects gate 2 in normal mode.
Only one set of transfer gate transistors RA9.4 is made conductive, and in the nibble mode, internal address signals RA9. The sets of transfer gate transistors in the selection gate 24 are sequentially and cyclically turned on starting from the set of transfer gate transistors designated by CA9.

Here, the normal mode is an operation mode in which one bit of data is input/output per one memory cycle (while the signal RAS is at "L" level) in a semiconductor memory device, and the nibble mode is an operation mode in which one bit of data is input/output per memory cycle (while the signal RAS is at "L" level). is given, one bit of memory cell is selected in response to this row address and column address, and after writing or reading this memory cell data, the signal fτ is set to “
This is an operation mode in which the CAS signal is toggled while being held at the "L" level, and the following 3-bit memory cell data is sequentially written or read. In this nibble mode, the row address and column address are set for each memory cell. Therefore, memory cell data can be written/read at a higher speed than in normal mode in units of one bit.

Preamplifiers 26a to 26d are provided between selection gate 24 and memory cell array 1o to amplify applied data. The preamplifier 26a is provided for the memory cell array block 10a, and similarly the preamplifier 26a is provided for the memory cell array block 10a.
6b to 26d are memory cell array blocks 10, respectively.
It is provided corresponding to b to 10d.

In order to write data, an input buffer 2 receives externally applied write data Din, shapes the waveform, and generates mutually complementary internal write data Din, Din, for example.
8, a write buffer 30 that generates an internal write instruction signal W in response to the write instruction signal W, and an input buffer 728 that is turned on in response to the internal write instruction signal W from the write buffer 30. Write gates 32 are provided for transmitting internal write data Din, Din from the memory to internal data bus lines DB, DB. The write gate 32 receives internal write data Din.
A transfer gate transistor T'10 transmits complementary internal write data Din to an internal data line DB, and a transfer gate transistor Tr9 transmits complementary internal write data Din to a complementary data line DB.

Internal data line DB for data reading.

An output buffer 38 is provided which receives either the data on the DB or the output of the logic operation circuit 34 via the read gate 36 and outputs the received data. The read gate 36 reads internal data lines DB, D in response to a control signal from the test control circuit 40.
Either the complementary pair data of B or the complementary data pair indicating the logical result from the logic operation circuit 34 is selected and applied to the output buffer 38. The output buffer 38 outputs successive data Dout corresponding to the given complementary data pair.

The logic operation circuit 34 receives the data read through the preamplifiers 26a to 26d, performs a predetermined logic operation, and then outputs a logic result consisting of a complementary data pair representing the logic result.

A row address strobe signal RA applied externally as a peripheral circuit for controlling the operation of a semiconductor memory device.
A RAS buffer 42 receives S and outputs an internal control signal RAS, and a word driver 1 generates a word line drive signal WL in response to the internal control signal from the RAS buffer 42.
8 and an activation signal 5O9S for each of the sense amplifiers 12a to 12d in response to a signal from the word driver 18.
A sense amplifier control circuit 44 that generates O and receives a column address strobe signal CAS applied from the outside.
A CAS buffer 46 is provided for generating internal control signals. The internal control signal from the RAS buffer 42 defines the operation timing of the row selection system of the semiconductor memory device. On the other hand, the internal control signal from the CAS buffer 46 defines column selection related operations of the semiconductor memory device.

In order to switch between the semiconductor memory device's functional test mode and the normal 1-bit data output/input mode,
A test control circuit 40 is provided which generates an internal test mode instruction signal in response to an externally applied test mode instruction signal TE.

An internal test mode instruction signal from test control circuit 40 is applied to nibble decoder 22 and read gate 36. When the nibble decoder 22 receives the internal test mode instruction signal, the nibble decoder 22 turns on all the transfer gate transistors Trl to Tr7 of the selection gate 24.

Read gate 36 transmits the output of logic operation circuit 34 to output buffer 38 in response to an internal test instruction signal from test control circuit 40 .

Furthermore, in the above-described configuration, since the configuration within the memory cell array constitutes a folded bit line, complementary data is transmitted in pairs on all signal lines that transmit internal data. Therefore, each memory cell array block 1
At 0a to 10d, the bit line BL is connected to the input/output data line I10, and the complementary bit line ■τ is connected to the complementary input/output data line T10. Similarly, internal data line DB is connected to data input/output line I10, and complementary internal data line DB
is connected to complementary internal data input/output line I10. Next, the operation of this semiconductor memory device will be briefly explained with reference to FIG. First, a description will be given of an operation mode in which data is normally output in 1-bit units.

In dynamic random access memory,
Generally, row addresses and column addresses are applied to address input terminals (AO to A9 in FIG. 2) in a time-division manner. The row address and column address given in this time division are RAS
Buffer 42. Under the control of CAS/< buffer 46,
They are taken in at the timing of falling edges of row address strobe signal RAS and column address strobe signal CAS, respectively, and internal row address signals RAO-RA9 and CAO-CA9 are generated. address buffer 1
The 10-bit row address signal RAO~R generated in
9-bit internal row address signal RAO to RA of A9
S is given to row decoders 16a to 16d. Row decoders 16a-16d decode the applied internal row address signals RAO-RAS and select the corresponding word line. After the word line selection operation of the row decoders 16a to 16d is finalized, a word line drive signal WL is generated from the word driver 18 and transmitted onto the selected word line. This activates the selected word line. As a result, during the data read operation, information stored in the memory cells MC connected to the selected word line is transmitted onto the bit line BL (or BL). According to this read storage information, the potential of the bit line BL (or BL) changes slightly, while the bit line BL (or BL) paired with it changes slightly.
Since the potential on the bit line pair BL and BL does not change, a potential difference occurs between the bit line pair BL and BL. Next, in response to a sense amplifier activation signal from the sense amplifier control circuit 44, each of the sense amplifiers 12a to 12d is activated, and the potential difference generated in each bit line pair is amplified. - On the other hand, a unit column decoder among column decoders 20a-20d is selected by internal column address signals CAO-CA8, and the corresponding bit line pair BL is selected.

Mini is the data input/output line I10. Connected to I/δ. Through this series of operations, memory cell array block 10a
10d, 1-bit memory cell MC is connected to data output lines 1101, 1/-6-1 to l104. l1
04, and then to preamplifiers 26a to 26d. Preamplifiers 26a to 26d each further amplify the provided information. The most significant address bit RA of the internal address signal generated by address buffer 14
9, CA9 is given to the nibble decoder 29.

The nibble decoder receives the applied highest internal address signal RA9. In response to CA9, only one of the four outputs is selected and applied to selection gate 24. As a result, only one set of transfer gate transistors among the transistors Tri to Tr8 included in the selection gate 24 is turned on, and the preamplifier output connected to this transistor pair turned on is transmitted to the internal data lines DB, DB. be done.

In normal 1-bit operation mode or high-speed serial access mode such as nibble mode, test mode instruction signal TE is not generated, and test control circuit 40 controls read gate 36 and output buffer 38 internally. Connected to data lines DB and DB. Therefore, the complementary data pair transmitted to internal data line DB--DB is applied to output buffer 38, converted into 1-bit data, and then outputted from output buffer 38 as read data Dout.

During the data read operation described above, the write control signal W is “
H" level, the write gate 32 is in a non-conductive state, and the external manual buffer 28 is connected to the internal data lines DB, D.
It is not connected to B.

During a data write operation, external write control signal W goes to "L" level, input buffer 28 is activated, and write gate 32 becomes conductive. As a result, the write data Din generated by the manual buffer 28
A complementary input data pair Din, Din corresponding to the internal data line DB.

It is transmitted onto the DB. The complementary data pair transmitted onto the internal data lines DB, DB follows a route opposite to that in the data read operation described above and is transmitted to the selected memory cell, thereby writing input data. The above is an outline of the data read or write operation in one memory cycle.

In the nibble operation mode, internal address RA9.
In response to CA9, a 1-bit memory cell (more precisely, one preamplifier) is selected by the nibble decoder 22.
Data is written to or read from the selected memory cell via the preamplifier selected by nibble decoder 22. Then, the signal RAS is set to the active state “L”.
By sequentially toggling the external column address strobe signal CAS while maintaining the level, the nibble decoder 22 sequentially turns on the sets of transfer gate transistors in the selection gate 24. As a result, the preamplifiers 26a to 26d sequentially connect to the internal data lines DB and DB.
When viewed from outside the memory device, memory cells from memory cell array blocks 10a to 10d are sequentially accessed bit by bit, and data in the memory cells is written or read.

During the functional operation of the semiconductor memory device, a test mode instruction signal TE is generated, and under the control of the test control circuit 40, the nibble decoder 22 turns on all the transfer gate transistors Tri to Tr8 in the selection gate 24. . At the same time, the successive gate 36 selects the logic operation circuit 34 as the output buffer 738. In this functional test mode, complementary internal write data Din and Din applied via the input buffer 28 are simultaneously transmitted to the selected memory cells of the four memory cell array blocks 10a to 10d and written therein. In rare cases, when reading data, 4-bit memory cell data is applied to logic operation circuit 34 via preamplifiers 26a to 26d. The logic operation circuit 34 receives the applied 4-bit (to be exact, 8 bits because it is a complementary data pair) data, performs a predetermined logic operation, and then outputs data representing the result of the logic operation. Output buffer 38 is read gate 3
6, and outputs the corresponding read data Dout.

The above is an outline of the data read or write operation in one test cycle, and it will be explained in more detail below, focusing on the configuration of the memory cell array section.

FIG. 3 is a diagram more specifically showing one main part of the memory cell array block of the semiconductor memory device shown in FIG. 2. The configuration shown in FIG. 3 includes a memory cell array corresponding to 256 bits, a sense amplifier, and a data output line I1.
0. Contains I10. In FIG. 3, 512 word lines WL1 to WL512 are provided, and 512 word lines WL1 to WL512 are arranged perpendicularly to the 512 word lines WLI to WL512.
L512 is provided. Word line WLI and bit line BL
A memory cell MCI is provided at the intersection with the word line WL2 and the complementary bit line BLI.
C2 is provided. Similarly, a memory cell MC511 is provided at the intersection of the word line WL511 and the bit line BLI,
A memory cell MC512 is provided at the intersection of word line WL512 and complementary bit line BLI. In other words, one memory cell is arranged at the intersection of one word line and one of the bit lines of one bit line pair, forming a folded bit line. A total of 512 memory cells are arranged on the bit line pair.

Memory cell MC (representative memory cell) is ↑n
It is composed of a capacitor CO that stores information in the form of charge, and a transfer gate transistor QO that turns on in response to a word line potential and connects the capacitor CO to the corresponding bit line BL (or BL). Transfer gate transistor QO is configured using, for example, an n-channel MOS transistor. The memory cell capacitor CO has, for example, a MOS (metal-insulating film-semiconductor) structure. One electrode of the memory cell capacitor CO is connected to a power source that outputs a predetermined constant voltage Vcp (for example, 1/2 the value of the operating power supply voltage Vcc) generated on the semiconductor chip on which the semiconductor memory device is provided. be done.

Each bit line pair BL is provided with a sense amplifier 2 for sensing and amplifying the potential difference on the bit line pair. Sense amplifier 2 includes p-channel MOS transistors Q3. Q4
a pMOS sense amplifier section with a flip-flop type configuration, and n-channel MOS transistors Ql, Q2.
and a flip-flop type nMOS sense amplifier section. A node N1 of the nMOS sense amplifier section is connected to a signal line SN. Node N2 of the pMOS sense amplifier section is connected to signal line SP.

The gates and drains of the transistors Ql and Q2 are cross-connected, and their sources are connected to the signal line SN. Similarly, transistor Q3. The gate and drain of Q4 are cross-connected, and the source thereof is connected to the signal line SP. A sense amplifier activation circuit 6 is provided to activate the sense amplifier 2. The sense amplifier activation circuit 6 turns on in response to the sense amplifier activation signal SO, and connects the n-channel MOS transistor QIO that connects the signal line SN to the ground potential level, and the sense amplifier activation signal y in response to the sense amplifier activation signal y. A p-channel MOS transistor Q11 is turned on and connects the signal line SP to the operating power supply potential Vcc level. Therefore, when the sense amplifier 2 is activated, the nMOS sense amplifier section discharges the low potential bit line potential in the corresponding bit line pair to the ground potential, and the pMOS sense amplifier section discharges the low potential bit line potential in the corresponding bit line pair. The potential of the bit line is set to the operating power supply potential Vc.
Charge to C level.

An equalize/hold circuit 4 is provided to hold each bit line pair potential at a predetermined potential V during standby. The equalize/hold circuit 4 receives an equalize signal E
An n-channel MOS transistor Q8 turns on in response to the equalization signal EQ and connects the bit line BLI to the signal line LBL, and an n-channel MOS transistor Q8 turns on in response to the equalization signal EQ and connects the complementary bit line BLI to the signal line Lat. M
It includes an OS transistor Q9 and an n-channel MOS transistor Q7 that turns on in response to an equalize signal EQ and connects bit lines BLI and BL1. The hold voltage V[IL is applied to the semiconductor memory in order to maintain the externally applied row address strobe signal RAS at the aHIll level (that is, in standby mode!) at the voltage equalization level (for example, Vcc/2) of each bit line. It is the voltage generated on the semiconductor chip on which the device is mounted.

In response to an external column address, the corresponding bit line pair is connected to data input/output 9110. An I10 gate 3 is provided for connection to I/σ. I10 gate 3 outputs column decoder output Y (column selection signals Y1 to Y512 are typically shown)
The n-channel MOS (n-channel MOS) transistor Q5 turns on in response to the input signal Y and connects the bit line BL1 to the data input/output line 110, and the transistor Q5 turns on in response to the column selection signal Y and connects the complementary bit line BLI to the complementary data input/output line 110. 7σ (n-channel MOS) transistor Q6.

A block 5 indicated by a dashed line in FIG. 3 includes a memory cell MC, a sense amplifier 2, an equalize/hold circuit 4, and an I10 gate 3 connected to one bit line pair.
This is a 512-bit cell array including: In a memory cell array of 516 bits, this block 5 is
Twelve unit column decoders are arranged in parallel, and 512 unit column decoders are arranged for these 512 blocks 5. Here, 256 bits represent 262 144 bits. Next, the operation of one cycle in the memory cell array block shown in FIG. 3 will be explained with reference to FIG. 4, which is a timing chart thereof.

Equalize signal EQ is a signal substantially synchronized with externally applied row address strobe signal RAS, and is at "H° level" before time t1.

In this state, the row address strobe signal RAs is “H”.
"level state, that is, the standby state of the semiconductor memory device. In this state, all transistors Q7 to Q9 in the equalize/hold circuit 4 are in the on state, and each bit line pair BL, BL The potential of is equal to Vcc/2.This precharge (
Basically, in the previous operation cycle, one of the bit line BL or complementary bit line BL is at the operating power supply potential Vcc, and the other bit line is at the ground potential, and at the end of that cycle, the equalize transistor Q7 is turned on. Since this is achieved by being in a conductive state, there is no need to supply a potential of Vcc/2 from the hold power supply potential VaL. However, if the standby state continues for a long time, transistor Q8. Each bit line BL via Q9
.

A hold potential VBL is supplied to τ. That is, the power supply VBL is a power supply potential for holding the bit line potential.

First, the read operation will be explained. When the row address strobe signal RAS goes to the "L" level near time t1 and the equalize signal EQ similarly goes to the "L" level, the transistors Q7 to Q9 in the equalize/hold circuit 4 turn off, and the bit line pair BL i , BL i
(i-1 to 512) are in a floating state. On the other hand, at this time, as described above, an address from the outside is taken into the memory device at the falling edge of the row address strobe signal RAS and is applied to the row decoder. As a result,
One unit decoder among the row decoders is selected.

At time t2, the word line drive signal WL is activated.
When it rises to H'' level, 512 word lines WL1~
One word line connected to the selected unit row decoder among the WLs 512 is selected, and its potential becomes 'H# level. As shown in FIG. 3, one memory cell MC is selected for one word line in one block 5, and 51 memory cells MC are selected for 512 bit line pairs.
Two memory cells are connected to this selected word line. Therefore, 512 memory cells are selected according to the selection of one word line. As a result, the charge stored in each selected memory cell is transmitted onto the bit line BL or BL. usually,
Since the ratio between the capacitance value CO' of the memory cell capacitor CO and the capacitance C[IL of the bit line is about 1:10,
The potential change on the bit line due to memory cell data reading is as small as about 1/10 of the operating power supply potential Vcc.

If the selected memory cell is currently storing an H" level and is connected to the bit line BL, the potential of the bit line BL will be slightly lowered as shown by the solid line in the operating waveform diagram of FIG. On the other hand, since the selected memory cell does not exist, the potential of the complementary bit line BL is V c c
/ remains at 2.

Next, at time t3, when the sense amplifier activation signal SO goes to the "H" level and the sense amplifier activation signal ■ goes to the "L" level, the common source line (signal line) SN goes to the "L" level.
level, the signal line SP becomes "H" level, and the nMOS sense amplifier consisting of transistors Ql and Q2 and transistors Q3. The 9MOS sense amplifier consisting of Q4 is activated and amplifies the potential of the bit line BL to the "H#" level and the potential of the complementary bit line BL to the "L" level.

At this point, 512 sets of sense amplifiers provide 5
Each of the 12 bit line pairs changes to the "H" level or the "L" level according to the stored information of the 512 selected memory cells.

At time t4, an internal column address is given to the column decoder, one unit column decoder included in the column decoder is selected, and when its output Yi becomes "H" level, 512
One of the bit line pairs is connected to data input/output lines I10 and Ilo via I10 gate 3. As a result, the potential levels of the data input/output lines I10 and Ilo, which were previously held in a floating state, change to the "H" level or "L# level" depending on the level of the connected bit line pair.After this, As described above, after being further amplified by the preamplifier connected to the data output line I10.I10, it is applied to the output buffer, and the H'' level output data Dout is outputted via this output buffer.

When the potential of the selected word line (word line WL1 is shown selected in FIG. 4) falls to "L" level at time t5, the selected memory cell and bit line BL ( or IL) are electrically disconnected.

At time t6, when the sense amplifier activation signal SO1 becomes the "L" level and the "H" level, and the equalize signal EQ becomes the "H" level, the bit line pair BL and BL- are each equalized and their potentials becomes the level of Vcc/2, and enters a standby state in preparation for the next cycle.

This completes one memory cycle (operation cycle). On the other hand, the amplified potential level on the bit line BL (or ■) between times t3 and t5 is transmitted to the selected memory cell, and this potential level is rewritten into the selected memory cell. .

When the selected memory cell stores the "L0" level, a signal change indicated by a broken line in FIG. 4 is applied, and the read data from the data output buffer becomes "L" level.

Next, in the write operation, data input/output lines I10. If the level of I10 is set to "H" or "L" level in advance instead of floating, the data input/output line I
10. Since I10 and the selected bit line pair are connected, at this point, the potential on the selected bit line pair becomes the potential level corresponding to the write data, and the selected memory cell also has this potential. The level will be written.

It should be noted here that in the above configuration, the bit line BL is connected to the data input/output line I10, and the complementary bit line BL is connected to the complementary data input/output line I10. Therefore, a memory cell (for example, a word line W
(memory cell connected to L2) has a value opposite to the write data Din (for example, "L" for "H" level)
Even when a potential level) is written and data continues to be written, a data value opposite to the potential level written to that memory cell is read out from the output buffer as data D.
This means that it is output as out. in this case,
Since data with a value opposite to the write data is written to the memory cell, and data with a value opposite to the stored information is read when reading data, from the outside of the semiconductor memory device, the written data is This is the same as reading the value itself, and no problem occurs. Further, in a normal semiconductor memory device, since memory cell array blocks have the same configuration, only memory cells connected to bit line BL or only memory cells connected to complementary bit 1iI8L are selected at the same time.

Next, the operation of the semiconductor memory device in test mode will be explained. In this case, test mode instruction signal TE is “
The signal becomes H'' level and is applied to the test control circuit 40.

A test mode control circuit 40 controls the nibble decoder 22, and controls the nibble decoder 22 regardless of the values of the internal row address signal RA9 and the internal column address signal CA9.
all outputs are set to "H" level at the same time. As a result,
All of the transistors Tri to Tr8 of the selection gate 24 become conductive. During data writing, the data transmitted to the selection gate 24 is transferred to the memory cell array block 1.
A total of 4 bits of memory cells respectively selected in 0a to 10d are all selected simultaneously, and the same data is written to each 4 bits of memory cells in the same manner as described above.

This reduces the time required for data writing to 1/4 compared to the method of accessing memory cells in units of 1 bit.

On the other hand, when data is being continuously output, the test control circuit 40 causes the successive output gate 36 to connect the output of the logic operation circuit 34 to the output buffer 738 . As a result, the 4-bit data read in the same manner as in the read operation described above is transmitted via the preamplifiers 26a to 26d, and this 4-bit memory cell information is then transmitted to the logic operation circuit 34, where it is transmitted. After being subjected to logical operation processing, it is applied to an output buffer 38 via a read gate 36. The output buffer 38 amplifies the output of the logic operation circuit 34 and outputs read data Dout corresponding to the result of this logic operation.

This allows you to access memory cells in 1-bit units,
The time required for reading data is also reduced to 1/4 compared to a method that performs a functional test. As described above, in this test mode, it is possible to simply shorten the test time to 1/4 compared to the conventional 1-bit unit method.

As for the configuration of this logic operation circuit 34, in the above-mentioned prior art document, a simplified configuration is shown in FIG. 5A, and a circuit configuration that provides a truth value as shown in FIG. 5B is used. It is being Referring to FIG. 5A, logic operation circuit 34 inputs 4-bit memory cell data MO-
It includes an AND gate M1 receiving M3, and an AND gate A2 receiving inverted data MO to M3 of 4-bit memory cell data. The output buffer 38 has an operating power supply potential Vc
The n-channel MOS transistor TR2 is connected to the ground potential. The output of AND gate A1 is applied to the gate of transistor TRI, and the output of AND gate A2 is applied to the gate of transistor TR2. Read data Dout is output from the connection point between transistors TR1 and TR2. In the configuration of FIG. 5A, read data MO-M3 corresponds to data transmitted via data output lines l101 to l104, and MO-M3 corresponds to data transmitted via data output lines 1101 to 1104. Compatible with data. In the truth table shown in FIG. 5B, the case where the selected memory cell outputs the "L'" level is "0", and the case where the selected memory cell outputs the H level is "1". As is clear from the truth table shown in FIG. 5B, when the logical operation circuit shown in FIG. 5A is used, if all selected 4-bit memory cells output "0" In this case, the data Dout becomes "0", and similarly, if the read data is all 1, the read data Dout becomes 1'.In addition, if even 1 bit of the read data differs, the read data Dout becomes "0". The output data DOut is in a high impedance (Hi-Z) state.

This method is usually called a ternary output method. As mentioned above, since the same data is written to 4-bit memory cells at the same time, if the memory cells are functioning normally, all the data output by the 4-bit memory cells that are read out will be the same. .

Therefore, in this three-value output power formula, the memory cell does not output output data (high impedance state) unless it is functioning normally, so it is easy to detect defects by inspection equipment, especially during unit testing. . Furthermore, even if all of the selected 4-bit memory cells are defective, the values will be output as they are, and the output data can be easily viewed with the inspection equipment.
All of these defective states can be detected.

Now, let us consider the case where a semiconductor memory device according to this three-value output formula is mounted on a memory board after a unit test. Usually, multiple DRAMs are mounted on a memory board, etc. In this case, the data output terminal is provided with a pull-up resistor to reliably transmit the output data, and this pull-up resistor is normally connected to the operating power supply. Potential Vcc
It is connected to the. Therefore, when performing a functional test using the three-value output formula described above when mounted on a board, the high impedance state becomes "H" level due to this pull-up resistor, making it difficult to accurately perform a functional test of a semiconductor memory device. The problem arises that it becomes difficult.

Therefore, for example, IEE
E. Die Shed of Technical Papers 19
On pages 12 and 13 of 1987, Machiko et al.
Mb DRAM ina 300m
A binary output power formula that does not include this high impedance state has been devised, as proposed in il DIP)'. As shown in FIGS. 6A and 6B, which show circuit configuration examples and truth tables, this binary output output formula shows that, for example, when all 4-bit memory cells output the same data, the output data Dout is 1''. If even one bit of the memory cell is defective and the output data is different, "0" is output as the output data Dout.This method is about to be standardized for 4 megabit DRAM. There is.

Here, FIG. 6A is a diagram showing a simplified configuration example of the logical operation circuit of the binary output type, and FIG. 6B is a diagram showing the truth table thereof. Referring to FIG. 6A, the binary output type logical operation circuit 34 outputs 4-bit memory cell data M.
AND gate A3 that receives outputs O to M3, and AN that receives inverted data MO to M3 of 4-bit memory cell data.
D gate A4 and AND gate A3. It includes an OR gate 01 that receives the A4 output, and an inverter 11 that inverts the output of the OR gate 01. The output of OR gate 01 is applied to the gate of transistor TR1 included in output buffer 38, and the output of inverter 11 is applied to the gate of transistor TR2 included in output buffer 38.

[Problems to be Solved by the Invention] As described above, although memory cells of multiple bits are accessed simultaneously and the functional test of the memory cells is performed in units of multiple bits, the functional test is shortened. In a conventional semiconductor memory device having a binary output type test mode, the following problems occur. In other words, if all 4-bit memory cells selected at the same time are defective, for example, even though all "1"s have been written to these 4-bit memory cells, reading from these 4-bit memory cells will not be possible. Even if the data is “0”, as shown in FIG. 6B, this output data D
out becomes "1", and this semiconductor memory device has the disadvantage that it is judged to be a good product (bus).

If such a memory cell defect is a fixed defect such as a pattern defect that occurs during the manufacturing of a semiconductor memory device, all bits can be tested in advance according to the normal mode (1-bit unit access) test. Memory cells with such defects can be removed. Of course, in this case, the effect of shortening test time is reduced.

However, if such a problem occurs during a test for examining operating margins such as timing margins and voltage margins, it becomes impossible to perform this functional test in test mode. Here, the timing margin is a margin that indicates whether the semiconductor memory device operates accurately no matter how much the operation timing of the control signal shifts, and the voltage margin is the margin that indicates how much the semiconductor memory device operates accurately no matter how much the operating power supply voltage fluctuates. This is the margin that indicates whether the system operates normally. An example of such a functional test is a refresh margin test.

As mentioned above, in a DRAM memory cell, information is stored as "1" in the memory cell capacitor (MOS capacitor).
(corresponds to "H" level) or "0" (corresponds to 'L' level).In particular, when this "1" is stored, the state where the potential is at H level is stored in the memory. The capacitor section is in a depleted state with no electrons, and is thermally non-equilibrium. Therefore, if this memory cell is kept in an unaccessed state (standby state) for a long time, the inside of this capacitor will gradually increase due to, for example, junction leakage (leakage at the junction between the semiconductor substrate and the impurity region that constitutes the capacitor part). Electrons are collected and the stored information changes to a "0" state. Therefore, it is necessary to read and rewrite the stored information in each memory cell at regular intervals. This operation is usually called refresh. The refresh margin test is a test to determine whether the memory cell retains correct information no matter how long the time between one refresh and the next refresh is extended. In this refresh margin test, a memory cell defect occurs only when "1#" is stored in the memory cell, and a defect occurs in a memory cell that stores "0" (memory capacitor filled with electrons). In other words, in this refresh margin test, only the 111+1→“0#” error of the memory cell occurs. Problems that may occur in the refresh margin test will be explained in detail below. For example, all bits of memory cells in a semiconductor memory device are set to “1”.
Assume that a test is performed in which data is written, held in a standby state for a certain period of time (this time is called the data retention time), and then read out. While the data retention time is short,
Although the data in each memory cell is correctly held, if this data holding time is made too long, the memory cell data will be inverted and a memory cell defect will occur. In other words, a 1"→'0" error occurs in the memory cell. However, when this test is performed in the binary output output test mode, even if all the selected memory cells cause an error from "1" to "0#", the output of the selected 4-bit memory cell is Since they all match, this output data Dout becomes "1" according to the truth table shown in FIG. 6B, and this semiconductor memory device is determined to be a good product.

Furthermore, problems that may occur in the voltage margin test will be explained with reference to FIGS. 7A and 7B.

Now, for example, every memory cell of a semiconductor memory device has 1"
Let us consider the case where a test is performed by writing 20 times the written data and reading out the written data by changing the operating power supply voltage.

In this case, it is necessary to check that the semiconductor memory device operates normally at an operating power supply potential within the range of 4.5 volts to 5.5 volts guaranteed by the standard. Now, in the normal mode (1-bit unit access) test, as shown in FIG. 7A, operation type I! Assume that there is a semiconductor memory device that malfunctions when the potential is below 4°75V. In other words, simply put, at an operating power supply voltage of 4.75V or less, the operating margin for "1" is small, and even if data "1" is written to a memory cell, "0" will be output from that memory cell. do. When this semiconductor memory device is tested in a binary output output test mode, as shown in FIG. 7B, when the operating power supply potential is 4.75V or higher, even when data "1" is written, each memory cell Since it outputs data of "1", it is determined to be a good product and no problem will occur. However, if "1" is written to a memory cell at an operating power supply potential of 4°5V or less, all selected memory cells will be "0°".
Therefore, according to the truth table shown in FIG. 6B, the output data Dout becomes "1m", and this semiconductor memory device is determined to be a good product.

Here, in FIG. 7B, there is a transition region that exists between the case where all memory cells are defective and the case where all memory cells are good (i.e., some memory cells operate correctly and some 7B (a region that would be defective) is exaggerated in FIG. 7B, and is a region that would not exist in an ideal state in which all memory cells are formed identically.

At the time of actual shipping inspection of semiconductor memory devices, in order to shorten the test time, the function test is not performed many times by changing the operating power supply voltage as described above, but rather, for example, if the operating power supply voltage is 4. Perform a functional test using only one point of 3V.

Therefore, a problem arises in that a semiconductor memory device that is determined to be a defective product in the normal mode functional test as shown in FIG. 7A is determined to be a non-defective product as shown in FIG. 7B.

Therefore, the present invention eliminates the drawbacks of the above-described conventional semiconductor memory device with a test mode, and provides a semiconductor memory device with a functional test mode that can accurately determine whether the semiconductor memory device is good or bad. It is to be.

A specific object of the present invention is to provide a semiconductor memory device with an improved binary output type test mode.

[Means for Solving the Problems] A dynamic semiconductor memory device according to the present invention has a test mode operation in which a function test is performed in units of a plurality of predetermined number of memory cells, and in this test mode, a predetermined number of memory cells are tested. means for simultaneously selecting, means for receiving write data from the outside, and operatively coupled to the means for receiving write data to simultaneously select at least one memory cell of the selected predetermined number of memory cells; means for writing data with the value of the write data inverted, and writing data having the same value as the value of the write data into the remaining memory cells of the selected predetermined number of memory cells; accesses a predetermined number of memory cells that have been selected, inverts and reads the stored data of the memory cells to which the inverted data has been written, and reads the stored data of the remaining memory cells of the selected predetermined number of memory cells as is. The device includes reading means, and means for receiving the output of the reading means in this test mode and outputting a logical value corresponding to the received output data.

[Operation] In the dynamic semiconductor memory device according to the present invention, data in which the value of the write data is inverted is written to at least one of a predetermined number of memory cells selected at the same time, and data that is the inverted value of the write data is written to the remaining memory cells. write data is written, and at the time of successive writing, the memory cell data to which this inverted data has been written is inverted, and the remaining memory cell data is read out as is. Therefore, even if one selected memory cell is defective and its memory information is reversed, the defective memory cell information can be reliably detected, and the functional test of the semiconductor memory device can be accurately performed using multiple bits. It can be done in units.

[Embodiments of the Invention] The structure of a dynamic semiconductor memory device which is an embodiment of the invention will be described below with reference to FIG. In the configuration shown in FIG. 1, the conventional IMD shown in FIG.
The configuration of the RAM and the corresponding configuration are shown, and the second
Portions corresponding to those of the semiconductor memory device in the figure are given the same reference numerals. As is clear from referring to FIG. 1 and FIG. 2, in the dynamic semiconductor memory device which is an embodiment of the present invention shown in FIG.
As shown by 0a to 100d, the connections between the bit line pairs BL and BL included in each memory cell array block 10a to 10d and the corresponding data input/output lines I10°Ilo are different. That is, memory cell array blocks 10a, 1
In 0b and 10d, bit @iBL is connected to data input/output line I10, and complementary bit line BL is connected to complementary data input/output line I10. On the other hand, in the memory cell array block 10c, the bit line BL is connected to the complementary data input/output line l103, and the complementary bit line B
L is connected to the data input/output line l103. In each block 10a to 10d, this connection configuration is as follows:
The same is done for all bit line pairs.

That is, in the present invention, in the memory cell array blocks 10a, 10b, and 10d, when the selected memory cell is connected to the bit line BL, the same data as the write data is written in the test mode, and the memory cell array blocks In 10c, a value obtained by inverting the write data value in the test mode is written.

Next, the operation will be explained. First, the operation of writing data during the function test operation will be explained. in this case,
By the nibble decoder 22 and the test control circuit 40,
Memory cells arranged at the same position in memory cell array blocks 10a to 10d are selected. It is assumed that the write data Din to the money receiving buffer 28 is 1 m.

In this case, complementary data of "1" and "0" are transmitted on internal data lines DB and DB. These complementary data pairs are transmitted to data input/output lines 1101.l101.1104, Suppose that a memory cell connected to the bit line BL is selected in each memory cell array block.In this case, memory cell array blocks 10a, 10b, 10d
In , “1” is written to the selected memory cell,
On the other hand, data of "0°" is written in the selected memory cell in memory cell array block 10c.

That is, memory cell array blocks 10a, 10b,
10d, the data input/output line l101. l101.
l102. ! / Seiding, l104.1104. ``1'' data is transmitted onto the bit line BL, and ``0'' data is transmitted onto the complementary bit line BL.Meanwhile, in the memory cell array block 10c, the connection is switched. Therefore, "0" data is transmitted on the bit line BL, and a "1" level signal is transmitted on the complementary bit line BL.As a result, in the selected memory cell, the data of "1" level is transmitted on the complementary bit line BL. , 10b, 1
0d, data of "1m" is written, and data of "O" is written in the selected memory cell in the memory cell array block 10c. ).In this case, a memory cell becomes defective in the refresh margin test mentioned above, and the data '1' becomes '1'.
Consider the case where the value changes to 01. In this case as well, “
In the memory cells to which Om has been written, the data does not change and remains at "01." Now suppose that a data "1#→"0" error occurs in all memory cells. In this case, the data stored in each memory cell MO to M3 is (0000). Next, when these 4-bit memory cells are simultaneously read at the time of data reading, the memory cell information in the memory cell array block 10c is inverted and read, so the data transmitted on the data input/output lines of the blocks 101 to 1104 is read out. becomes (0010).

This data is applied to the logic operation circuit 34 via preamplifiers 26a to 26d. Therefore, logic operation circuit 3
In step 4, since the data of the selected 4-bit memory cells do not match, this semiconductor memory device is determined to be defective. In other words, in the conventional binary output method test mode, “
Even in the case of 1” → “0m error, it was judged as a good product, but
In one embodiment of the present invention, since all 4-bit memory cell data do not match, it is correctly determined that the memory cell is defective.

In addition, when testing the power supply voltage margin, even in a semiconductor memory device where the margin for "1" is small when the power supply voltage is low, even if the write data Din is "1", at least one memory cell is “0” is written, and the operating power supply voltage margin is small “1”
→ Even if data inversion of “0” occurs in the remaining memory cells and the stored data in the selected 4-bit memory cell changes to (0000), it becomes (0010) when reading that data. The 4-bit memory cell data do not match and can be correctly determined to be defective.

Furthermore, even when a memory cell to be connected to the complementary bit line BLI is selected in the above-described configuration, if the write data Din is "1", this inverted data is written in each memory cell. In this embodiment, data having the same value as the write data is written in one selected memory cell. Therefore, it is possible to accurately detect defects in the semiconductor memory device in the same way as described above.

That is, when the command write data Din is 1'' and the selected memory cell is connected to the complementary bit line BL, the 4-bit selected memory cell data is (00
10), and the “1” data is reversed to “0” and becomes 0.
000), when the data continues to increase, this 4
Since the bit memory cell data is (1101),
Since the 4-bit memory cell data do not match, it is possible to accurately determine the defect.

In the above embodiment, only one bit of the selected memory cells is configured to write data that is different from the write data. at least 1 of them
The same effect as in the above embodiment can be obtained even if the configuration is such that data inverted from the write data Din is written in the bit memory cells, and data with the same value as the write data is written in the remaining memory cells. Can be done.

Further, in the above embodiment, an IM as a semiconductor memory device is used.
Although the configuration of the bDRAM has been shown and the case where the number of memory cells selected at the same time is 4 has been described, instead of this, the number of memory cells selected at the same time in the test mode may be greater or less than this. Effects similar to those of the above embodiment can be obtained.

Furthermore, in the above embodiment, a case has been described in which the memory cells that are simultaneously selected in the test mode are selected one bit from each memory cell array block, but the configuration is not limited to this, and multiple bits can be selected from any memory cell array block. They may be configured to be selected at the same time. Further, in the above embodiment, the bit line pair and the data input/output line I10. Although the connection with I10 was configured to be different in at least one block, instead of this, in the preamplifiers 26a to 26d, the connection path between the data buses DB, DB and the data input/output line 110, Ilo is different in at least one block. Even if the configuration is configured such that switching is performed at , the same effect as in the above embodiment can be obtained.

Further, in the above embodiment, it has been explained that the memory cells selected at the same time are the memory cells connected to the bit line or the complementary bit line BL, but instead of this, at least one of the memory cells selected at the same time is connected to the bit line or the complementary bit line BL. Even if one memory cell is connected to the complementary bit line BL and the other memory cells are connected to the bit line BL, the same effect as in the above embodiment can be obtained.

Further, the present invention is also applicable to a storage device equipped with a test mode of a ternary output method.

Further, in the above embodiment, the test mode instruction signal T
Although the case where E is applied via an external terminal has been described, this test mode instruction signal TE is also a control signal applied from the outside, such as a row address strobe signal R.
Write in which AS, column address strobe signal CAS, and write instruction signal W are set in a specific timing relationship, for example, the write instruction signal is set to "L" level, signal RAS is set to H" level, and signal σAS is set to "L" level.

The internal test instruction signal may be generated when a relationship such as CAS before RAS is satisfied.

Furthermore, in the above embodiment, one pair of internal data input/output lines I10 is provided for one memory cell array block.
．． Although the configuration in which I10. The present invention is applicable even to a configuration in which I10 is connected.

Furthermore, in the above embodiment, the bit lines BL and the complementary bit lines BL are regularly arranged in this order from the top to the bottom in FIG. 3 in each memory cell array block. Although the arrangement of the bit lines is not limited to this, it is possible to use bit lines in which the arrangement order of the bit lines BL and complementary bit lines BL is different, for example, BL, BL, BL, BL. The present invention is also applicable to a line array configuration, and the same effects as in the above embodiment can be obtained.

In addition, the present invention is not limited to the specific configuration shown in the above embodiments, and various modifications and changes can be made without departing from the spirit of the present invention.

[Effects of the Invention] As described above, according to the present invention, among a predetermined number of memory cells selected simultaneously in the test mode, at least one memory cell has the value of written data inverted during data writing. When data is written, data of the same value as the written data is written in the remaining memory cells, and when reading, the information of the memory cells to which this inverted data is written is inverted and read out, Since the remaining memory cells are configured to be read as they are, even if a data inversion occurs from 1" to "0#, it is possible to reliably detect the occurrence of this data inversion, and it has a high defect detection ability. A dynamic semiconductor memory device with an improved test mode can be obtained. That is, according to the present invention, it is possible to obtain a dynamic semiconductor memory device having an improved binary output type test mode with high defect detection ability.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a dynamic semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of a conventional dynamic semiconductor memory device. FIG. 3 is a diagram specifically showing the configuration of a main part of a memory cell array section in a conventional dynamic semiconductor memory device. FIG. 4 is a waveform diagram showing the operation of the semiconductor memory device shown in FIG. 3. FIGS. 5A and 5B are diagrams showing the configuration and truth table of a three-value output type logic operation circuit that simultaneously performs a functional test on a plurality of bits of memory cells of a dynamic semiconductor memory device. The figure shows an example of a specific configuration of this logical operation circuit, and FIG. 5B is a diagram showing a truth table of the input/output relationship. 6A and 6B are diagrams showing a binary output type logic operation circuit of a dynamic semiconductor memory device and its input/output truth table, and FIG. 6A is an example of a specific configuration of the logic operation circuit. , and FIG. 6B is a diagram showing a truth table of the person's output. Figures 7A and 7
Figure B is a diagram for explaining the problems of a power supply voltage margin test in a semiconductor memory device with a conventional binary output type test mode, and Figure 7A is a diagram in a normal mode in which a functional test is performed in units of one bit. FIG. 7B is a diagram schematically showing a pass/fail determination, and FIG. 7B is a diagram schematically showing a pass/fail determination operation in a test mode in which a test is performed in units of multiple bits. In the figure, 10 is a memory cell array, 10a to 10d.
is a memory cell array block, 2.12a to 12d are sense amplifiers, 14 is an address buffer, 16a to 16d
is a row decoder, 22 is a nibble decoder, 24 is a selection gate, 26a to 26b are preamplifiers, 28 is an input buffer, 34 is a logic operation circuit, 36 is a read gate, 38 is an output buffer, 100a to 100d are bit line pairs BL,
Br and data input/output line I10. A memory in which data inverted from the write data is written in at least one block, the same data as the write data is written in the remaining memory cells, and this inverted data is written in the read operation. The connection for inverting and outputting the stored information of cell data and reading the remaining memory output data as is is shown. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

What is claimed is: A dynamic semiconductor memory device including a memory cell array consisting of a plurality of memory cells each storing information, the semiconductor memory device comprising a predetermined number of memory cells of a plurality of bits in the memory cell array. are simultaneously selected, information is simultaneously written to the selected predetermined number of memory cells, and after this writing, information stored in the predetermined number of memory cells is simultaneously read, and based on the read information, the semiconductor It is equipped with a test mode operation for determining whether the storage device is good or bad, and includes means for generating a signal instructing the test mode, and means activated in response to the test mode instruction signal and responsive to an externally given address. means for simultaneously selecting the predetermined number of memory cells from the memory cell array; means for receiving externally applied write data; operatively coupled to the write data receiving means; Writing data that is an inversion of the write data value into at least one memory cell among the memory cells, and writing data with the same value as the write data into the remaining memory cells of the selected predetermined number of memory cells. accessing the selected predetermined number of memory cells, inverting and reading the stored data of the memory cells to which the inverted data has been written, and reading the stored data of the remaining memory cells; A dynamic semiconductor memory device comprising means for reading data as is, and means activated in response to the test mode instruction signal, receiving output data from the reading means, and outputting a logic value corresponding to the received data.