JPH02135932A - Inter-channel synchronizing system - Google Patents

Abstract

PURPOSE:To reduce the scale of a device by providing a control signal bus between channels, and taking synthronism by performing the transfer of a timing signal. CONSTITUTION:A fast clock is generated by a fast synchronizing signal generating means 6, and is converted to a 1/n fast clock by the number (n) of a low speed part, and is sent to each of the low speed parts 110 1n0. Slow clocks are generated at the low speed parts 110-1n0 by synchronizing signal generating means 21-2n, however, no synchronism is taken. The synchronism of all the low speed parts 110-1n0 can be taken by using the timing signal generated first out of (n) low speed parts 110-1n0 as a reset signal to take the synchronism of the slow clock, and resetting the synchronizing signal generating means 21-2n of another slow speed part by synchronizing signal recovery means 31-3n. In such a way, the scale of the device can be compressed.

Description

[Detailed Description of the Invention] [Summary] Regarding a low-speed clock synchronization method when a digital multiplexer used for digital communication has a multiplexing circuit in the low-speed section, a control signal bus is provided between channels, and the timing A first multiplexing means for multiplexing low-speed data; synchronous signal generating means for generating a synchronous signal;
A low-speed section consisting of a synchronization signal recovery means for synchronizing the synchronization signal generation means, a control signal bus section for transmitting and receiving timing signals with the low-speed section, and a predetermined channel multiplexing of the low-speed channels sent from the low-speed section. a second multiplexing means;
1/n high-speed section consisting of high-speed synchronization signal generation means for sending a high-speed clock to the low-speed section, and the pulse of the low-speed section that first generated the timing signal among the n channels is used to restore the synchronization signal of the other low-speed sections. By starting up and resetting the synchronization signal generating means, all channels are configured to be synchronized from the next cycle.

[Industrial application field]

The present invention relates to a method for synchronizing low-speed clocks when a multiplexing circuit is provided in the low-speed section of a digital multiplexer used for digital communications.

For example, when communicating over a 1.5 Mbps digital line, 24 channels of 64 kbps can be obtained.

When multiplexing and transmitting low-speed data to the second 64 kbps channel, it is necessary to synchronize the low-speed clocks in order to use a common clock in addition to matching the leading bits of the data.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and its configuration is as follows: low-speed multiplexing circuits 11a to lna for multiplexing low-speed data.
, buffer memories 41a to 4na that temporarily store data multiplexed by the low-speed multiplexing circuits, and buffer memories 41a to 4na that generate synchronizing signals and transmitting the synchronizing signals to the low-speed multiplexing circuits 11a to lna and data (not shown). A low-speed section 111-1nl consisting of synchronization signal generation circuits 21a to 2na that sends out to the terminals, a high-speed multiplexing circuit 5a that multiplexes the low-speed channels sent from the low-speed sections 111 to 1nl into predetermined channels, and generates a high-speed clock. a high-speed section 301 consisting of a high-speed synchronization signal generation circuit 6a; a high-speed synchronization signal frequency division circuit 7a that frequency-divides the high-speed clock generated by the high-speed synchronization signal generation circuit 6a to generate a 1/n high-speed clock; The clock distribution section 401 includes a low-speed synchronization signal frequency dividing circuit 8a that divides a 1/n high-speed clock to generate a low-speed clock and supplies it to the low-speed sections 111 to lnl.

In such a configuration, n low-speed sections 111 to lnl
It is necessary to synchronize the clock distribution unit 401 to each of the low-speed units 111 to lnl.
/n supplies high-speed clock and low-speed clock,
Synchronization is achieved by operating with clocks from the same clock source.

[Problem to be solved by the invention]

In the conventional example described above, in order to synchronize the n low-speed sections 111 to 1n1, synchronization is achieved by supplying a 1/n high-speed clock and a low-speed clock from the clock distribution section 401. A clock distribution unit 401 for generating clocks and low-speed clocks includes:
The scale of the equipment is large, which poses more of a problem than the cost aspect.

An object of the present invention is to provide an inter-channel synchronization method that can significantly reduce the device size by providing a control signal between channels and transmitting and receiving timing signals to achieve synchronization. .

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 11 to 1n are first multiplexing means for multiplexing low-speed data, 21 to 2n are synchronization signal generation means to generate a synchronization signal, and 31 to 1n are first multiplexing means for multiplexing low-speed data; 3n is a synchronizing signal generating means 21 at a predetermined timing.
110 to 1nO are synchronization signal recovery means for resetting the first multiplexing means 11 to 1n, the synchronization signal generation means 21 to 2n, and the synchronization signal recovery means 31 to 3.
200 is a low speed section consisting of n, and 200 is a low speed section 110 to 1n.
5 is a control signal bus section for transmitting and receiving signals with the synchronization signal recovery means 31 to 3n of O, and 5 is a second multiplexing means for multiplexing the low speed channels sent from the low speed sections 110 to 1n into predetermined channels. 6 is a high-speed synchronization signal generation means for sending a 1/n high-speed clock to a low-speed section, and 300 is a second multiplexing means 5 and a high-speed synchronization signal generation means 6
This is a high-speed section consisting of the following, and by providing such means, it is a means for solving this problem.

This is converted into a l/n high-speed clock by the number n of low-speed sections, and sent to each of the low-speed sections 110 to 1nO.

In each of the low-speed sections 110 to 1nO, the synchronizing signal generating means 21 to
2n generates a low-speed clock, but it is not synchronized.

In order to synchronize this low-speed clock, n low-speed sections 1
Thai old means 31-3 that occurred first among 10-1nO
By resetting with n, all low speed parts 110 to l
It becomes possible to synchronize no.

(Embodiment) The gist of the present invention is shown in FIGS. 2 and 3 below. FIG. 3 shows a time chart for explaining an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Low-speed multiplexing circuits 11a to lna having the same contents as
, buffer memories 41a to 4na, synchronization signal generation means 2
1 to 2n are synchronization signal generation circuits 21b to 2n that are reset and synchronized by the outputs of the OR circuits 51 to 5n.
b. OR circuits 71 to 71 whose inputs are the outputs of the synchronous signal generation circuits 21b to 2nb as the synchronous signal recovery means 31 to 3n;
7n, initial reset circuit 6 that operates when the power is turned on
OR circuits 51-5 whose inputs are the outputs of 1-6n, OR circuits 71-7n, and initial reset circuits 61-6n.
n.

As the second multiplexing means 5, a high-speed multiplexing circuit 5a having the same contents as explained in FIG. In this example, the high-speed synchronization signal generation circuit 6b is configured to include a control signal bus 200 for transmitting and receiving timing signals.

FIG. 3 shows a time chart 1 of the embodiment, in which the final bit is sent onto the control signal bus 200 as a timing signal when dividing a high speed clock to create a low speed clock.

For example, when channel 1 generates a timing signal first, this signal is input to the OR circuits 71 to 7n of the other low-speed sections 112 to 1n2 through the control signal bus 200, and the output is set to "1", and then to "1". are OR circuits 51 to 5
n, its output is set to "1", and the synchronization signal generation circuits 21b to 2nb are reset, so that from the next cycle, the synchronization signal generation circuits 21b to 2nb of all the low speed sections 112 to in2 are synchronized. be done.

Furthermore, when channel 1 is installed first and channel 2 is inserted later, synchronization is performed in the same manner.

〔Effect of the invention〕

According to the present invention as described above, by exchanging timing signals through control signals, it is possible to perform synchronization between channels in the low-speed section, and it is possible to reduce the scale of the device and make it more economical. becomes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a time chart explaining the embodiment of the present invention, and FIG. 4 is a conventional example. A block diagram explaining the following is shown. In the figure, 5 is a second multiplexing means, 5a is a high-speed multiplexing circuit, 6 is a high-speed synchronization signal generation means, 6a and 6b are high-speed synchronization signal generation circuits, 7a is a high-speed synchronization signal frequency dividing circuit, and 8a is a low-speed synchronization Signal frequency dividing circuit, 11 to 1n are first multiplexing means, ], l a to lna are low speed multiplexing circuits, 21 to 2n are synchronization signal generation means, 21a to 2na, 21b to 2nb are synchronization signal generation circuits 31 -3n are synchronization signal recovery means, 41a-4na are buffer memories, 51-5n, 71-7n are OR circuits, 61-6n
is the initial reset circuit, 110~1nO1111-
1nl, 12-12 are low-speed parts, 200 is a control signal bus, and 300.301.302 are high-speed parts, respectively. FIG. 1 is a detailed block diagram explaining the present invention. FIG. 2 is a detailed block diagram explaining the present invention. FIG. 3 is a time chart for explaining the embodiment of the present invention. FIG.

Claims (1)

[Claims] An inter-channel synchronization method of a low-speed clock of a multiplexing device that multiplexes low-speed data in a low-speed section, comprising first multiplexing means (11 to 1n) that multiplexes low-speed data, and synchronization. A low-speed section (110-2n) comprising a synchronization signal generation means (21-2n) that generates a signal, and a synchronization signal recovery means (31-3n) that synchronizes the synchronization signal generation means (21-2n).
1n0), a control signal bus section (200) that sends and receives timing signals to and from the low-speed section (110 to 1n0), and a control signal bus section (200) that transmits and receives timing signals to and from the low-speed section (110 to 1n0);
a second multiplexing means (5) that multiplexes the low-speed channels sent from the low-speed sections (110-1n0) into a predetermined channel; and a high-speed synchronization signal that sends the 1/n high-speed clock to the low-speed section (110-1n0). A high-speed section (
300), the synchronization signal recovery means (31 to 3n) of other low-speed parts are activated by the pulse of the low-speed section (110 to 1n0) that first generated the timing signal among the n channels, and the synchronization signal is restored. An inter-channel synchronization method characterized in that all channels are synchronized from the next cycle by resetting the generating means (21 to 2n).