JPH02133954A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate a fear that a mutual interference is caused between circuit elements even when an operating frequency of an integrated circuit device is high and its operating speed is fast by a method wherein the circuit element divided from an epitaxial layer of a water by using a junction isolation layer are formed. CONSTITUTION:Inside each partial region on a wafer, an n-type epitaxial layer 7 as this partial region is used as a drain region and single n-channel vertical- type field-effect transistors T are formed. Two interference routes exist between circuit elements formed in different partial regions; in the case of this invention, one interference route out of them is formed via a low-concentration impurity semiconductor region 2. Accordingly, in this integrated circuit device, an operating frequency where an impedance value of the first interference route is lowered to a degree generating an interference actually in nearly the same as a frequency for a second interference route or a little higher than that. When the impedance value of the first interference route as a main cause of the interference in a conventional case is increased, it is possible to reduce a that a mutual interference is caused between the circuit elements of the integrated circuit device.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit device in which circuit elements such as transistors constituting an electronic circuit or a group of circuit elements are located in semiconductor regions of a wafer whose potentials are separated from each other. It relates to things that are divided and created.

[Conventional technology]

As is well known, in integrated circuit devices, the component circuit elements are built into an epitaxial layer grown on a substrate, and then a desired circuit is constructed using a connecting film of metal such as aluminum. However, during circuit operation, the terminals of each circuit element are placed at fixed or variable potentials such as power supply potential, ground potential, and intermediate potential. It is necessary to divide the area into sub-areas of , and create a single circuit element or a group of circuit elements with the same operating potential conditions in each area. FIG. 3 shows an example in which a single vertical field effect transistor as a circuit element is fabricated in each molecular iJl region divided from the epitaxial layer by a junction separation method.

In FIG. 3, a p-type buried isolation layer 5 and an n-type buried layer 6 are diffused with high impurity concentration on the surface of a p-type substrate 2, and then an n-type epitaxial layer 7 is grown. The epitaxial layer 7 is formed by deeply diffusing the p-type junction isolation layer 8 with high impurity concentration until it reaches the buried isolation layer 5.
is divided into a plurality of partial regions, and a vertical field effect transistor T is fabricated in each of the partial regions.

The semiconductor layer for each field effect transistor T includes a connection layer 11 with a high impurity concentration for the drain which is deeply diffused in n-type so as to be connected to the buried layer 6, and a p-type semiconductor layer which is diffused in an annular pattern. outer channel forming layer 12 and inner channel forming layer 15. An n-type source layer 16 with a high impurity concentration diffused in an annular pattern is provided in these channel forming layers, and a gate 14 is provided thereon via a gate oxide film 13 as usual. The drain terminal of the transistor is connected from the contact layer 11 to the source terminal S.
is derived from the source layer 16, and the gate terminal G is derived from the gate 14.As can be seen from Figure 0, each partial region divided from the epitaxial layer 7 has a drain of the vertical field effect transistor T built therein. A potential is applied to the terminals. The transistor T constructed as described above is used in a connection as shown in FIG. 2, for example. That is, the drain terminals of both transistors T are connected to the power supply potential point V through the respective loads, and the source terminals S are respectively connected to the ground potential point E where the substrate 2 is placed, and the voltages are applied to their gate terminals G independently. For example, the load is controlled to open or close depending on the control signal.

When the integrated circuit device is used to drive a display panel, the load is on each pixel, and at least several dozen such field effect transistors T are integrated within the integrated circuit device. Since the potential of the drain terminal, that is, the potential of the partial region in which the transistor is built, can vary independently from the power supply potential E to the ground potential S, the Transistors are built one by one.

Of course, depending on the case, a load may be inserted between the source terminal S of each transistor T and the ground potential point E.

[Problem to be solved by the invention]

As mentioned above, if the circuit elements constituting an integrated circuit, such as transistors, are distributed and fabricated in junction-separated partial regions, mutual interference between the circuit elements should not occur during circuit operation, but the circuit operation At higher frequencies (or at higher operating speeds), it is no longer possible to completely prevent interference. This is because dynamic interference can occur between subareas through connection layers and substrates, The relevant equivalent circuit is shown in FIG.

The first interference path is formed between the drain terminals of the two transistors T via the substrate 2, and as shown in the figure, the resistance of the drain contact 1111.

Resistance of buried layer 6, junction capacitance il between buried layer 6 and substrate 2
This is a series CR circuit consisting of a resistor of C and the substrate 2, and its impedance value decreases as the operating frequency increases, making it more likely that interference will occur. The second interference path is formed between the source terminals S of both transistors via the connection layer 8, and is connected to the resistor 1 epitaxial layer 7 of the epitaxial layer 7, which is the resistor 1 partial region of the outer channel forming layer 12. Series C1 of the junction capacitance 1c with the separation layer 8 and the resistance of the junction separation layer 8? Similarly, as the operating frequency increases, the impedance value decreases.

In the circuit connection shown in FIG. 2, the second interference path is short-circuited and does not work, but it may cause interference if a load is connected to the source terminal S side. In addition, although the midpoint of each interference path is grounded directly or via the resistance of the embedded bone M layer 5, if the potential of the drain terminal or source terminal S of each transistor changes independently, Even grounding cannot completely prevent interference, and the current flowing through these interference paths causes interference between circuit elements.

SUMMARY OF THE INVENTION An object of the present invention is to solve this problem and reduce the possibility of mutual interference occurring between circuit elements even when the operating frequency of an integrated circuit device is not high or its operating speed is high.

[Means to solve the problem]

According to the present invention, this object is achieved by providing a base body consisting of a semiconductor region having one conductivity type and a semiconductor region having a lower impurity concentration, and a semiconductor region having the other conductivity type diffused from the surface of the base body on the side of the low impurity concentration semiconductor region. an epitaxial layer of the other conductivity type grown on the surface in which the buried layer of the substrate is diffused; A wafer for an integrated circuit device is constituted by a junction separation layer which is diffused in a conductive type and divides the epitaxial layer into a plurality of junction-separated partial regions, and each portion of the wafer is divided from the epitaxial layer by the junction separation layer. This is accomplished by building circuit elements that make up an integrated circuit within the area.

[Effect]

The present invention successfully reduces mutual interference between circuit elements constituting an integrated circuit device by increasing the impedance value of the first interference path, that is, the interference path through the buried layer and substrate for each partial region. This is what I did.

Of course, another cause of interference is the second interference path mentioned above, but this always goes through the epitaxial layer and the junction separation layer, and the epitaxial layer has a relatively low impurity concentration and is The resistance value is high, and since the depletion layer of the pn junction between it and the junction separation layer easily extends toward the epitaxial layer, the junction capacitance is also relatively small, so the frequency at which the impedance value of this second interference path decreases is Compared to this, both the embedded layer and the substrate in the first interference path have low resistance values and the junction capacitance between them is also high, so the frequency at which the impedance of the first interference path decreases is relatively high. is usually an order of magnitude or more lower than the second interference path.

The buried layer in the first interference path not only serves as a semiconductor layer connected to the terminal of the circuit element as shown in FIG. For this reason, it is made into a highly impurity concentration layer, so its resistance value is always low.
In integrated circuit devices, this resistance value cannot be lowered.In principle, it is possible to lower the impurity concentration of the substrate in the first interference path and increase the resistance value. The CZ method (
It is necessary to use single-crystal silicon produced by the Chickralski method, and with this current manufacturing method, it is difficult to put into practical use a product with low impurity concentration and high resistance.

The present invention focuses on this point, and uses a substrate in which a semiconductor region having one conductivity type as described above is combined with a semiconductor region having the same conductivity type and a lower impurity concentration, such as an epitaxial layer region. is used instead of the conventional substrate. Thereafter, in the same way as before, a buried layer of the other conductivity type is diffused on the surface, an epitaxial layer is grown in the other conductivity type, and a junction separation layer of one conductivity type is grown from the surface with low impurity impurity of the substrate. Multiple epitaxial layers diffused to conductively connect to the doped semiconductor region? (2) A wafer is made that is bonded and separated into regions, and circuit elements are built into each of the regions.

This is equivalent to using a substrate with low impurity concentration and high resistance in the first interference path, increasing the resistance value and reducing the junction capacitance of the pn junction with the buried layer. In this way, the frequency at which the impedance value of the first interference path decreases can be increased above the frequency for the second interference path, thereby reducing mutual interference between circuit elements.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIG.

This figure shows an integrated circuit device according to the present invention in which the same vertical field effect transistors as in the case of FIG. ), and corresponding parts to those in FIG. 3 are given the same reference numerals.

FIG. 1(a) shows a substrate 3 for an integrated circuit device according to the present invention, in which a semiconductor region 1 constituting the substrate corresponds to a conventional substrate, which has a resistivity of several tens of tens of yen by the usual CZ method. Ω
Single crystal silicon of about C111 is used, and its conductivity type is, for example, p-type as shown in the figure. In this example, the low impurity concentration semiconductor region 2, which is another component of the substrate 3, has a low impurity concentration of about several hundred Ωl, which is the same p-type as on the semiconductor region 1, but whose resistivity is an order of magnitude higher than that of the low impurity concentration semiconductor region 2. A grown epitaxial layer is used. The thickness of this low impurity concentration semiconductor region 2 varies depending on the operating voltage of the integrated circuit device, but is usually several tens of microns.For example, the thickness of the n-type epitaxial layer grown thereon is 20 to 30-
In this case, the thickness is about twice that, 40 to 50μ.

Next, an oxide film 4 is applied to the surface of the low impurity concentration semiconductor region 2 of the base 3, and using this as a mask, p-type impurities are introduced into the buried isolation layer 5 and n-type impurities are introduced into the buried layer 6. , are thermally diffused so as to obtain sheet resistance values of about 10 to 20 Ω/hole to form the state shown in FIG. 1(a).

FIG. 1) shows a wafer 9 for an integrated circuit device according to the invention. To achieve this state, first see (a) in the same figure.
After removing the oxide film 4 on the substrate 3, an n-type epitaxial layer 7 is grown at an impurity concentration such that the resistivity becomes around 10ΩC1. When a high voltage vertical field effect transistor is fabricated in an integrated circuit device as in this example, the thickness of the epitaxial layer 7 is approximately 20 to 301 Em. Next, a p-type junction isolation layer 8 is formed from the surface of this epitaxial layer 7 using the newly applied oxide lI4 as a mask.
The epitaxial layer 7 is junction-separated into a plurality of partial regions by deeply diffusing it at a relatively high impurity concentration so that its sheet resistance is about 10 to 20 Ω/hole until it connects with the buried isolation layer 5 as shown in the figure. do. This is the state shown in Fig. 1 et al.).

In the present invention, a circuit element or a group of circuit elements constituting an integrated circuit is fabricated in each partial area of the wafer produced as described above. In this example, each subregion contains the information shown in Figure 1 (
As shown in C), the n-type buried N6 under the 0 partial region in which a single n-channel vertical field effect transistor T is built using the n-type epitaxial layer 7 as the drain region is as follows: In addition to the usual role of perfecting the junction isolation, it also plays the role of connecting the drain region to the drain terminal together with the connection layer 11, so when fabricating the transistor, it is necessary to make an n-type connection from the surface of the epitaxial layer 7. A drain system is first formed by deeply diffusing layer 11 with high impurity concentration and connecting it to buried layer 6.

Next, a p-type outer channel forming layer 12 is diffused in a circular pattern with a relatively low impurity concentration of about 1011 atoms/d to a depth of about 5 to 10-1, and then the inner epitaxial layer 7 is formed. The surface is covered with a gate oxide film 13 as thin as about 0.1, and a gate 1 made of polycrystalline silicon or the like is formed on top of it.
4 will be provided. Next, the p-type inner channel forming layer 15 and the n-type source layer 16 are sequentially diffused in an annular pattern using the conventional ion implantation method using the gate electrode 14 as a mask. At this time, the inner channel forming layer 1
The source layer 16 is diffused to a depth of 1 to 2 - with a high impurity concentration of 10111 atoms/d or more.

This completes the semiconductor layer diffusion process, so let's move on to the game)
An oxide film 17 is applied over the entire surface including the top of the oxide film 14, and an electrode film 18 is provided by opening windows at important points thereof, and then terminals S, D and G for the transistor T are led out as shown in the figure. Note that the electrode film 18 for the source terminal S is the outer channel forming layer 1.
2 and source layer 16 to short-circuit both layers.

Further, a ground terminal E is led out from the electrode film 18 that is in conductive contact with the junction separation layer 8 . In this vertical field effect transistor T, the p-type inner channel forming layer 1 under the gate electrode 14 is
An n-type channel is formed on the surface of 5. A current with electrons as carriers flows through the source layer 1 connected to the source terminal S.
6 passes through this channel into an epitaxial layer 7 serving as a drain region, passes therein in the vertical direction, and then is guided to the drain terminal via the buried layer 6 and the connection layer 11.

In the above-described integrated circuit device according to the present invention, there are two interference paths shown in FIG. 2 between the circuit elements built in different partial areas, but the first interference path among these exists. In the case of the present invention, is formed via the low impurity concentration semiconductor region 2. The resistance component of this interference path is different from the resistance component of the second interference path via the junction separation layer 8 because the value of the resistance R of the low impurity concentration semiconductor region 2 is one order of magnitude higher than that of the conventional substrate. It will be about the same size or slightly larger.

In addition, the junction capacitance C between the low impurity concentration semiconductor region 2 and the buried layer 6, which is the capacitance component, becomes much smaller than before because the depletion layer from the junction tends to extend toward the high resistance former. , the junction capacitance between the junction isolation layer 8 and the epitaxial layer 7 in the second interference path is about the same or lower.

Therefore, in the integrated circuit device according to the present invention, the operating frequency at which the impedance value of the first interference path decreases to such an extent that interference actually occurs is approximately the same as or slightly higher than the frequency for the second interference path.

In this manner, by increasing the impedance value of the first interference path, which has conventionally been the main cause of interference, the present invention can reduce the risk of mutual interference occurring between circuit elements of an integrated circuit device.

In the above embodiments, the circuit elements are vertical field effect transistors, but the present invention is not limited to this, and can be appropriately implemented even when the circuit elements are bipolar transistors or the like.

〔Effect of the invention〕

As explained above, in the present invention, there is a base body consisting of a semiconductor region having one conductivity type and a semiconductor region 61 having a lower impurity concentration, and a semiconductor region having the other conductivity type diffused from the surface of the base body on the low impurity concentration semiconductor region side. a buried layer of a conductivity type and an epitaxial layer of the other conductivity type grown on the surface of the substrate in which the buried layer is diffused, such that the surface of the epitaxial layer is conductively connected to the lightly doped semiconductor region of the substrate. A wafer for an integrated circuit device is formed by a junction separation layer that is diffused with one conductivity type and divides the epitaxial layer into a plurality of junction-separated subregions, and then the epitaxial layer of this wafer is divided by the junction separation layer. Since the circuit elements constituting the integrated circuit are built into each partial region, the impedance value of the interference path passing through the buried layer and the low impurity concentration semiconductor region under the partial region can be increased. As a result, the wave number of the operation that causes interference between the circuit elements of an integrated circuit device that is divided into partial areas and manufactured is increased by, for example, one order of magnitude compared to the conventional one, thereby effectively reducing the degree of interference or substantially eliminating its risk. The top can be removed.

The present invention is suitable for integrated circuit devices that operate in a high frequency range and incorporate a large number of output transistors that handle high voltage and large currents.For example, when applied to an integrated circuit for driving a display panel, so-called crosstalk that is likely to occur between pixels It is possible to improve the image quality by reducing the number of images and making the display clearer.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 relate to the present invention; FIG. 1 is a partially enlarged sectional view showing an embodiment of an integrated circuit device according to the present invention in each of its main manufacturing steps; FIG. 2 is an equivalent circuit diagram of the interference path formed between the circuit elements. FIG. 3 is a partially enlarged sectional view of a conventional integrated circuit device. In the figure, 1: semiconductor region or substrate constituting the base body, 2: low impurity semiconductor region or epitaxial layer constituting the base body, 3: base body, 4 dioxide film, 5: buried isolation layer, 6:
Buried layer, 7: Epitaxial layer or partial region, 8:
Joint bone MN, 9: wafer, 11 Nidorain connection layer, 12
: outer channel forming layer, 13: gate oxide film, 14: gate, 15: inner channel forming layer, 16: source layer, 1
7: Oxide film under electrode film, 18: Electrode film, C: Junction capacitance between low impurity concentration semiconductor region and buried layer, C: Junction capacitance between epitaxial layer and junction separation layer, D Nidrain terminal, E: Ground terminal or ground potential point, G: Gate terminal, S: Source terminal, L: Load, R: Resistance of low impurity 4 degree semiconductor region, T: Circuit element or vertical field effect transistor, ■: Power supply voltage or power supply is the potential point. Figure 12 ↑l ↑Eng.

Claims (1)

[Claims] A base body consisting of a semiconductor region of one conductivity type and a semiconductor region with a lower impurity concentration, a buried layer of the other conductivity type diffused from the surface of the base body on the low impurity concentration semiconductor region side, and a buried layer of the base body. an epitaxial layer of the other conductivity type grown on the surface in which the doped layer is diffused, and a plurality of epitaxial layers diffused in one conductivity type such that the surface of the epitaxial layer is conductively connected to the low impurity concentration semiconductor region of the substrate. A wafer for an integrated circuit device is constructed by a junction separation layer that is divided into junction-separated partial regions, and a circuit that constitutes an integrated circuit in each partial region that is divided from the epitaxial layer of this wafer by the junction separation layer. An integrated circuit device characterized by having built-in elements.